From mboxrd@z Thu Jan 1 00:00:00 1970 From: Roger Pau =?iso-8859-1?Q?Monn=E9?= Subject: Re: [PATCH V3 10/29] vtd: add and align register definitions Date: Thu, 19 Oct 2017 11:21:35 +0100 Message-ID: <20171019102135.fhdjs4if45ylzmqq@dhcp-3-128.uk.xensource.com> References: <1506049330-11196-1-git-send-email-tianyu.lan@intel.com> <1506049330-11196-11-git-send-email-tianyu.lan@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <1506049330-11196-11-git-send-email-tianyu.lan@intel.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: Lan Tianyu Cc: tim@xen.org, kevin.tian@intel.com, sstabellini@kernel.org, wei.liu2@citrix.com, konrad.wilk@oracle.com, George.Dunlap@eu.citrix.com, andrew.cooper3@citrix.com, ian.jackson@eu.citrix.com, xen-devel@lists.xen.org, jbeulich@suse.com, Chao Gao List-Id: xen-devel@lists.xenproject.org T24gVGh1LCBTZXAgMjEsIDIwMTcgYXQgMTE6MDE6NTFQTSAtMDQwMCwgTGFuIFRpYW55dSB3cm90 ZToKPiBGcm9tOiBDaGFvIEdhbyA8Y2hhby5nYW9AaW50ZWwuY29tPgo+IAo+IE5vIGZ1bmN0aW9u YWwgY2hhbmdlcy4KPiAKPiBTaWduZWQtb2ZmLWJ5OiBDaGFvIEdhbyA8Y2hhby5nYW9AaW50ZWwu Y29tPgo+IFNpZ25lZC1vZmYtYnk6IExhbiBUaWFueXUgPHRpYW55dS5sYW5AaW50ZWwuY29tPgoK UmV2aWV3ZWQtYnk6IFJvZ2VyIFBhdSBNb25uw6kgPHJvZ2VyLnBhdUBjaXRyaXguY29tPgoKV291 bGQgaGF2ZSBiZWVuIG5pY2UgdG8gbWF5YmUgc3BsaXQgdGhpcyBpbnRvIHR3bywgb25lIHBhdGNo IHRoYXQKc2ltcGx5IGZpeGVzIHRoZSBhbGlnbm1lbnQgYW5kIGFub3RoZXIgb25lIHRoYXQgaW50 cm9kdWNlcyB0aGUgbmV3CmRlZmluZXMgKG9yIGV2ZW4gaW50cm9kdWNlIHRoZSBuZXcgZGVmaW5l cyB3aGVuIHRoZXkgYXJlIGFjdHVhbGx5Cm5lZWRlZCkuCgpUaGFua3MsIFJvZ2VyLgoKX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVsIG1haWxp bmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVuLm9yZwpodHRwczovL2xpc3RzLnhlbi5vcmcveGVu LWRldmVsCg==