From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932286AbdJYXiO (ORCPT ); Wed, 25 Oct 2017 19:38:14 -0400 Received: from 5pmail.ess.barracuda.com ([64.235.154.203]:55642 "EHLO 5pmail.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752040AbdJYXiJ (ORCPT ); Wed, 25 Oct 2017 19:38:09 -0400 From: Paul Burton To: Jason Cooper , Marc Zyngier , Thomas Gleixner CC: , , Paul Burton Subject: [PATCH 0/8] irqchip: mips-gic: Cleanups, fixes, prep for multi-cluster Date: Wed, 25 Oct 2017 16:37:22 -0700 Message-ID: <20171025233730.22225-1-paul.burton@mips.com> X-Mailer: git-send-email 2.14.3 MIME-Version: 1.0 Content-Type: text/plain X-BESS-ID: 1508974659-321459-28741-58358-7 X-BESS-VER: 2017.12-r1709122024 X-BESS-Apparent-Source-IP: 12.201.5.28 X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.186295 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS59374 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series continues cleaning & fixing up the MIPS GIC irqchip driver whilst laying groundwork to support multi-cluster systems. Patch 1 refactors in order to reduce some duplication and prepare us for the following patches. Patches 2-4 move per-CPU GIC configuration away from being performed all at once when the driver is probed or when interrupts are masked & unmasked, instead performing configuration as CPUs are brought online. This allows us to support reconfiguring after clusters are powered down & back up, generally cleans up and fixes bugs in the process. Patch 5 makes use of num_possible_cpus() to reserve IPIs, rather than the gic_vpes variable. This prepares us for multi-cluster in which gic_vpes is mostly meaningless since it only reflects the local cluster, and it generally makes more sense to use the more standard num_possible_cpus(). Patch 6 removes the now unused gic_vpes variable. Patch 7 is a general clean up but also prepares us for later patches as described in its commit message. Patch 8 is a general clean up marking some variables static. This series by itself continues along the path towards supporting multi-cluster systems such as the MIPS I6500, but does not yet get us the whole way there. If you wish to see my current work in progress which builds out multi-cluster support atop these patches then that can be found in the multicluster branch of: git://git.linux-mips.org/pub/scm/paul/linux.git Or browsed at: https://git.linux-mips.org/cgit/paul/linux.git/log/?h=multicluster This series applies cleanly atop v4.14-rc6. Paul Burton (8): irqchip: mips-gic: Inline gic_local_irq_domain_map() irqchip: mips-gic: Use irq_cpu_online to (un)mask all-VP(E) IRQs irqchip: mips-gic: Mask local interrupts when CPUs come online irqchip: mips-gic: Configure EIC when CPUs come online irqchip: mips-gic: Use num_possible_cpus() to reserve IPIs irqchip: mips-gic: Remove gic_vpes variable irqchip: mips-gic: Share register writes in gic_set_type() irqchip: mips-gic: Make IPI bitmaps static drivers/irqchip/irq-mips-gic.c | 213 ++++++++++++++++++++++------------------- 1 file changed, 114 insertions(+), 99 deletions(-) -- 2.14.3 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from 5pmail.ess.barracuda.com ([64.235.154.203]:53295 "EHLO 5pmail.ess.barracuda.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S23990901AbdJYXiHGxHyS (ORCPT ); Thu, 26 Oct 2017 01:38:07 +0200 From: Paul Burton Subject: [PATCH 0/8] irqchip: mips-gic: Cleanups, fixes, prep for multi-cluster Date: Wed, 25 Oct 2017 16:37:22 -0700 Message-ID: <20171025233730.22225-1-paul.burton@mips.com> MIME-Version: 1.0 Content-Type: text/plain Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: Jason Cooper , Marc Zyngier , Thomas Gleixner Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Paul Burton Message-ID: <20171025233722.GV-Sz-4C9w-5rdgcJgtOtdLBQ1KEuaqnuLejqEYNhAI@z> This series continues cleaning & fixing up the MIPS GIC irqchip driver whilst laying groundwork to support multi-cluster systems. Patch 1 refactors in order to reduce some duplication and prepare us for the following patches. Patches 2-4 move per-CPU GIC configuration away from being performed all at once when the driver is probed or when interrupts are masked & unmasked, instead performing configuration as CPUs are brought online. This allows us to support reconfiguring after clusters are powered down & back up, generally cleans up and fixes bugs in the process. Patch 5 makes use of num_possible_cpus() to reserve IPIs, rather than the gic_vpes variable. This prepares us for multi-cluster in which gic_vpes is mostly meaningless since it only reflects the local cluster, and it generally makes more sense to use the more standard num_possible_cpus(). Patch 6 removes the now unused gic_vpes variable. Patch 7 is a general clean up but also prepares us for later patches as described in its commit message. Patch 8 is a general clean up marking some variables static. This series by itself continues along the path towards supporting multi-cluster systems such as the MIPS I6500, but does not yet get us the whole way there. If you wish to see my current work in progress which builds out multi-cluster support atop these patches then that can be found in the multicluster branch of: git://git.linux-mips.org/pub/scm/paul/linux.git Or browsed at: https://git.linux-mips.org/cgit/paul/linux.git/log/?h=multicluster This series applies cleanly atop v4.14-rc6. Paul Burton (8): irqchip: mips-gic: Inline gic_local_irq_domain_map() irqchip: mips-gic: Use irq_cpu_online to (un)mask all-VP(E) IRQs irqchip: mips-gic: Mask local interrupts when CPUs come online irqchip: mips-gic: Configure EIC when CPUs come online irqchip: mips-gic: Use num_possible_cpus() to reserve IPIs irqchip: mips-gic: Remove gic_vpes variable irqchip: mips-gic: Share register writes in gic_set_type() irqchip: mips-gic: Make IPI bitmaps static drivers/irqchip/irq-mips-gic.c | 213 ++++++++++++++++++++++------------------- 1 file changed, 114 insertions(+), 99 deletions(-) -- 2.14.3