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From: Borislav Petkov <bp@alien8.de>
To: Gayatri Kammela <gayatri.kammela@intel.com>
Cc: linux-kernel@vger.kernel.org, x86@kernel.org,
	hpa@linux.intel.com, Thomas Gleixner <tglx@linutronix.de>,
	Andi Kleen <andi.kleen@intel.com>,
	Ravi Shankar <ravi.v.shankar@intel.com>,
	Fenghua Yu <fenghua.yu@intel.com>,
	Ricardo Neri <ricardo.neri@intel.com>,
	Yang Zhong <yang.zhong@intel.com>
Subject: Re: [PATCH v2]  x86/cpufeatures: Enable new SSE/AVX/AVX512 cpu features
Date: Tue, 31 Oct 2017 11:06:19 +0100	[thread overview]
Message-ID: <20171031100619.q5asiqkbuqi2cecp@pd.tnic> (raw)
In-Reply-To: <1509412829-23380-1-git-send-email-gayatri.kammela@intel.com>

On Mon, Oct 30, 2017 at 06:20:29PM -0700, Gayatri Kammela wrote:
> Add a few new SSE/AVX/AVX512 instruction groups/features for enumeration
> in /proc/cpuinfo: AVX512_VBMI2, GFNI, VAES, VPCLMULQDQ, AVX512_VNNI,
> AVX512_BITALG.
> 
> CPUID.(EAX=7,ECX=0):ECX[bit 6]  AVX512_VBMI2
> CPUID.(EAX=7,ECX=0):ECX[bit 8]  GFNI
> CPUID.(EAX=7,ECX=0):ECX[bit 9]  VAES
> CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
> CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512_VNNI
> CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG
> 
> Detailed information of cpuid bits for these features can be found
> in the Intel Architecture Instruction Set Extensions and Future Features
> Programming Interface document (refer to Table 1-1. and Table 1-2.).
> A copy of this document is available at
> https://bugzilla.kernel.org/show_bug.cgi?id=197239
> 
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Andi Kleen <andi.kleen@intel.com>
> Cc: Ravi Shankar <ravi.v.shankar@intel.com>
> Cc: Fenghua Yu <fenghua.yu@intel.com>
> Cc: Ricardo Neri <ricardo.neri@intel.com>
> Cc: Yang Zhong <yang.zhong@intel.com>
> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
> ---
> Changes since v1:
> 1) Rebased against the tip tree and so removed all the setup_clear flags
> 
>  arch/x86/include/asm/cpufeatures.h | 6 ++++++
>  arch/x86/kernel/cpu/cpuid-deps.c   | 6 ++++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 401a70992060..b0556f882aa8 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -299,6 +299,12 @@
>  #define X86_FEATURE_AVX512VBMI  (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/

So we have previous AVX512 feature bits which do not separate AVX512
with a "_" but the new ones do. I think we should unify this and the SDM
should be fixed too.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

  reply	other threads:[~2017-10-31 10:06 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-31  1:20 [PATCH v2] x86/cpufeatures: Enable new SSE/AVX/AVX512 cpu features Gayatri Kammela
2017-10-31 10:06 ` Borislav Petkov [this message]
2017-10-31 18:02   ` Yu, Fenghua
2017-10-31 18:25     ` Borislav Petkov
2017-10-31 18:25   ` Yu, Fenghua
2017-10-31 18:32     ` Borislav Petkov
2017-10-31 19:37       ` Yu, Fenghua
2017-10-31 20:02         ` Borislav Petkov
2017-10-31 12:05 ` [tip:x86/fpu] x86/cpufeatures: Enable new SSE/AVX/AVX512 CPU features tip-bot for Gayatri Kammela

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