* [PATCH] drm/i915: Implement ReadHitWriteOnlyDisable.
@ 2017-11-01 16:32 Rafael Antognolli
2017-11-01 19:20 ` ✓ Fi.CI.BAT: success for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Rafael Antognolli @ 2017-11-01 16:32 UTC (permalink / raw)
To: intel-gfx
The workaround for this is described as:
"if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
RenderSurfaceState.Num_Multisamples == 1, set 0x7010[14] = 1"
So it looks like the userspace should be responsible for setting these,
based on the number of multisamples dependency. However, the register
that controls RCC clock gating is not a context register, and cannot be
set by userspace.
Since we would end up setting one or another based on the number of
multisamples anyway, it seems harmless to just set both all the time.
This change (specially the GEN10_READ_HIT_WRITEONLY_DISABLE bit)
improves CNL stability by avoiding some of the hangs seen in the
platform.
Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8c775e96b4e4..d9a65cebefaa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3837,6 +3837,7 @@ enum {
*/
#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
#define SARBUNIT_CLKGATE_DIS (1 << 5)
+#define RCCUNIT_CLKGATE_DIS (1 << 7)
/*
* Display engine regs
@@ -7016,6 +7017,7 @@ enum {
#define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
# define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
+# define GEN10_READ_HIT_WRITEONLY_DISABLE (1<<14)
#define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
# define GEN9_PBE_COMPRESSED_HASH_SELECTION (1<<13)
# define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index f31f2d6384c3..0d8e25a4623a 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1320,6 +1320,11 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
+ /* ReadHitWriteOnlyDisable: cnl */
+ WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
+ GEN10_READ_HIT_WRITEONLY_DISABLE);
+ WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);
+
/* WaEnablePreemptionGranularityControlByUMD:cnl */
I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
--
2.13.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Implement ReadHitWriteOnlyDisable.
2017-11-01 16:32 [PATCH] drm/i915: Implement ReadHitWriteOnlyDisable Rafael Antognolli
@ 2017-11-01 19:20 ` Patchwork
2017-11-01 20:56 ` ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2017-11-01 19:20 UTC (permalink / raw)
To: Rafael Antognolli; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Implement ReadHitWriteOnlyDisable.
URL : https://patchwork.freedesktop.org/series/32991/
State : success
== Summary ==
Series 32991v1 drm/i915: Implement ReadHitWriteOnlyDisable.
https://patchwork.freedesktop.org/api/1.0/series/32991/revisions/1/mbox/
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:449s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:457s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:380s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:531s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:277s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:505s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:508s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:510s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:491s
fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:567s
fi-cnl-y total:217 pass:196 dwarn:0 dfail:0 fail:0 skip:20
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:431s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:264s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:590s
fi-glk-dsi total:289 pass:258 dwarn:0 dfail:0 fail:1 skip:30 time:495s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:432s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:429s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:428s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:499s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:468s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:500s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:573s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:480s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:590s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:572s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:459s
fi-skl-6600u total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:600s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:650s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:520s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:499s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:457s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:572s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:418s
7da46c0a019ebaec3f67a8a6ccc60a56c2d521b1 drm-tip: 2017y-11m-01d-17h-32m-50s UTC integration manifest
e0e862794bb5 drm/i915: Implement ReadHitWriteOnlyDisable.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6300/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915: Implement ReadHitWriteOnlyDisable.
2017-11-01 16:32 [PATCH] drm/i915: Implement ReadHitWriteOnlyDisable Rafael Antognolli
2017-11-01 19:20 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-11-01 20:56 ` Patchwork
2017-11-01 21:14 ` Rodrigo Vivi
2017-11-01 21:11 ` [PATCH] " Rodrigo Vivi
2017-11-01 21:50 ` ✓ Fi.CI.BAT: success for " Patchwork
3 siblings, 1 reply; 7+ messages in thread
From: Patchwork @ 2017-11-01 20:56 UTC (permalink / raw)
To: Rafael Antognolli; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Implement ReadHitWriteOnlyDisable.
URL : https://patchwork.freedesktop.org/series/32991/
State : failure
== Summary ==
Test kms_flip:
Subgroup plain-flip-fb-recreate-interruptible:
pass -> FAIL (shard-hsw) fdo#100368
Subgroup modeset-vs-vblank-race-interruptible:
fail -> PASS (shard-hsw) fdo#103060
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
Test perf:
Subgroup oa-exponents:
fail -> PASS (shard-hsw) fdo#102254
Test drv_module_reload:
Subgroup basic-reload:
pass -> DMESG-WARN (shard-hsw) fdo#102707
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-pri-indfb-multidraw:
pass -> FAIL (shard-hsw)
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
shard-hsw total:2539 pass:1430 dwarn:2 dfail:0 fail:10 skip:1097 time:9227s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6300/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/i915: Implement ReadHitWriteOnlyDisable.
2017-11-01 16:32 [PATCH] drm/i915: Implement ReadHitWriteOnlyDisable Rafael Antognolli
2017-11-01 19:20 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-11-01 20:56 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2017-11-01 21:11 ` Rodrigo Vivi
2017-11-01 21:37 ` Rafael Antognolli
2017-11-01 21:50 ` ✓ Fi.CI.BAT: success for " Patchwork
3 siblings, 1 reply; 7+ messages in thread
From: Rodrigo Vivi @ 2017-11-01 21:11 UTC (permalink / raw)
To: Rafael Antognolli; +Cc: intel-gfx
On Wed, Nov 01, 2017 at 04:32:35PM +0000, Rafael Antognolli wrote:
> The workaround for this is described as:
>
> "if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
> RenderSurfaceState.Num_Multisamples == 1, set 0x7010[14] = 1"
>
> So it looks like the userspace should be responsible for setting these,
> based on the number of multisamples dependency. However, the register
> that controls RCC clock gating is not a context register, and cannot be
> set by userspace.
>
> Since we would end up setting one or another based on the number of
> multisamples anyway, it seems harmless to just set both all the time.
>
> This change (specially the GEN10_READ_HIT_WRITEONLY_DISABLE bit)
I wonder if we shouldn't stay only with this bit. For me it looks like
one or another.
> improves CNL stability by avoiding some of the hangs seen in the
> platform.
But this is what matters. If this is the safest option for us
let's do it.
>
> Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8c775e96b4e4..d9a65cebefaa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3837,6 +3837,7 @@ enum {
> */
> #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> #define SARBUNIT_CLKGATE_DIS (1 << 5)
> +#define RCCUNIT_CLKGATE_DIS (1 << 7)
>
> /*
> * Display engine regs
> @@ -7016,6 +7017,7 @@ enum {
> #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
> # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
> # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
> +# define GEN10_READ_HIT_WRITEONLY_DISABLE (1<<14)
I don't believe you need to redefine this.
It is same as GEN9_RHWO_OPTIMIZATION_DISABLE.
RCC Read Hit Write Only Optimization Disabled, SKL+ o spec.
> #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
> # define GEN9_PBE_COMPRESSED_HASH_SELECTION (1<<13)
> # define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index f31f2d6384c3..0d8e25a4623a 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1320,6 +1320,11 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
> WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>
> + /* ReadHitWriteOnlyDisable: cnl */
I was going to complain about the name but I saw on bspec it is really
ReadHitWriteOnlyDisable while on wa_database it is WaReadHitWriteOnlyDisable
I would tend to prefer the second one, but with the first one the search on Bspec works
and search on wa_database also works... while second one it would be found on BSpec.
So let it be: ReadHitWriteOnlyDisable
Thanks,
Rodrigo.
> + WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> + GEN10_READ_HIT_WRITEONLY_DISABLE);
> + WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);
> +
> /* WaEnablePreemptionGranularityControlByUMD:cnl */
> I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
> _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
> --
> 2.13.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: ✗ Fi.CI.IGT: failure for drm/i915: Implement ReadHitWriteOnlyDisable.
2017-11-01 20:56 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2017-11-01 21:14 ` Rodrigo Vivi
0 siblings, 0 replies; 7+ messages in thread
From: Rodrigo Vivi @ 2017-11-01 21:14 UTC (permalink / raw)
To: intel-gfx
On Wed, Nov 01, 2017 at 08:56:59PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Implement ReadHitWriteOnlyDisable.
> URL : https://patchwork.freedesktop.org/series/32991/
> State : failure
>
> == Summary ==
>
> Test kms_flip:
> Subgroup plain-flip-fb-recreate-interruptible:
> pass -> FAIL (shard-hsw) fdo#100368
> Subgroup modeset-vs-vblank-race-interruptible:
> fail -> PASS (shard-hsw) fdo#103060
> Test kms_setmode:
> Subgroup basic:
> fail -> PASS (shard-hsw) fdo#99912
> Test perf:
> Subgroup oa-exponents:
> fail -> PASS (shard-hsw) fdo#102254
> Test drv_module_reload:
> Subgroup basic-reload:
> pass -> DMESG-WARN (shard-hsw) fdo#102707
> Test kms_frontbuffer_tracking:
> Subgroup fbc-1p-pri-indfb-multidraw:
> pass -> FAIL (shard-hsw)
A false positive here. I triggered the patch retest. Altough we don't
cnl on full igt run anyways...
>
> fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
> fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
> fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
> fdo#102254 https://bugs.freedesktop.org/show_bug.cgi?id=102254
> fdo#102707 https://bugs.freedesktop.org/show_bug.cgi?id=102707
>
> shard-hsw total:2539 pass:1430 dwarn:2 dfail:0 fail:10 skip:1097 time:9227s
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6300/shards.html
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/i915: Implement ReadHitWriteOnlyDisable.
2017-11-01 21:11 ` [PATCH] " Rodrigo Vivi
@ 2017-11-01 21:37 ` Rafael Antognolli
0 siblings, 0 replies; 7+ messages in thread
From: Rafael Antognolli @ 2017-11-01 21:37 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Wed, Nov 01, 2017 at 02:11:05PM -0700, Rodrigo Vivi wrote:
> On Wed, Nov 01, 2017 at 04:32:35PM +0000, Rafael Antognolli wrote:
> > The workaround for this is described as:
> >
> > "if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
> > RenderSurfaceState.Num_Multisamples == 1, set 0x7010[14] = 1"
> >
> > So it looks like the userspace should be responsible for setting these,
> > based on the number of multisamples dependency. However, the register
> > that controls RCC clock gating is not a context register, and cannot be
> > set by userspace.
> >
> > Since we would end up setting one or another based on the number of
> > multisamples anyway, it seems harmless to just set both all the time.
> >
> > This change (specially the GEN10_READ_HIT_WRITEONLY_DISABLE bit)
>
> I wonder if we shouldn't stay only with this bit. For me it looks like
> one or another.
I would say we need at least the GEN10_READ_HIT_WRITEONLY_DISABLE bit, and then
we can decide if we are adding the other one or not. Within the same
program (I think sometimes even within a single draw call), it's
possible that we have some surfaces that are multisampled while others
are not, so in that case we would probably have to set both anyway.
However, I don't have a test case that proves that the workaround for
the multisampled case is required...
> > improves CNL stability by avoiding some of the hangs seen in the
> > platform.
>
> But this is what matters. If this is the safest option for us
> let's do it.
>
> >
> > Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 2 ++
> > drivers/gpu/drm/i915/intel_engine_cs.c | 5 +++++
> > 2 files changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 8c775e96b4e4..d9a65cebefaa 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3837,6 +3837,7 @@ enum {
> > */
> > #define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> > #define SARBUNIT_CLKGATE_DIS (1 << 5)
> > +#define RCCUNIT_CLKGATE_DIS (1 << 7)
> >
> > /*
> > * Display engine regs
> > @@ -7016,6 +7017,7 @@ enum {
> > #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010)
> > # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
> > # define GEN9_RHWO_OPTIMIZATION_DISABLE (1<<14)
> > +# define GEN10_READ_HIT_WRITEONLY_DISABLE (1<<14)
>
> I don't believe you need to redefine this.
> It is same as GEN9_RHWO_OPTIMIZATION_DISABLE.
>
> RCC Read Hit Write Only Optimization Disabled, SKL+ o spec.
Oh, I haven't noticed that! Will fix it in the next version...
> > #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014)
> > # define GEN9_PBE_COMPRESSED_HASH_SELECTION (1<<13)
> > # define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1<<12)
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index f31f2d6384c3..0d8e25a4623a 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1320,6 +1320,11 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
> > WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> > GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
> >
> > + /* ReadHitWriteOnlyDisable: cnl */
>
> I was going to complain about the name but I saw on bspec it is really
> ReadHitWriteOnlyDisable while on wa_database it is WaReadHitWriteOnlyDisable
>
> I would tend to prefer the second one, but with the first one the search on Bspec works
> and search on wa_database also works... while second one it would be found on BSpec.
> So let it be: ReadHitWriteOnlyDisable
>
> Thanks,
> Rodrigo.
>
> > + WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> > + GEN10_READ_HIT_WRITEONLY_DISABLE);
> > + WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);
> > +
>
> > /* WaEnablePreemptionGranularityControlByUMD:cnl */
> > I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
> > _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
> > --
> > 2.13.6
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Implement ReadHitWriteOnlyDisable.
2017-11-01 16:32 [PATCH] drm/i915: Implement ReadHitWriteOnlyDisable Rafael Antognolli
` (2 preceding siblings ...)
2017-11-01 21:11 ` [PATCH] " Rodrigo Vivi
@ 2017-11-01 21:50 ` Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2017-11-01 21:50 UTC (permalink / raw)
To: Rafael Antognolli; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Implement ReadHitWriteOnlyDisable.
URL : https://patchwork.freedesktop.org/series/32991/
State : success
== Summary ==
Series 32991v1 drm/i915: Implement ReadHitWriteOnlyDisable.
https://patchwork.freedesktop.org/api/1.0/series/32991/revisions/1/mbox/
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:447s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:456s
fi-blb-e6850 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:382s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:543s
fi-bwr-2160 total:289 pass:183 dwarn:0 dfail:0 fail:0 skip:106 time:276s
fi-bxt-dsi total:289 pass:259 dwarn:0 dfail:0 fail:0 skip:30 time:508s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:503s
fi-byt-j1900 total:289 pass:253 dwarn:1 dfail:0 fail:0 skip:35 time:508s
fi-byt-n2820 total:289 pass:249 dwarn:1 dfail:0 fail:0 skip:39 time:490s
fi-cfl-s total:289 pass:253 dwarn:4 dfail:0 fail:0 skip:32 time:557s
fi-cnl-y total:217 pass:196 dwarn:0 dfail:0 fail:0 skip:20
fi-elk-e7500 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:442s
fi-gdg-551 total:289 pass:178 dwarn:1 dfail:0 fail:1 skip:109 time:263s
fi-glk-1 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:585s
fi-glk-dsi total:289 pass:258 dwarn:0 dfail:0 fail:1 skip:30 time:492s
fi-hsw-4770 total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:430s
fi-hsw-4770r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:430s
fi-ilk-650 total:289 pass:228 dwarn:0 dfail:0 fail:0 skip:61 time:425s
fi-ivb-3520m total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:500s
fi-ivb-3770 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:470s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:496s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:575s
fi-kbl-7567u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:486s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:586s
fi-pnv-d510 total:289 pass:222 dwarn:1 dfail:0 fail:0 skip:66 time:567s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:459s
fi-skl-6600u total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:600s
fi-skl-6700hq total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:649s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:520s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:502s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:458s
fi-snb-2520m total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:571s
fi-snb-2600 total:289 pass:249 dwarn:0 dfail:0 fail:0 skip:40 time:423s
7da46c0a019ebaec3f67a8a6ccc60a56c2d521b1 drm-tip: 2017y-11m-01d-17h-32m-50s UTC integration manifest
b474a1ebd14f drm/i915: Implement ReadHitWriteOnlyDisable.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_6306/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2017-11-01 21:50 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-01 16:32 [PATCH] drm/i915: Implement ReadHitWriteOnlyDisable Rafael Antognolli
2017-11-01 19:20 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-11-01 20:56 ` ✗ Fi.CI.IGT: failure " Patchwork
2017-11-01 21:14 ` Rodrigo Vivi
2017-11-01 21:11 ` [PATCH] " Rodrigo Vivi
2017-11-01 21:37 ` Rafael Antognolli
2017-11-01 21:50 ` ✓ Fi.CI.BAT: success for " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.