From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756415AbdKCR5E (ORCPT ); Fri, 3 Nov 2017 13:57:04 -0400 Received: from mx2.suse.de ([195.135.220.15]:34832 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756217AbdKCR5C (ORCPT ); Fri, 3 Nov 2017 13:57:02 -0400 Date: Fri, 3 Nov 2017 18:56:49 +0100 From: Borislav Petkov To: Janakarajan Natarajan Cc: kvm@vger.kernel.org, x86@kernel.org, linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" , Paolo Bonzini , Radim Krcmar , Len Brown , Kyle Huey , Kan Liang , Grzegorz Andrejczuk , Tom Lendacky , Tony Luck Subject: Re: [PATCH 2/4] Add AMD Core Perf Extension MSRs Message-ID: <20171103175649.xzz7gcyq6chddxg6@pd.tnic> References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Nov 01, 2017 at 11:19:28AM -0500, Janakarajan Natarajan wrote: > Add the EventSelect and Counter MSRs for AMD Core Perf Extension. > > Signed-off-by: Janakarajan Natarajan > --- > arch/x86/include/asm/msr-index.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index 17f5c12..9ec706f 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -338,6 +338,18 @@ > /* Fam 15h MSRs */ > #define MSR_F15H_PERF_CTL 0xc0010200 > #define MSR_F15H_PERF_CTR 0xc0010201 move that one... > +#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL > +#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) > +#define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) > +#define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) > +#define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) > +#define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) ... here and leave a space between the CTL and CTR groups. One letter difference is confusing enough. > +#define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR > +#define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) > +#define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) > +#define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) > +#define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) > +#define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) > #define MSR_F15H_NB_PERF_CTL 0xc0010240 > #define MSR_F15H_NB_PERF_CTR 0xc0010241 > #define MSR_F15H_PTSC 0xc0010280 > -- Thx. -- Regards/Gruss, Boris. SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg) --