* [PATCH 1/4] drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE result
@ 2017-11-09 14:49 Christian König
[not found] ` <20171109144925.2913-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 8+ messages in thread
From: Christian König @ 2017-11-09 14:49 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Not sure what that should originally been good for, but it doesn't seem
to make any sense any more.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/cik.c | 40 +++++++++++++++++-----------------
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 8 +++----
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 10 ++++-----
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 38 ++++++++++++++++----------------
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +++----
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 18 +++++++--------
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 +++----
drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 12 +++++-----
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 20 ++++++++---------
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 +++----
drivers/gpu/drm/amd/amdgpu/si.c | 34 ++++++++++++++---------------
drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/vi.c | 10 ++++-----
15 files changed, 113 insertions(+), 113 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 793b1470284d..6128080ff662 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -757,72 +757,72 @@ static void cik_init_golden_registers(struct amdgpu_device *adev)
case CHIP_BONAIRE:
amdgpu_program_register_sequence(adev,
bonaire_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
+ ARRAY_SIZE(bonaire_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
bonaire_golden_registers,
- (const u32)ARRAY_SIZE(bonaire_golden_registers));
+ ARRAY_SIZE(bonaire_golden_registers));
amdgpu_program_register_sequence(adev,
bonaire_golden_common_registers,
- (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
+ ARRAY_SIZE(bonaire_golden_common_registers));
amdgpu_program_register_sequence(adev,
bonaire_golden_spm_registers,
- (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
+ ARRAY_SIZE(bonaire_golden_spm_registers));
break;
case CHIP_KABINI:
amdgpu_program_register_sequence(adev,
kalindi_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
+ ARRAY_SIZE(kalindi_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
kalindi_golden_registers,
- (const u32)ARRAY_SIZE(kalindi_golden_registers));
+ ARRAY_SIZE(kalindi_golden_registers));
amdgpu_program_register_sequence(adev,
kalindi_golden_common_registers,
- (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
+ ARRAY_SIZE(kalindi_golden_common_registers));
amdgpu_program_register_sequence(adev,
kalindi_golden_spm_registers,
- (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
+ ARRAY_SIZE(kalindi_golden_spm_registers));
break;
case CHIP_MULLINS:
amdgpu_program_register_sequence(adev,
kalindi_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
+ ARRAY_SIZE(kalindi_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
godavari_golden_registers,
- (const u32)ARRAY_SIZE(godavari_golden_registers));
+ ARRAY_SIZE(godavari_golden_registers));
amdgpu_program_register_sequence(adev,
kalindi_golden_common_registers,
- (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
+ ARRAY_SIZE(kalindi_golden_common_registers));
amdgpu_program_register_sequence(adev,
kalindi_golden_spm_registers,
- (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
+ ARRAY_SIZE(kalindi_golden_spm_registers));
break;
case CHIP_KAVERI:
amdgpu_program_register_sequence(adev,
spectre_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
+ ARRAY_SIZE(spectre_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
spectre_golden_registers,
- (const u32)ARRAY_SIZE(spectre_golden_registers));
+ ARRAY_SIZE(spectre_golden_registers));
amdgpu_program_register_sequence(adev,
spectre_golden_common_registers,
- (const u32)ARRAY_SIZE(spectre_golden_common_registers));
+ ARRAY_SIZE(spectre_golden_common_registers));
amdgpu_program_register_sequence(adev,
spectre_golden_spm_registers,
- (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
+ ARRAY_SIZE(spectre_golden_spm_registers));
break;
case CHIP_HAWAII:
amdgpu_program_register_sequence(adev,
hawaii_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
+ ARRAY_SIZE(hawaii_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
hawaii_golden_registers,
- (const u32)ARRAY_SIZE(hawaii_golden_registers));
+ ARRAY_SIZE(hawaii_golden_registers));
amdgpu_program_register_sequence(adev,
hawaii_golden_common_registers,
- (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
+ ARRAY_SIZE(hawaii_golden_common_registers));
amdgpu_program_register_sequence(adev,
hawaii_golden_spm_registers,
- (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
+ ARRAY_SIZE(hawaii_golden_spm_registers));
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index f3dd6b7bfd4d..a397111c2ced 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -147,18 +147,18 @@ static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
case CHIP_FIJI:
amdgpu_program_register_sequence(adev,
fiji_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
+ ARRAY_SIZE(fiji_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
golden_settings_fiji_a10,
- (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
+ ARRAY_SIZE(golden_settings_fiji_a10));
break;
case CHIP_TONGA:
amdgpu_program_register_sequence(adev,
tonga_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
+ ARRAY_SIZE(tonga_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
golden_settings_tonga_a11,
- (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
+ ARRAY_SIZE(golden_settings_tonga_a11));
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index be25706e5f07..67e670989e81 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -156,26 +156,26 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
case CHIP_CARRIZO:
amdgpu_program_register_sequence(adev,
cz_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
+ ARRAY_SIZE(cz_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
cz_golden_settings_a11,
- (const u32)ARRAY_SIZE(cz_golden_settings_a11));
+ ARRAY_SIZE(cz_golden_settings_a11));
break;
case CHIP_STONEY:
amdgpu_program_register_sequence(adev,
stoney_golden_settings_a11,
- (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
+ ARRAY_SIZE(stoney_golden_settings_a11));
break;
case CHIP_POLARIS11:
case CHIP_POLARIS12:
amdgpu_program_register_sequence(adev,
polaris11_golden_settings_a11,
- (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
+ ARRAY_SIZE(polaris11_golden_settings_a11));
break;
case CHIP_POLARIS10:
amdgpu_program_register_sequence(adev,
polaris10_golden_settings_a11,
- (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
+ ARRAY_SIZE(polaris10_golden_settings_a11));
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index a74515aba1f6..1512325af117 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -681,53 +681,53 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
case CHIP_TOPAZ:
amdgpu_program_register_sequence(adev,
iceland_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
+ ARRAY_SIZE(iceland_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
golden_settings_iceland_a11,
- (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
+ ARRAY_SIZE(golden_settings_iceland_a11));
amdgpu_program_register_sequence(adev,
iceland_golden_common_all,
- (const u32)ARRAY_SIZE(iceland_golden_common_all));
+ ARRAY_SIZE(iceland_golden_common_all));
break;
case CHIP_FIJI:
amdgpu_program_register_sequence(adev,
fiji_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
+ ARRAY_SIZE(fiji_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
golden_settings_fiji_a10,
- (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
+ ARRAY_SIZE(golden_settings_fiji_a10));
amdgpu_program_register_sequence(adev,
fiji_golden_common_all,
- (const u32)ARRAY_SIZE(fiji_golden_common_all));
+ ARRAY_SIZE(fiji_golden_common_all));
break;
case CHIP_TONGA:
amdgpu_program_register_sequence(adev,
tonga_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
+ ARRAY_SIZE(tonga_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
golden_settings_tonga_a11,
- (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
+ ARRAY_SIZE(golden_settings_tonga_a11));
amdgpu_program_register_sequence(adev,
tonga_golden_common_all,
- (const u32)ARRAY_SIZE(tonga_golden_common_all));
+ ARRAY_SIZE(tonga_golden_common_all));
break;
case CHIP_POLARIS11:
case CHIP_POLARIS12:
amdgpu_program_register_sequence(adev,
golden_settings_polaris11_a11,
- (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
+ ARRAY_SIZE(golden_settings_polaris11_a11));
amdgpu_program_register_sequence(adev,
polaris11_golden_common_all,
- (const u32)ARRAY_SIZE(polaris11_golden_common_all));
+ ARRAY_SIZE(polaris11_golden_common_all));
break;
case CHIP_POLARIS10:
amdgpu_program_register_sequence(adev,
golden_settings_polaris10_a11,
- (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
+ ARRAY_SIZE(golden_settings_polaris10_a11));
amdgpu_program_register_sequence(adev,
polaris10_golden_common_all,
- (const u32)ARRAY_SIZE(polaris10_golden_common_all));
+ ARRAY_SIZE(polaris10_golden_common_all));
WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
if (adev->pdev->revision == 0xc7 &&
((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
@@ -740,24 +740,24 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
case CHIP_CARRIZO:
amdgpu_program_register_sequence(adev,
cz_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
+ ARRAY_SIZE(cz_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
cz_golden_settings_a11,
- (const u32)ARRAY_SIZE(cz_golden_settings_a11));
+ ARRAY_SIZE(cz_golden_settings_a11));
amdgpu_program_register_sequence(adev,
cz_golden_common_all,
- (const u32)ARRAY_SIZE(cz_golden_common_all));
+ ARRAY_SIZE(cz_golden_common_all));
break;
case CHIP_STONEY:
amdgpu_program_register_sequence(adev,
stoney_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
+ ARRAY_SIZE(stoney_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
stoney_golden_settings_a11,
- (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
+ ARRAY_SIZE(stoney_golden_settings_a11));
amdgpu_program_register_sequence(adev,
stoney_golden_common_all,
- (const u32)ARRAY_SIZE(stoney_golden_common_all));
+ ARRAY_SIZE(stoney_golden_common_all));
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 56f5508a5fdc..7381b99024bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -226,18 +226,18 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
case CHIP_VEGA10:
amdgpu_program_register_sequence(adev,
golden_settings_gc_9_0,
- (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
+ ARRAY_SIZE(golden_settings_gc_9_0));
amdgpu_program_register_sequence(adev,
golden_settings_gc_9_0_vg10,
- (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
+ ARRAY_SIZE(golden_settings_gc_9_0_vg10));
break;
case CHIP_RAVEN:
amdgpu_program_register_sequence(adev,
golden_settings_gc_9_1,
- (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
+ ARRAY_SIZE(golden_settings_gc_9_1));
amdgpu_program_register_sequence(adev,
golden_settings_gc_9_1_rv1,
- (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
+ ARRAY_SIZE(golden_settings_gc_9_1_rv1));
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 583d87792820..6c6a7e14359c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -69,10 +69,10 @@ static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
case CHIP_TOPAZ:
amdgpu_program_register_sequence(adev,
iceland_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
+ ARRAY_SIZE(iceland_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
golden_settings_iceland_a11,
- (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
+ ARRAY_SIZE(golden_settings_iceland_a11));
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 9ca5fea93ebc..edbe0df24d90 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -122,42 +122,42 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
case CHIP_FIJI:
amdgpu_program_register_sequence(adev,
fiji_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
+ ARRAY_SIZE(fiji_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
golden_settings_fiji_a10,
- (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
+ ARRAY_SIZE(golden_settings_fiji_a10));
break;
case CHIP_TONGA:
amdgpu_program_register_sequence(adev,
tonga_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
+ ARRAY_SIZE(tonga_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
golden_settings_tonga_a11,
- (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
+ ARRAY_SIZE(golden_settings_tonga_a11));
break;
case CHIP_POLARIS11:
case CHIP_POLARIS12:
amdgpu_program_register_sequence(adev,
golden_settings_polaris11_a11,
- (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
+ ARRAY_SIZE(golden_settings_polaris11_a11));
break;
case CHIP_POLARIS10:
amdgpu_program_register_sequence(adev,
golden_settings_polaris10_a11,
- (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
+ ARRAY_SIZE(golden_settings_polaris10_a11));
break;
case CHIP_CARRIZO:
amdgpu_program_register_sequence(adev,
cz_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
+ ARRAY_SIZE(cz_mgcg_cgcg_init));
break;
case CHIP_STONEY:
amdgpu_program_register_sequence(adev,
stoney_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
+ ARRAY_SIZE(stoney_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
golden_settings_stoney_common,
- (const u32)ARRAY_SIZE(golden_settings_stoney_common));
+ ARRAY_SIZE(golden_settings_stoney_common));
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 0de4dc068516..91fc097abdfc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -687,15 +687,15 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
case CHIP_VEGA10:
amdgpu_program_register_sequence(adev,
golden_settings_mmhub_1_0_0,
- (const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0));
+ ARRAY_SIZE(golden_settings_mmhub_1_0_0));
amdgpu_program_register_sequence(adev,
golden_settings_athub_1_0_0,
- (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
+ ARRAY_SIZE(golden_settings_athub_1_0_0));
break;
case CHIP_RAVEN:
amdgpu_program_register_sequence(adev,
golden_settings_athub_1_0_0,
- (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
+ ARRAY_SIZE(golden_settings_athub_1_0_0));
break;
default:
break;
@@ -715,7 +715,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
amdgpu_program_register_sequence(adev,
golden_settings_vega10_hdp,
- (const u32)ARRAY_SIZE(golden_settings_vega10_hdp));
+ ARRAY_SIZE(golden_settings_vega10_hdp));
if (adev->gart.robj == NULL) {
dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
index 2b435c02ef44..df52824c0cd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
@@ -281,29 +281,29 @@ void xgpu_vi_init_golden_registers(struct amdgpu_device *adev)
case CHIP_FIJI:
amdgpu_program_register_sequence(adev,
xgpu_fiji_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(
+ ARRAY_SIZE(
xgpu_fiji_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
xgpu_fiji_golden_settings_a10,
- (const u32)ARRAY_SIZE(
+ ARRAY_SIZE(
xgpu_fiji_golden_settings_a10));
amdgpu_program_register_sequence(adev,
xgpu_fiji_golden_common_all,
- (const u32)ARRAY_SIZE(
+ ARRAY_SIZE(
xgpu_fiji_golden_common_all));
break;
case CHIP_TONGA:
amdgpu_program_register_sequence(adev,
xgpu_tonga_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(
+ ARRAY_SIZE(
xgpu_tonga_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
xgpu_tonga_golden_settings_a11,
- (const u32)ARRAY_SIZE(
+ ARRAY_SIZE(
xgpu_tonga_golden_settings_a11));
amdgpu_program_register_sequence(adev,
xgpu_tonga_golden_common_all,
- (const u32)ARRAY_SIZE(
+ ARRAY_SIZE(
xgpu_tonga_golden_common_all));
break;
default:
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 92f8c44a73b6..121e628e7cdb 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -95,10 +95,10 @@ static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
case CHIP_TOPAZ:
amdgpu_program_register_sequence(adev,
iceland_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
+ ARRAY_SIZE(iceland_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
golden_settings_iceland_a11,
- (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
+ ARRAY_SIZE(golden_settings_iceland_a11));
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 52e6bf2e9e59..c8c93f9dac21 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -194,45 +194,45 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
case CHIP_FIJI:
amdgpu_program_register_sequence(adev,
fiji_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
+ ARRAY_SIZE(fiji_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
golden_settings_fiji_a10,
- (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
+ ARRAY_SIZE(golden_settings_fiji_a10));
break;
case CHIP_TONGA:
amdgpu_program_register_sequence(adev,
tonga_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
+ ARRAY_SIZE(tonga_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
golden_settings_tonga_a11,
- (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
+ ARRAY_SIZE(golden_settings_tonga_a11));
break;
case CHIP_POLARIS11:
case CHIP_POLARIS12:
amdgpu_program_register_sequence(adev,
golden_settings_polaris11_a11,
- (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
+ ARRAY_SIZE(golden_settings_polaris11_a11));
break;
case CHIP_POLARIS10:
amdgpu_program_register_sequence(adev,
golden_settings_polaris10_a11,
- (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
+ ARRAY_SIZE(golden_settings_polaris10_a11));
break;
case CHIP_CARRIZO:
amdgpu_program_register_sequence(adev,
cz_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
+ ARRAY_SIZE(cz_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
cz_golden_settings_a11,
- (const u32)ARRAY_SIZE(cz_golden_settings_a11));
+ ARRAY_SIZE(cz_golden_settings_a11));
break;
case CHIP_STONEY:
amdgpu_program_register_sequence(adev,
stoney_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
+ ARRAY_SIZE(stoney_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
stoney_golden_settings_a11,
- (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
+ ARRAY_SIZE(stoney_golden_settings_a11));
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index fe78c00b9ffa..a0a5a8da4c4f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -132,18 +132,18 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
case CHIP_VEGA10:
amdgpu_program_register_sequence(adev,
golden_settings_sdma_4,
- (const u32)ARRAY_SIZE(golden_settings_sdma_4));
+ ARRAY_SIZE(golden_settings_sdma_4));
amdgpu_program_register_sequence(adev,
golden_settings_sdma_vg10,
- (const u32)ARRAY_SIZE(golden_settings_sdma_vg10));
+ ARRAY_SIZE(golden_settings_sdma_vg10));
break;
case CHIP_RAVEN:
amdgpu_program_register_sequence(adev,
golden_settings_sdma_4_1,
- (const u32)ARRAY_SIZE(golden_settings_sdma_4_1));
+ ARRAY_SIZE(golden_settings_sdma_4_1));
amdgpu_program_register_sequence(adev,
golden_settings_sdma_rv1,
- (const u32)ARRAY_SIZE(golden_settings_sdma_rv1));
+ ARRAY_SIZE(golden_settings_sdma_rv1));
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 8284d5dbfc30..49eef3090f08 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1392,63 +1392,63 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
case CHIP_TAHITI:
amdgpu_program_register_sequence(adev,
tahiti_golden_registers,
- (const u32)ARRAY_SIZE(tahiti_golden_registers));
+ ARRAY_SIZE(tahiti_golden_registers));
amdgpu_program_register_sequence(adev,
tahiti_golden_rlc_registers,
- (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
+ ARRAY_SIZE(tahiti_golden_rlc_registers));
amdgpu_program_register_sequence(adev,
tahiti_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
+ ARRAY_SIZE(tahiti_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
tahiti_golden_registers2,
- (const u32)ARRAY_SIZE(tahiti_golden_registers2));
+ ARRAY_SIZE(tahiti_golden_registers2));
break;
case CHIP_PITCAIRN:
amdgpu_program_register_sequence(adev,
pitcairn_golden_registers,
- (const u32)ARRAY_SIZE(pitcairn_golden_registers));
+ ARRAY_SIZE(pitcairn_golden_registers));
amdgpu_program_register_sequence(adev,
pitcairn_golden_rlc_registers,
- (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
+ ARRAY_SIZE(pitcairn_golden_rlc_registers));
amdgpu_program_register_sequence(adev,
pitcairn_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
+ ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
break;
case CHIP_VERDE:
amdgpu_program_register_sequence(adev,
verde_golden_registers,
- (const u32)ARRAY_SIZE(verde_golden_registers));
+ ARRAY_SIZE(verde_golden_registers));
amdgpu_program_register_sequence(adev,
verde_golden_rlc_registers,
- (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
+ ARRAY_SIZE(verde_golden_rlc_registers));
amdgpu_program_register_sequence(adev,
verde_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
+ ARRAY_SIZE(verde_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev,
verde_pg_init,
- (const u32)ARRAY_SIZE(verde_pg_init));
+ ARRAY_SIZE(verde_pg_init));
break;
case CHIP_OLAND:
amdgpu_program_register_sequence(adev,
oland_golden_registers,
- (const u32)ARRAY_SIZE(oland_golden_registers));
+ ARRAY_SIZE(oland_golden_registers));
amdgpu_program_register_sequence(adev,
oland_golden_rlc_registers,
- (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
+ ARRAY_SIZE(oland_golden_rlc_registers));
amdgpu_program_register_sequence(adev,
oland_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
+ ARRAY_SIZE(oland_mgcg_cgcg_init));
break;
case CHIP_HAINAN:
amdgpu_program_register_sequence(adev,
hainan_golden_registers,
- (const u32)ARRAY_SIZE(hainan_golden_registers));
+ ARRAY_SIZE(hainan_golden_registers));
amdgpu_program_register_sequence(adev,
hainan_golden_registers2,
- (const u32)ARRAY_SIZE(hainan_golden_registers2));
+ ARRAY_SIZE(hainan_golden_registers2));
amdgpu_program_register_sequence(adev,
hainan_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
+ ARRAY_SIZE(hainan_mgcg_cgcg_init));
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 4e67fe1e7955..fa27e0354f35 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -265,12 +265,12 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
case CHIP_VEGA10:
amdgpu_program_register_sequence(adev,
vega10_golden_init,
- (const u32)ARRAY_SIZE(vega10_golden_init));
+ ARRAY_SIZE(vega10_golden_init));
break;
case CHIP_RAVEN:
amdgpu_program_register_sequence(adev,
raven_golden_init,
- (const u32)ARRAY_SIZE(raven_golden_init));
+ ARRAY_SIZE(raven_golden_init));
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 3a4c2fa7e36d..bb8ca9489546 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -284,27 +284,27 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)
case CHIP_TOPAZ:
amdgpu_program_register_sequence(adev,
iceland_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
+ ARRAY_SIZE(iceland_mgcg_cgcg_init));
break;
case CHIP_FIJI:
amdgpu_program_register_sequence(adev,
fiji_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
+ ARRAY_SIZE(fiji_mgcg_cgcg_init));
break;
case CHIP_TONGA:
amdgpu_program_register_sequence(adev,
tonga_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
+ ARRAY_SIZE(tonga_mgcg_cgcg_init));
break;
case CHIP_CARRIZO:
amdgpu_program_register_sequence(adev,
cz_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
+ ARRAY_SIZE(cz_mgcg_cgcg_init));
break;
case CHIP_STONEY:
amdgpu_program_register_sequence(adev,
stoney_mgcg_cgcg_init,
- (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
+ ARRAY_SIZE(stoney_mgcg_cgcg_init));
break;
case CHIP_POLARIS11:
case CHIP_POLARIS10:
--
2.11.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/4] drm/amdgpu: cleanup vm_size handling
[not found] ` <20171109144925.2913-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
@ 2017-11-09 14:49 ` Christian König
[not found] ` <20171109144925.2913-2-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2017-11-09 14:49 ` [PATCH 3/4] drm/amdgpu: make AMDGPU_VA_RESERVED_SIZE 64bit Christian König
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Christian König @ 2017-11-09 14:49 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
It's pointless to have the same value twice, just always use max_pfn.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 18 +++++++++---------
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 7 +++----
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 -
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 -
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 -
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 13 +++++--------
6 files changed, 17 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 407d3dad8f97..94500358eccc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2576,27 +2576,27 @@ void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
* @adev: amdgpu_device pointer
* @vm_size: the default vm size if it's set auto
*/
-void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
+void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
uint32_t fragment_size_default)
{
/* adjust vm size firstly */
- if (amdgpu_vm_size == -1)
- adev->vm_manager.vm_size = vm_size;
- else
- adev->vm_manager.vm_size = amdgpu_vm_size;
+ if (amdgpu_vm_size != -1)
+ vm_size = amdgpu_vm_size;
+
+ adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
/* block size depends on vm size */
if (amdgpu_vm_block_size == -1)
adev->vm_manager.block_size =
- amdgpu_vm_get_block_size(adev->vm_manager.vm_size);
+ amdgpu_vm_get_block_size(vm_size);
else
adev->vm_manager.block_size = amdgpu_vm_block_size;
amdgpu_vm_set_fragment_size(adev, fragment_size_default);
- DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n",
- adev->vm_manager.vm_size, adev->vm_manager.block_size,
- adev->vm_manager.fragment_size);
+ DRM_INFO("vm size is %u GB, block size is %u-bit, fragment size is %u-bit\n",
+ vm_size, adev->vm_manager.block_size,
+ adev->vm_manager.fragment_size);
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index aa914256b4bc..c7b796c12775 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -220,7 +220,6 @@ struct amdgpu_vm_manager {
uint64_t max_pfn;
uint32_t num_level;
- uint64_t vm_size;
uint32_t block_size;
uint32_t fragment_size;
/* vram base address for page table entry */
@@ -312,9 +311,9 @@ struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
struct amdgpu_bo_va *bo_va);
void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
- uint32_t fragment_size_default);
-void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
- uint32_t fragment_size_default);
+ uint32_t fragment_size_default);
+void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
+ uint32_t fragment_size_default);
int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
struct amdgpu_job *job);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index d2a43db22cff..c8e47c36608e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -838,7 +838,6 @@ static int gmc_v6_0_sw_init(void *handle)
return r;
amdgpu_vm_adjust_size(adev, 64, 9);
- adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
adev->mc.mc_mask = 0xffffffffffULL;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 6c6a7e14359c..2b7338e22409 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -978,7 +978,6 @@ static int gmc_v7_0_sw_init(void *handle)
* Max GPUVM size for cayman and SI is 40 bits.
*/
amdgpu_vm_adjust_size(adev, 64, 9);
- adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
/* Set the internal MC address mask
* This is the max address of the GPU's
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index edbe0df24d90..e30a96a8f49b 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1075,7 +1075,6 @@ static int gmc_v8_0_sw_init(void *handle)
* Max GPUVM size for cayman and SI is 40 bits.
*/
amdgpu_vm_adjust_size(adev, 64, 9);
- adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
/* Set the internal MC address mask
* This is the max address of the GPU's
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 91fc097abdfc..16bba97e704a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -555,7 +555,7 @@ static int gmc_v9_0_sw_init(void *handle)
case CHIP_RAVEN:
adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
- adev->vm_manager.vm_size = 1U << 18;
+ adev->vm_manager.max_pfn = 1ULL << 36;
adev->vm_manager.block_size = 9;
adev->vm_manager.num_level = 3;
amdgpu_vm_set_fragment_size(adev, 9);
@@ -573,7 +573,7 @@ static int gmc_v9_0_sw_init(void *handle)
* vm size is 256TB (48bit), maximum size of Vega10,
* block size 512 (9bit)
*/
- adev->vm_manager.vm_size = 1U << 18;
+ adev->vm_manager.max_pfn = 1ULL << 36;
adev->vm_manager.block_size = 9;
adev->vm_manager.num_level = 3;
amdgpu_vm_set_fragment_size(adev, 9);
@@ -582,10 +582,9 @@ static int gmc_v9_0_sw_init(void *handle)
break;
}
- DRM_INFO("vm size is %llu GB, block size is %u-bit,fragment size is %u-bit\n",
- adev->vm_manager.vm_size,
- adev->vm_manager.block_size,
- adev->vm_manager.fragment_size);
+ DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n",
+ adev->vm_manager.max_pfn >> 18, adev->vm_manager.block_size,
+ adev->vm_manager.fragment_size);
/* This interrupt is VMC page fault.*/
r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
@@ -596,8 +595,6 @@ static int gmc_v9_0_sw_init(void *handle)
if (r)
return r;
- adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
-
/* Set the internal MC address mask
* This is the max address of the GPU's
* internal address space.
--
2.11.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 3/4] drm/amdgpu: make AMDGPU_VA_RESERVED_SIZE 64bit
[not found] ` <20171109144925.2913-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2017-11-09 14:49 ` [PATCH 2/4] drm/amdgpu: cleanup vm_size handling Christian König
@ 2017-11-09 14:49 ` Christian König
2017-11-09 14:49 ` [PATCH 4/4] drm/amdgpu: fix VA hole handling on Vega10 Christian König
2017-11-09 16:28 ` [PATCH 1/4] drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE result Alex Deucher
3 siblings, 0 replies; 8+ messages in thread
From: Christian König @ 2017-11-09 14:49 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Even when it's a small handle it as 64bit value as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ++-
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index fb72edc4c026..4710e51099c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -556,9 +556,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
dev_err(&dev->pdev->dev,
- "va_address 0x%lX is in reserved area 0x%X\n",
- (unsigned long)args->va_address,
- AMDGPU_VA_RESERVED_SIZE);
+ "va_address 0x%LX is in reserved area 0x%LX\n",
+ args->va_address, AMDGPU_VA_RESERVED_SIZE);
return -EINVAL;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index c7b796c12775..e8f8896d18db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -94,7 +94,8 @@ struct amdgpu_bo_list_entry;
#define AMDGPU_MMHUB 1
/* hardcode that limit for now */
-#define AMDGPU_VA_RESERVED_SIZE (8 << 20)
+#define AMDGPU_VA_RESERVED_SIZE (8ULL << 20)
+
/* max vmids dedicated for process */
#define AMDGPU_VM_MAX_RESERVED_VMID 1
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 4/4] drm/amdgpu: fix VA hole handling on Vega10
[not found] ` <20171109144925.2913-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2017-11-09 14:49 ` [PATCH 2/4] drm/amdgpu: cleanup vm_size handling Christian König
2017-11-09 14:49 ` [PATCH 3/4] drm/amdgpu: make AMDGPU_VA_RESERVED_SIZE 64bit Christian König
@ 2017-11-09 14:49 ` Christian König
[not found] ` <20171109144925.2913-4-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2017-11-09 16:28 ` [PATCH 1/4] drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE result Alex Deucher
3 siblings, 1 reply; 8+ messages in thread
From: Christian König @ 2017-11-09 14:49 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Similar to the CPU address space the VA on Vega10 has a hole in it.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 10 +++++-----
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 11 +++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 +++-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 5 +++++
4 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 354c874888f1..b15591c879ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -869,8 +869,8 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
struct amdgpu_bo_va_mapping *m;
struct amdgpu_bo *aobj = NULL;
struct amdgpu_cs_chunk *chunk;
+ uint64_t offset, va_start;
struct amdgpu_ib *ib;
- uint64_t offset;
uint8_t *kptr;
chunk = &p->chunks[i];
@@ -880,14 +880,14 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
continue;
- r = amdgpu_cs_find_mapping(p, chunk_ib->va_start,
- &aobj, &m);
+ va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;
+ r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
if (r) {
DRM_ERROR("IB va_start is invalid\n");
return r;
}
- if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
+ if ((va_start + chunk_ib->ib_bytes) >
(m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
DRM_ERROR("IB va_start+ib_bytes is invalid\n");
return -EINVAL;
@@ -900,7 +900,7 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
}
offset = m->start * AMDGPU_GPU_PAGE_SIZE;
- kptr += chunk_ib->va_start - offset;
+ kptr += va_start - offset;
memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
amdgpu_bo_kunmap(aobj);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 4710e51099c2..81c34132fbd5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -561,6 +561,17 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
return -EINVAL;
}
+ if (args->va_address >= AMDGPU_VA_HOLE_START &&
+ args->va_address < AMDGPU_VA_HOLE_END) {
+ dev_err(&dev->pdev->dev,
+ "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
+ args->va_address, AMDGPU_VA_HOLE_START,
+ AMDGPU_VA_HOLE_END);
+ return -EINVAL;
+ }
+
+ args->va_address &= AMDGPU_VA_HOLE_MASK;
+
if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
dev_err(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
args->flags);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 1d56b5b5c25d..694d953e9cb6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -589,7 +589,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
if (amdgpu_sriov_vf(adev))
dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
- dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
+ dev_info.virtual_address_max =
+ min(adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE,
+ AMDGPU_VA_HOLE_START);
dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index e8f8896d18db..31cd57592546 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -96,6 +96,11 @@ struct amdgpu_bo_list_entry;
/* hardcode that limit for now */
#define AMDGPU_VA_RESERVED_SIZE (8ULL << 20)
+/* VA hole for 48bit addresses on Vega10 */
+#define AMDGPU_VA_HOLE_START 0x0000800000000000ULL
+#define AMDGPU_VA_HOLE_END 0xffff800000000000ULL
+#define AMDGPU_VA_HOLE_MASK 0x0000ffffffffffffULL
+
/* max vmids dedicated for process */
#define AMDGPU_VM_MAX_RESERVED_VMID 1
--
2.11.0
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 4/4] drm/amdgpu: fix VA hole handling on Vega10
[not found] ` <20171109144925.2913-4-christian.koenig-5C7GfCeVMHo@public.gmane.org>
@ 2017-11-09 14:59 ` Michel Dänzer
[not found] ` <ebc6ec8d-4ea5-9080-fb27-a18e46f3740f-otUistvHUpPR7s880joybQ@public.gmane.org>
0 siblings, 1 reply; 8+ messages in thread
From: Michel Dänzer @ 2017-11-09 14:59 UTC (permalink / raw)
To: Christian König; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On 09/11/17 03:49 PM, Christian König wrote:
> Similar to the CPU address space the VA on Vega10 has a hole in it.
[...]
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index 4710e51099c2..81c34132fbd5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -561,6 +561,17 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
> return -EINVAL;
> }
>
> + if (args->va_address >= AMDGPU_VA_HOLE_START &&
> + args->va_address < AMDGPU_VA_HOLE_END) {
> + dev_err(&dev->pdev->dev,
> + "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
> + args->va_address, AMDGPU_VA_HOLE_START,
> + AMDGPU_VA_HOLE_END);
> + return -EINVAL;
> + }
This should probably be dev_dbg instead of dev_err, to prevent buggy (or
malicious) userspace from spamming dmesg.
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X developer
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 4/4] drm/amdgpu: fix VA hole handling on Vega10
[not found] ` <ebc6ec8d-4ea5-9080-fb27-a18e46f3740f-otUistvHUpPR7s880joybQ@public.gmane.org>
@ 2017-11-09 16:15 ` Christian König
0 siblings, 0 replies; 8+ messages in thread
From: Christian König @ 2017-11-09 16:15 UTC (permalink / raw)
To: Michel Dänzer; +Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Am 09.11.2017 um 15:59 schrieb Michel Dänzer:
> On 09/11/17 03:49 PM, Christian König wrote:
>> Similar to the CPU address space the VA on Vega10 has a hole in it.
> [...]
>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> index 4710e51099c2..81c34132fbd5 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> @@ -561,6 +561,17 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
>> return -EINVAL;
>> }
>>
>> + if (args->va_address >= AMDGPU_VA_HOLE_START &&
>> + args->va_address < AMDGPU_VA_HOLE_END) {
>> + dev_err(&dev->pdev->dev,
>> + "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
>> + args->va_address, AMDGPU_VA_HOLE_START,
>> + AMDGPU_VA_HOLE_END);
>> + return -EINVAL;
>> + }
> This should probably be dev_dbg instead of dev_err, to prevent buggy (or
> malicious) userspace from spamming dmesg.
Good point, and yes we have quite a number of other issues like that one.
Going to fix this in v2 of the patches.
Christian.
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/4] drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE result
[not found] ` <20171109144925.2913-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2017-11-09 14:49 ` [PATCH 4/4] drm/amdgpu: fix VA hole handling on Vega10 Christian König
@ 2017-11-09 16:28 ` Alex Deucher
3 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2017-11-09 16:28 UTC (permalink / raw)
To: Christian König; +Cc: amd-gfx list
On Thu, Nov 9, 2017 at 9:49 AM, Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
> Not sure what that should originally been good for, but it doesn't seem
> to make any sense any more.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/cik.c | 40 +++++++++++++++++-----------------
> drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 8 +++----
> drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 10 ++++-----
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 38 ++++++++++++++++----------------
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +++----
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 18 +++++++--------
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 +++----
> drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 12 +++++-----
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 20 ++++++++---------
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 +++----
> drivers/gpu/drm/amd/amdgpu/si.c | 34 ++++++++++++++---------------
> drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/vi.c | 10 ++++-----
> 15 files changed, 113 insertions(+), 113 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
> index 793b1470284d..6128080ff662 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
> @@ -757,72 +757,72 @@ static void cik_init_golden_registers(struct amdgpu_device *adev)
> case CHIP_BONAIRE:
> amdgpu_program_register_sequence(adev,
> bonaire_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
> + ARRAY_SIZE(bonaire_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> bonaire_golden_registers,
> - (const u32)ARRAY_SIZE(bonaire_golden_registers));
> + ARRAY_SIZE(bonaire_golden_registers));
> amdgpu_program_register_sequence(adev,
> bonaire_golden_common_registers,
> - (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
> + ARRAY_SIZE(bonaire_golden_common_registers));
> amdgpu_program_register_sequence(adev,
> bonaire_golden_spm_registers,
> - (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
> + ARRAY_SIZE(bonaire_golden_spm_registers));
> break;
> case CHIP_KABINI:
> amdgpu_program_register_sequence(adev,
> kalindi_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
> + ARRAY_SIZE(kalindi_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> kalindi_golden_registers,
> - (const u32)ARRAY_SIZE(kalindi_golden_registers));
> + ARRAY_SIZE(kalindi_golden_registers));
> amdgpu_program_register_sequence(adev,
> kalindi_golden_common_registers,
> - (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
> + ARRAY_SIZE(kalindi_golden_common_registers));
> amdgpu_program_register_sequence(adev,
> kalindi_golden_spm_registers,
> - (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
> + ARRAY_SIZE(kalindi_golden_spm_registers));
> break;
> case CHIP_MULLINS:
> amdgpu_program_register_sequence(adev,
> kalindi_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
> + ARRAY_SIZE(kalindi_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> godavari_golden_registers,
> - (const u32)ARRAY_SIZE(godavari_golden_registers));
> + ARRAY_SIZE(godavari_golden_registers));
> amdgpu_program_register_sequence(adev,
> kalindi_golden_common_registers,
> - (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
> + ARRAY_SIZE(kalindi_golden_common_registers));
> amdgpu_program_register_sequence(adev,
> kalindi_golden_spm_registers,
> - (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
> + ARRAY_SIZE(kalindi_golden_spm_registers));
> break;
> case CHIP_KAVERI:
> amdgpu_program_register_sequence(adev,
> spectre_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
> + ARRAY_SIZE(spectre_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> spectre_golden_registers,
> - (const u32)ARRAY_SIZE(spectre_golden_registers));
> + ARRAY_SIZE(spectre_golden_registers));
> amdgpu_program_register_sequence(adev,
> spectre_golden_common_registers,
> - (const u32)ARRAY_SIZE(spectre_golden_common_registers));
> + ARRAY_SIZE(spectre_golden_common_registers));
> amdgpu_program_register_sequence(adev,
> spectre_golden_spm_registers,
> - (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
> + ARRAY_SIZE(spectre_golden_spm_registers));
> break;
> case CHIP_HAWAII:
> amdgpu_program_register_sequence(adev,
> hawaii_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
> + ARRAY_SIZE(hawaii_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> hawaii_golden_registers,
> - (const u32)ARRAY_SIZE(hawaii_golden_registers));
> + ARRAY_SIZE(hawaii_golden_registers));
> amdgpu_program_register_sequence(adev,
> hawaii_golden_common_registers,
> - (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
> + ARRAY_SIZE(hawaii_golden_common_registers));
> amdgpu_program_register_sequence(adev,
> hawaii_golden_spm_registers,
> - (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
> + ARRAY_SIZE(hawaii_golden_spm_registers));
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> index f3dd6b7bfd4d..a397111c2ced 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
> @@ -147,18 +147,18 @@ static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
> case CHIP_FIJI:
> amdgpu_program_register_sequence(adev,
> fiji_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
> + ARRAY_SIZE(fiji_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> golden_settings_fiji_a10,
> - (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
> + ARRAY_SIZE(golden_settings_fiji_a10));
> break;
> case CHIP_TONGA:
> amdgpu_program_register_sequence(adev,
> tonga_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
> + ARRAY_SIZE(tonga_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> golden_settings_tonga_a11,
> - (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
> + ARRAY_SIZE(golden_settings_tonga_a11));
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> index be25706e5f07..67e670989e81 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
> @@ -156,26 +156,26 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
> case CHIP_CARRIZO:
> amdgpu_program_register_sequence(adev,
> cz_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
> + ARRAY_SIZE(cz_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> cz_golden_settings_a11,
> - (const u32)ARRAY_SIZE(cz_golden_settings_a11));
> + ARRAY_SIZE(cz_golden_settings_a11));
> break;
> case CHIP_STONEY:
> amdgpu_program_register_sequence(adev,
> stoney_golden_settings_a11,
> - (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
> + ARRAY_SIZE(stoney_golden_settings_a11));
> break;
> case CHIP_POLARIS11:
> case CHIP_POLARIS12:
> amdgpu_program_register_sequence(adev,
> polaris11_golden_settings_a11,
> - (const u32)ARRAY_SIZE(polaris11_golden_settings_a11));
> + ARRAY_SIZE(polaris11_golden_settings_a11));
> break;
> case CHIP_POLARIS10:
> amdgpu_program_register_sequence(adev,
> polaris10_golden_settings_a11,
> - (const u32)ARRAY_SIZE(polaris10_golden_settings_a11));
> + ARRAY_SIZE(polaris10_golden_settings_a11));
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index a74515aba1f6..1512325af117 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -681,53 +681,53 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
> case CHIP_TOPAZ:
> amdgpu_program_register_sequence(adev,
> iceland_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
> + ARRAY_SIZE(iceland_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> golden_settings_iceland_a11,
> - (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
> + ARRAY_SIZE(golden_settings_iceland_a11));
> amdgpu_program_register_sequence(adev,
> iceland_golden_common_all,
> - (const u32)ARRAY_SIZE(iceland_golden_common_all));
> + ARRAY_SIZE(iceland_golden_common_all));
> break;
> case CHIP_FIJI:
> amdgpu_program_register_sequence(adev,
> fiji_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
> + ARRAY_SIZE(fiji_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> golden_settings_fiji_a10,
> - (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
> + ARRAY_SIZE(golden_settings_fiji_a10));
> amdgpu_program_register_sequence(adev,
> fiji_golden_common_all,
> - (const u32)ARRAY_SIZE(fiji_golden_common_all));
> + ARRAY_SIZE(fiji_golden_common_all));
> break;
>
> case CHIP_TONGA:
> amdgpu_program_register_sequence(adev,
> tonga_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
> + ARRAY_SIZE(tonga_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> golden_settings_tonga_a11,
> - (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
> + ARRAY_SIZE(golden_settings_tonga_a11));
> amdgpu_program_register_sequence(adev,
> tonga_golden_common_all,
> - (const u32)ARRAY_SIZE(tonga_golden_common_all));
> + ARRAY_SIZE(tonga_golden_common_all));
> break;
> case CHIP_POLARIS11:
> case CHIP_POLARIS12:
> amdgpu_program_register_sequence(adev,
> golden_settings_polaris11_a11,
> - (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
> + ARRAY_SIZE(golden_settings_polaris11_a11));
> amdgpu_program_register_sequence(adev,
> polaris11_golden_common_all,
> - (const u32)ARRAY_SIZE(polaris11_golden_common_all));
> + ARRAY_SIZE(polaris11_golden_common_all));
> break;
> case CHIP_POLARIS10:
> amdgpu_program_register_sequence(adev,
> golden_settings_polaris10_a11,
> - (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
> + ARRAY_SIZE(golden_settings_polaris10_a11));
> amdgpu_program_register_sequence(adev,
> polaris10_golden_common_all,
> - (const u32)ARRAY_SIZE(polaris10_golden_common_all));
> + ARRAY_SIZE(polaris10_golden_common_all));
> WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
> if (adev->pdev->revision == 0xc7 &&
> ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
> @@ -740,24 +740,24 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
> case CHIP_CARRIZO:
> amdgpu_program_register_sequence(adev,
> cz_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
> + ARRAY_SIZE(cz_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> cz_golden_settings_a11,
> - (const u32)ARRAY_SIZE(cz_golden_settings_a11));
> + ARRAY_SIZE(cz_golden_settings_a11));
> amdgpu_program_register_sequence(adev,
> cz_golden_common_all,
> - (const u32)ARRAY_SIZE(cz_golden_common_all));
> + ARRAY_SIZE(cz_golden_common_all));
> break;
> case CHIP_STONEY:
> amdgpu_program_register_sequence(adev,
> stoney_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
> + ARRAY_SIZE(stoney_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> stoney_golden_settings_a11,
> - (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
> + ARRAY_SIZE(stoney_golden_settings_a11));
> amdgpu_program_register_sequence(adev,
> stoney_golden_common_all,
> - (const u32)ARRAY_SIZE(stoney_golden_common_all));
> + ARRAY_SIZE(stoney_golden_common_all));
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 56f5508a5fdc..7381b99024bd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -226,18 +226,18 @@ static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
> case CHIP_VEGA10:
> amdgpu_program_register_sequence(adev,
> golden_settings_gc_9_0,
> - (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
> + ARRAY_SIZE(golden_settings_gc_9_0));
> amdgpu_program_register_sequence(adev,
> golden_settings_gc_9_0_vg10,
> - (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
> + ARRAY_SIZE(golden_settings_gc_9_0_vg10));
> break;
> case CHIP_RAVEN:
> amdgpu_program_register_sequence(adev,
> golden_settings_gc_9_1,
> - (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
> + ARRAY_SIZE(golden_settings_gc_9_1));
> amdgpu_program_register_sequence(adev,
> golden_settings_gc_9_1_rv1,
> - (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
> + ARRAY_SIZE(golden_settings_gc_9_1_rv1));
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index 583d87792820..6c6a7e14359c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -69,10 +69,10 @@ static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
> case CHIP_TOPAZ:
> amdgpu_program_register_sequence(adev,
> iceland_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
> + ARRAY_SIZE(iceland_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> golden_settings_iceland_a11,
> - (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
> + ARRAY_SIZE(golden_settings_iceland_a11));
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 9ca5fea93ebc..edbe0df24d90 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -122,42 +122,42 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
> case CHIP_FIJI:
> amdgpu_program_register_sequence(adev,
> fiji_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
> + ARRAY_SIZE(fiji_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> golden_settings_fiji_a10,
> - (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
> + ARRAY_SIZE(golden_settings_fiji_a10));
> break;
> case CHIP_TONGA:
> amdgpu_program_register_sequence(adev,
> tonga_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
> + ARRAY_SIZE(tonga_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> golden_settings_tonga_a11,
> - (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
> + ARRAY_SIZE(golden_settings_tonga_a11));
> break;
> case CHIP_POLARIS11:
> case CHIP_POLARIS12:
> amdgpu_program_register_sequence(adev,
> golden_settings_polaris11_a11,
> - (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
> + ARRAY_SIZE(golden_settings_polaris11_a11));
> break;
> case CHIP_POLARIS10:
> amdgpu_program_register_sequence(adev,
> golden_settings_polaris10_a11,
> - (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
> + ARRAY_SIZE(golden_settings_polaris10_a11));
> break;
> case CHIP_CARRIZO:
> amdgpu_program_register_sequence(adev,
> cz_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
> + ARRAY_SIZE(cz_mgcg_cgcg_init));
> break;
> case CHIP_STONEY:
> amdgpu_program_register_sequence(adev,
> stoney_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
> + ARRAY_SIZE(stoney_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> golden_settings_stoney_common,
> - (const u32)ARRAY_SIZE(golden_settings_stoney_common));
> + ARRAY_SIZE(golden_settings_stoney_common));
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 0de4dc068516..91fc097abdfc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -687,15 +687,15 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
> case CHIP_VEGA10:
> amdgpu_program_register_sequence(adev,
> golden_settings_mmhub_1_0_0,
> - (const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0));
> + ARRAY_SIZE(golden_settings_mmhub_1_0_0));
> amdgpu_program_register_sequence(adev,
> golden_settings_athub_1_0_0,
> - (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
> + ARRAY_SIZE(golden_settings_athub_1_0_0));
> break;
> case CHIP_RAVEN:
> amdgpu_program_register_sequence(adev,
> golden_settings_athub_1_0_0,
> - (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
> + ARRAY_SIZE(golden_settings_athub_1_0_0));
> break;
> default:
> break;
> @@ -715,7 +715,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
>
> amdgpu_program_register_sequence(adev,
> golden_settings_vega10_hdp,
> - (const u32)ARRAY_SIZE(golden_settings_vega10_hdp));
> + ARRAY_SIZE(golden_settings_vega10_hdp));
>
> if (adev->gart.robj == NULL) {
> dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
> diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> index 2b435c02ef44..df52824c0cd4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
> @@ -281,29 +281,29 @@ void xgpu_vi_init_golden_registers(struct amdgpu_device *adev)
> case CHIP_FIJI:
> amdgpu_program_register_sequence(adev,
> xgpu_fiji_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(
> + ARRAY_SIZE(
> xgpu_fiji_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> xgpu_fiji_golden_settings_a10,
> - (const u32)ARRAY_SIZE(
> + ARRAY_SIZE(
> xgpu_fiji_golden_settings_a10));
> amdgpu_program_register_sequence(adev,
> xgpu_fiji_golden_common_all,
> - (const u32)ARRAY_SIZE(
> + ARRAY_SIZE(
> xgpu_fiji_golden_common_all));
> break;
> case CHIP_TONGA:
> amdgpu_program_register_sequence(adev,
> xgpu_tonga_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(
> + ARRAY_SIZE(
> xgpu_tonga_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> xgpu_tonga_golden_settings_a11,
> - (const u32)ARRAY_SIZE(
> + ARRAY_SIZE(
> xgpu_tonga_golden_settings_a11));
> amdgpu_program_register_sequence(adev,
> xgpu_tonga_golden_common_all,
> - (const u32)ARRAY_SIZE(
> + ARRAY_SIZE(
> xgpu_tonga_golden_common_all));
> break;
> default:
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index 92f8c44a73b6..121e628e7cdb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -95,10 +95,10 @@ static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
> case CHIP_TOPAZ:
> amdgpu_program_register_sequence(adev,
> iceland_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
> + ARRAY_SIZE(iceland_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> golden_settings_iceland_a11,
> - (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
> + ARRAY_SIZE(golden_settings_iceland_a11));
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 52e6bf2e9e59..c8c93f9dac21 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -194,45 +194,45 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
> case CHIP_FIJI:
> amdgpu_program_register_sequence(adev,
> fiji_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
> + ARRAY_SIZE(fiji_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> golden_settings_fiji_a10,
> - (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
> + ARRAY_SIZE(golden_settings_fiji_a10));
> break;
> case CHIP_TONGA:
> amdgpu_program_register_sequence(adev,
> tonga_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
> + ARRAY_SIZE(tonga_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> golden_settings_tonga_a11,
> - (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
> + ARRAY_SIZE(golden_settings_tonga_a11));
> break;
> case CHIP_POLARIS11:
> case CHIP_POLARIS12:
> amdgpu_program_register_sequence(adev,
> golden_settings_polaris11_a11,
> - (const u32)ARRAY_SIZE(golden_settings_polaris11_a11));
> + ARRAY_SIZE(golden_settings_polaris11_a11));
> break;
> case CHIP_POLARIS10:
> amdgpu_program_register_sequence(adev,
> golden_settings_polaris10_a11,
> - (const u32)ARRAY_SIZE(golden_settings_polaris10_a11));
> + ARRAY_SIZE(golden_settings_polaris10_a11));
> break;
> case CHIP_CARRIZO:
> amdgpu_program_register_sequence(adev,
> cz_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
> + ARRAY_SIZE(cz_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> cz_golden_settings_a11,
> - (const u32)ARRAY_SIZE(cz_golden_settings_a11));
> + ARRAY_SIZE(cz_golden_settings_a11));
> break;
> case CHIP_STONEY:
> amdgpu_program_register_sequence(adev,
> stoney_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
> + ARRAY_SIZE(stoney_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> stoney_golden_settings_a11,
> - (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
> + ARRAY_SIZE(stoney_golden_settings_a11));
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index fe78c00b9ffa..a0a5a8da4c4f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -132,18 +132,18 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
> case CHIP_VEGA10:
> amdgpu_program_register_sequence(adev,
> golden_settings_sdma_4,
> - (const u32)ARRAY_SIZE(golden_settings_sdma_4));
> + ARRAY_SIZE(golden_settings_sdma_4));
> amdgpu_program_register_sequence(adev,
> golden_settings_sdma_vg10,
> - (const u32)ARRAY_SIZE(golden_settings_sdma_vg10));
> + ARRAY_SIZE(golden_settings_sdma_vg10));
> break;
> case CHIP_RAVEN:
> amdgpu_program_register_sequence(adev,
> golden_settings_sdma_4_1,
> - (const u32)ARRAY_SIZE(golden_settings_sdma_4_1));
> + ARRAY_SIZE(golden_settings_sdma_4_1));
> amdgpu_program_register_sequence(adev,
> golden_settings_sdma_rv1,
> - (const u32)ARRAY_SIZE(golden_settings_sdma_rv1));
> + ARRAY_SIZE(golden_settings_sdma_rv1));
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
> index 8284d5dbfc30..49eef3090f08 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> @@ -1392,63 +1392,63 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
> case CHIP_TAHITI:
> amdgpu_program_register_sequence(adev,
> tahiti_golden_registers,
> - (const u32)ARRAY_SIZE(tahiti_golden_registers));
> + ARRAY_SIZE(tahiti_golden_registers));
> amdgpu_program_register_sequence(adev,
> tahiti_golden_rlc_registers,
> - (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
> + ARRAY_SIZE(tahiti_golden_rlc_registers));
> amdgpu_program_register_sequence(adev,
> tahiti_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
> + ARRAY_SIZE(tahiti_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> tahiti_golden_registers2,
> - (const u32)ARRAY_SIZE(tahiti_golden_registers2));
> + ARRAY_SIZE(tahiti_golden_registers2));
> break;
> case CHIP_PITCAIRN:
> amdgpu_program_register_sequence(adev,
> pitcairn_golden_registers,
> - (const u32)ARRAY_SIZE(pitcairn_golden_registers));
> + ARRAY_SIZE(pitcairn_golden_registers));
> amdgpu_program_register_sequence(adev,
> pitcairn_golden_rlc_registers,
> - (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
> + ARRAY_SIZE(pitcairn_golden_rlc_registers));
> amdgpu_program_register_sequence(adev,
> pitcairn_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
> + ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
> break;
> case CHIP_VERDE:
> amdgpu_program_register_sequence(adev,
> verde_golden_registers,
> - (const u32)ARRAY_SIZE(verde_golden_registers));
> + ARRAY_SIZE(verde_golden_registers));
> amdgpu_program_register_sequence(adev,
> verde_golden_rlc_registers,
> - (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
> + ARRAY_SIZE(verde_golden_rlc_registers));
> amdgpu_program_register_sequence(adev,
> verde_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
> + ARRAY_SIZE(verde_mgcg_cgcg_init));
> amdgpu_program_register_sequence(adev,
> verde_pg_init,
> - (const u32)ARRAY_SIZE(verde_pg_init));
> + ARRAY_SIZE(verde_pg_init));
> break;
> case CHIP_OLAND:
> amdgpu_program_register_sequence(adev,
> oland_golden_registers,
> - (const u32)ARRAY_SIZE(oland_golden_registers));
> + ARRAY_SIZE(oland_golden_registers));
> amdgpu_program_register_sequence(adev,
> oland_golden_rlc_registers,
> - (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
> + ARRAY_SIZE(oland_golden_rlc_registers));
> amdgpu_program_register_sequence(adev,
> oland_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
> + ARRAY_SIZE(oland_mgcg_cgcg_init));
> break;
> case CHIP_HAINAN:
> amdgpu_program_register_sequence(adev,
> hainan_golden_registers,
> - (const u32)ARRAY_SIZE(hainan_golden_registers));
> + ARRAY_SIZE(hainan_golden_registers));
> amdgpu_program_register_sequence(adev,
> hainan_golden_registers2,
> - (const u32)ARRAY_SIZE(hainan_golden_registers2));
> + ARRAY_SIZE(hainan_golden_registers2));
> amdgpu_program_register_sequence(adev,
> hainan_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(hainan_mgcg_cgcg_init));
> + ARRAY_SIZE(hainan_mgcg_cgcg_init));
> break;
>
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 4e67fe1e7955..fa27e0354f35 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -265,12 +265,12 @@ static void soc15_init_golden_registers(struct amdgpu_device *adev)
> case CHIP_VEGA10:
> amdgpu_program_register_sequence(adev,
> vega10_golden_init,
> - (const u32)ARRAY_SIZE(vega10_golden_init));
> + ARRAY_SIZE(vega10_golden_init));
> break;
> case CHIP_RAVEN:
> amdgpu_program_register_sequence(adev,
> raven_golden_init,
> - (const u32)ARRAY_SIZE(raven_golden_init));
> + ARRAY_SIZE(raven_golden_init));
> break;
> default:
> break;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
> index 3a4c2fa7e36d..bb8ca9489546 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> @@ -284,27 +284,27 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)
> case CHIP_TOPAZ:
> amdgpu_program_register_sequence(adev,
> iceland_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
> + ARRAY_SIZE(iceland_mgcg_cgcg_init));
> break;
> case CHIP_FIJI:
> amdgpu_program_register_sequence(adev,
> fiji_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
> + ARRAY_SIZE(fiji_mgcg_cgcg_init));
> break;
> case CHIP_TONGA:
> amdgpu_program_register_sequence(adev,
> tonga_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
> + ARRAY_SIZE(tonga_mgcg_cgcg_init));
> break;
> case CHIP_CARRIZO:
> amdgpu_program_register_sequence(adev,
> cz_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
> + ARRAY_SIZE(cz_mgcg_cgcg_init));
> break;
> case CHIP_STONEY:
> amdgpu_program_register_sequence(adev,
> stoney_mgcg_cgcg_init,
> - (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
> + ARRAY_SIZE(stoney_mgcg_cgcg_init));
> break;
> case CHIP_POLARIS11:
> case CHIP_POLARIS10:
> --
> 2.11.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/4] drm/amdgpu: cleanup vm_size handling
[not found] ` <20171109144925.2913-2-christian.koenig-5C7GfCeVMHo@public.gmane.org>
@ 2017-11-09 16:28 ` Alex Deucher
0 siblings, 0 replies; 8+ messages in thread
From: Alex Deucher @ 2017-11-09 16:28 UTC (permalink / raw)
To: Christian König; +Cc: amd-gfx list
On Thu, Nov 9, 2017 at 9:49 AM, Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
> It's pointless to have the same value twice, just always use max_pfn.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 18 +++++++++---------
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 7 +++----
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 -
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 -
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 -
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 13 +++++--------
> 6 files changed, 17 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 407d3dad8f97..94500358eccc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -2576,27 +2576,27 @@ void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
> * @adev: amdgpu_device pointer
> * @vm_size: the default vm size if it's set auto
> */
> -void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
> +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
> uint32_t fragment_size_default)
> {
> /* adjust vm size firstly */
> - if (amdgpu_vm_size == -1)
> - adev->vm_manager.vm_size = vm_size;
> - else
> - adev->vm_manager.vm_size = amdgpu_vm_size;
> + if (amdgpu_vm_size != -1)
> + vm_size = amdgpu_vm_size;
> +
> + adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
>
> /* block size depends on vm size */
> if (amdgpu_vm_block_size == -1)
> adev->vm_manager.block_size =
> - amdgpu_vm_get_block_size(adev->vm_manager.vm_size);
> + amdgpu_vm_get_block_size(vm_size);
> else
> adev->vm_manager.block_size = amdgpu_vm_block_size;
>
> amdgpu_vm_set_fragment_size(adev, fragment_size_default);
>
> - DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n",
> - adev->vm_manager.vm_size, adev->vm_manager.block_size,
> - adev->vm_manager.fragment_size);
> + DRM_INFO("vm size is %u GB, block size is %u-bit, fragment size is %u-bit\n",
> + vm_size, adev->vm_manager.block_size,
> + adev->vm_manager.fragment_size);
> }
>
> /**
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index aa914256b4bc..c7b796c12775 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -220,7 +220,6 @@ struct amdgpu_vm_manager {
>
> uint64_t max_pfn;
> uint32_t num_level;
> - uint64_t vm_size;
> uint32_t block_size;
> uint32_t fragment_size;
> /* vram base address for page table entry */
> @@ -312,9 +311,9 @@ struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
> void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
> struct amdgpu_bo_va *bo_va);
> void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
> - uint32_t fragment_size_default);
> -void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size,
> - uint32_t fragment_size_default);
> + uint32_t fragment_size_default);
> +void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
> + uint32_t fragment_size_default);
> int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
> bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
> struct amdgpu_job *job);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index d2a43db22cff..c8e47c36608e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -838,7 +838,6 @@ static int gmc_v6_0_sw_init(void *handle)
> return r;
>
> amdgpu_vm_adjust_size(adev, 64, 9);
> - adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
>
> adev->mc.mc_mask = 0xffffffffffULL;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index 6c6a7e14359c..2b7338e22409 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -978,7 +978,6 @@ static int gmc_v7_0_sw_init(void *handle)
> * Max GPUVM size for cayman and SI is 40 bits.
> */
> amdgpu_vm_adjust_size(adev, 64, 9);
> - adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
>
> /* Set the internal MC address mask
> * This is the max address of the GPU's
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index edbe0df24d90..e30a96a8f49b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -1075,7 +1075,6 @@ static int gmc_v8_0_sw_init(void *handle)
> * Max GPUVM size for cayman and SI is 40 bits.
> */
> amdgpu_vm_adjust_size(adev, 64, 9);
> - adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
>
> /* Set the internal MC address mask
> * This is the max address of the GPU's
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 91fc097abdfc..16bba97e704a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -555,7 +555,7 @@ static int gmc_v9_0_sw_init(void *handle)
> case CHIP_RAVEN:
> adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
> if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
> - adev->vm_manager.vm_size = 1U << 18;
> + adev->vm_manager.max_pfn = 1ULL << 36;
> adev->vm_manager.block_size = 9;
> adev->vm_manager.num_level = 3;
> amdgpu_vm_set_fragment_size(adev, 9);
> @@ -573,7 +573,7 @@ static int gmc_v9_0_sw_init(void *handle)
> * vm size is 256TB (48bit), maximum size of Vega10,
> * block size 512 (9bit)
> */
> - adev->vm_manager.vm_size = 1U << 18;
> + adev->vm_manager.max_pfn = 1ULL << 36;
> adev->vm_manager.block_size = 9;
> adev->vm_manager.num_level = 3;
> amdgpu_vm_set_fragment_size(adev, 9);
> @@ -582,10 +582,9 @@ static int gmc_v9_0_sw_init(void *handle)
> break;
> }
>
> - DRM_INFO("vm size is %llu GB, block size is %u-bit,fragment size is %u-bit\n",
> - adev->vm_manager.vm_size,
> - adev->vm_manager.block_size,
> - adev->vm_manager.fragment_size);
> + DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n",
> + adev->vm_manager.max_pfn >> 18, adev->vm_manager.block_size,
> + adev->vm_manager.fragment_size);
>
> /* This interrupt is VMC page fault.*/
> r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
> @@ -596,8 +595,6 @@ static int gmc_v9_0_sw_init(void *handle)
> if (r)
> return r;
>
> - adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
> -
> /* Set the internal MC address mask
> * This is the max address of the GPU's
> * internal address space.
> --
> 2.11.0
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2017-11-09 16:28 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-09 14:49 [PATCH 1/4] drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE result Christian König
[not found] ` <20171109144925.2913-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2017-11-09 14:49 ` [PATCH 2/4] drm/amdgpu: cleanup vm_size handling Christian König
[not found] ` <20171109144925.2913-2-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2017-11-09 16:28 ` Alex Deucher
2017-11-09 14:49 ` [PATCH 3/4] drm/amdgpu: make AMDGPU_VA_RESERVED_SIZE 64bit Christian König
2017-11-09 14:49 ` [PATCH 4/4] drm/amdgpu: fix VA hole handling on Vega10 Christian König
[not found] ` <20171109144925.2913-4-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2017-11-09 14:59 ` Michel Dänzer
[not found] ` <ebc6ec8d-4ea5-9080-fb27-a18e46f3740f-otUistvHUpPR7s880joybQ@public.gmane.org>
2017-11-09 16:15 ` Christian König
2017-11-09 16:28 ` [PATCH 1/4] drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE result Alex Deucher
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