[PATCH] MIPS: Fix odd fp register warnings with MIPS64r2

[PATCH] MIPS: Fix odd fp register warnings with MIPS64r2

[James Hogan]

From: James Hogan <jhogan@kernel.org>

Building 32-bit MIPS64r2 kernels produces warnings like the following
on certain toolchains (such as GNU assembler 2.24.90, but not GNU
assembler 2.28.51) since commit 22b8ba765a72 ("MIPS: Fix MIPS64 FP
save/restore on 32-bit kernels"), due to the exposure of fpu_save_16odd
from fpu_save_double and fpu_restore_16odd from fpu_restore_double:

arch/mips/kernel/r4k_fpu.S:47: Warning: float register should be even, was 1
...
arch/mips/kernel/r4k_fpu.S:59: Warning: float register should be even, was 1
...

This appears to be because .set mips64r2 does not change the FPU ABI to
64-bit when -march=mips64r2 (or e.g. -march=xlp) is provided on the
command line on that toolchain, from the default FPU ABI of 32-bit due
to the -mabi=32. This makes access to the odd FPU registers invalid.

Fix by explicitly changing the FPU ABI with .set fp=64 directives in
fpu_save_16odd and fpu_restore_16odd, and moving the undefine of fp up
in asmmacro.h so fp doesn't turn into $30.

Fixes: 22b8ba765a72 ("MIPS: Fix MIPS64 FP save/restore on 32-bit kernels")
Signed-off-by: James Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 4.0+: 22b8ba765a72: MIPS: Fix MIPS64 FP save/restore on 32-bit kernels
Cc: <stable@vger.kernel.org> # 4.0+
---
 arch/mips/include/asm/asmmacro.h | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index b815d7b3bd27..feb069cbf44e 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -19,6 +19,9 @@
 #include <asm/asmmacro-64.h>
 #endif
 
+/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
+#undef fp
+
 /*
  * Helper macros for generating raw instruction encodings.
  */
@@ -105,6 +108,7 @@
 	.macro	fpu_save_16odd thread
 	.set	push
 	.set	mips64r2
+	.set	fp=64
 	SET_HARDFLOAT
 	sdc1	$f1,  THREAD_FPR1(\thread)
 	sdc1	$f3,  THREAD_FPR3(\thread)
@@ -163,6 +167,7 @@
 	.macro	fpu_restore_16odd thread
 	.set	push
 	.set	mips64r2
+	.set	fp=64
 	SET_HARDFLOAT
 	ldc1	$f1,  THREAD_FPR1(\thread)
 	ldc1	$f3,  THREAD_FPR3(\thread)
@@ -234,9 +239,6 @@
 	.endm
 
 #ifdef TOOLCHAIN_SUPPORTS_MSA
-/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
-#undef fp
-
 	.macro	_cfcmsa	rd, cs
 	.set	push
 	.set	mips32r2
-- 
2.14.1

[PATCH] MIPS: Fix odd fp register warnings with MIPS64r2

[James Hogan]

From: James Hogan <jhogan@kernel.org>

Building 32-bit MIPS64r2 kernels produces warnings like the following
on certain toolchains (such as GNU assembler 2.24.90, but not GNU
assembler 2.28.51) since commit 22b8ba765a72 ("MIPS: Fix MIPS64 FP
save/restore on 32-bit kernels"), due to the exposure of fpu_save_16odd
from fpu_save_double and fpu_restore_16odd from fpu_restore_double:

arch/mips/kernel/r4k_fpu.S:47: Warning: float register should be even, was 1
...
arch/mips/kernel/r4k_fpu.S:59: Warning: float register should be even, was 1
...

This appears to be because .set mips64r2 does not change the FPU ABI to
64-bit when -march=mips64r2 (or e.g. -march=xlp) is provided on the
command line on that toolchain, from the default FPU ABI of 32-bit due
to the -mabi=32. This makes access to the odd FPU registers invalid.

Fix by explicitly changing the FPU ABI with .set fp=64 directives in
fpu_save_16odd and fpu_restore_16odd, and moving the undefine of fp up
in asmmacro.h so fp doesn't turn into $30.

Fixes: 22b8ba765a72 ("MIPS: Fix MIPS64 FP save/restore on 32-bit kernels")
Signed-off-by: James Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 4.0+: 22b8ba765a72: MIPS: Fix MIPS64 FP save/restore on 32-bit kernels
Cc: <stable@vger.kernel.org> # 4.0+
---
 arch/mips/include/asm/asmmacro.h | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h
index b815d7b3bd27..feb069cbf44e 100644
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -19,6 +19,9 @@
 #include <asm/asmmacro-64.h>
 #endif
 
+/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
+#undef fp
+
 /*
  * Helper macros for generating raw instruction encodings.
  */
@@ -105,6 +108,7 @@
 	.macro	fpu_save_16odd thread
 	.set	push
 	.set	mips64r2
+	.set	fp=64
 	SET_HARDFLOAT
 	sdc1	$f1,  THREAD_FPR1(\thread)
 	sdc1	$f3,  THREAD_FPR3(\thread)
@@ -163,6 +167,7 @@
 	.macro	fpu_restore_16odd thread
 	.set	push
 	.set	mips64r2
+	.set	fp=64
 	SET_HARDFLOAT
 	ldc1	$f1,  THREAD_FPR1(\thread)
 	ldc1	$f3,  THREAD_FPR3(\thread)
@@ -234,9 +239,6 @@
 	.endm
 
 #ifdef TOOLCHAIN_SUPPORTS_MSA
-/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
-#undef fp
-
 	.macro	_cfcmsa	rd, cs
 	.set	push
 	.set	mips32r2
-- 
2.14.1

Re: [PATCH] MIPS: Fix odd fp register warnings with MIPS64r2

[Maciej W. Rozycki]

On Fri, 10 Nov 2017, James Hogan wrote:

> Building 32-bit MIPS64r2 kernels produces warnings like the following
> on certain toolchains (such as GNU assembler 2.24.90, but not GNU
> assembler 2.28.51) since commit 22b8ba765a72 ("MIPS: Fix MIPS64 FP
> save/restore on 32-bit kernels"), due to the exposure of fpu_save_16odd
> from fpu_save_double and fpu_restore_16odd from fpu_restore_double:
> 
> arch/mips/kernel/r4k_fpu.S:47: Warning: float register should be even, was 1
> ...
> arch/mips/kernel/r4k_fpu.S:59: Warning: float register should be even, was 1
> ...

 Hmm, versions 2.24.90 and 2.28.51 are otherwise unindentified development 
snapshots; I think it would be slightly more appropriate if you referred 
to actual release versions, such as 2.25 and 2.29 respectively (if they 
indeed expose the same symptoms), especially as people other than 
toolchain developers and testers are generally expected not to use 
development snapshots.

 Also I find it suspicious that you say that the message has since 
vanished, as I can clearly reproduce it with current head (2.29.51):

$ cat oddfpr.s
	.module mips64r2
foo:
	ldc1	$f1, 0($2)
$ as -o oddfpr.o oddfpr.s
oddfpr.s: Assembler messages:
oddfpr.s:3: Warning: float register should be even, was 1
$ 

Can you send me a .s file produced from r4k_fpu.S along with compiler 
flags used?

> This appears to be because .set mips64r2 does not change the FPU ABI to
> 64-bit when -march=mips64r2 (or e.g. -march=xlp) is provided on the
> command line on that toolchain, from the default FPU ABI of 32-bit due
> to the -mabi=32. This makes access to the odd FPU registers invalid.

 Correct, the purpose of `.set arch=mips64r2', which is the canonical form 
`.set mips64r2' is equivalent to, and indeed any `.set arch=...' 
pseudo-op, is only to change the set of instructions accepted within the 
limits determined by the ABI chosen with `-mabi=...' (or its equivalent 
short forms) and not the ABI itself.

 The patch itself LGTM.

Reviewed-by: Maciej W. Rozycki <macro@mips.com>

  Maciej

Re: [PATCH] MIPS: Fix odd fp register warnings with MIPS64r2

[Maciej W. Rozycki]

On Fri, 10 Nov 2017, James Hogan wrote:

> Building 32-bit MIPS64r2 kernels produces warnings like the following
> on certain toolchains (such as GNU assembler 2.24.90, but not GNU
> assembler 2.28.51) since commit 22b8ba765a72 ("MIPS: Fix MIPS64 FP
> save/restore on 32-bit kernels"), due to the exposure of fpu_save_16odd
> from fpu_save_double and fpu_restore_16odd from fpu_restore_double:
> 
> arch/mips/kernel/r4k_fpu.S:47: Warning: float register should be even, was 1
> ...
> arch/mips/kernel/r4k_fpu.S:59: Warning: float register should be even, was 1
> ...

 Hmm, versions 2.24.90 and 2.28.51 are otherwise unindentified development 
snapshots; I think it would be slightly more appropriate if you referred 
to actual release versions, such as 2.25 and 2.29 respectively (if they 
indeed expose the same symptoms), especially as people other than 
toolchain developers and testers are generally expected not to use 
development snapshots.

 Also I find it suspicious that you say that the message has since 
vanished, as I can clearly reproduce it with current head (2.29.51):

$ cat oddfpr.s
	.module mips64r2
foo:
	ldc1	$f1, 0($2)
$ as -o oddfpr.o oddfpr.s
oddfpr.s: Assembler messages:
oddfpr.s:3: Warning: float register should be even, was 1
$ 

Can you send me a .s file produced from r4k_fpu.S along with compiler 
flags used?

> This appears to be because .set mips64r2 does not change the FPU ABI to
> 64-bit when -march=mips64r2 (or e.g. -march=xlp) is provided on the
> command line on that toolchain, from the default FPU ABI of 32-bit due
> to the -mabi=32. This makes access to the odd FPU registers invalid.

 Correct, the purpose of `.set arch=mips64r2', which is the canonical form 
`.set mips64r2' is equivalent to, and indeed any `.set arch=...' 
pseudo-op, is only to change the set of instructions accepted within the 
limits determined by the ABI chosen with `-mabi=...' (or its equivalent 
short forms) and not the ABI itself.

 The patch itself LGTM.

Reviewed-by: Maciej W. Rozycki <macro@mips.com>

  Maciej