[PATCH i-g-t 2/2] tests/perf_pmu: Add tests for engine queued stat

[Tvrtko Ursulin <tursulin@ursulin.net>]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Simple test to check correct queue-depth is reported per engine.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/perf_pmu.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 79 insertions(+)

diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 8585ed7bcee8..17f0afca6fe1 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -87,6 +87,17 @@ static uint64_t pmu_read_single(int fd)
 	return data[0];
 }
 
+static uint64_t pmu_sample_single(int fd, uint64_t *val)
+{
+	uint64_t data[2];
+
+	igt_assert_eq(read(fd, data, sizeof(data)), sizeof(data));
+
+	*val = data[0];
+
+	return data[1];
+}
+
 static void pmu_read_multi(int fd, unsigned int num, uint64_t *val)
 {
 	uint64_t buf[2 + num];
@@ -655,6 +666,65 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
 	assert_within_epsilon(val[1], slept, tolerance);
 }
 
+static double calc_queued(uint64_t d_val, uint64_t d_ns)
+{
+	return (double)d_val * 1e9 * I915_SAMPLE_QUEUED_SCALE / d_ns;
+}
+
+static void
+queued(int gem_fd, const struct intel_execution_engine2 *e)
+{
+	const unsigned long duration_ns = 500e6;
+	igt_spin_t *spin[2];
+	uint64_t val[2];
+	uint64_t ts[2];
+	int fd;
+
+	fd = open_pmu(I915_PMU_ENGINE_QUEUED(e->class, e->instance));
+
+	/*
+	 * First check on an idle engine.
+	 */
+	ts[0] = pmu_sample_single(fd, &val[0]);
+	usleep(duration_ns / 3000);
+	ts[1] = pmu_sample_single(fd, &val[1]);
+	assert_within_epsilon(calc_queued(val[1] - val[0], ts[1] - ts[0]),
+			      0.0, tolerance);
+
+	/*
+	 * First spin batch will be immediately executing.
+	 */
+	spin[0] = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e), 0);
+	igt_spin_batch_set_timeout(spin[0], duration_ns);
+
+	ts[0] = pmu_sample_single(fd, &val[0]);
+	usleep(duration_ns / 3000);
+	ts[1] = pmu_sample_single(fd, &val[1]);
+	assert_within_epsilon(calc_queued(val[1] - val[0], ts[1] - ts[0]),
+			      1.0, tolerance);
+
+	/*
+	 * Second spin batch will sit in the execution queue behind the
+	 * first one so must cause the PMU to correctly report the queued
+	 * counter.
+	 */
+	spin[1] = igt_spin_batch_new(gem_fd, 0, e2ring(gem_fd, e), 0);
+	igt_spin_batch_set_timeout(spin[1], duration_ns);
+
+	ts[0] = pmu_sample_single(fd, &val[0]);
+	usleep(duration_ns / 3000);
+	ts[1] = pmu_sample_single(fd, &val[1]);
+	assert_within_epsilon(calc_queued(val[1] - val[0], ts[1] - ts[0]),
+			      2.0, tolerance);
+
+	gem_sync(gem_fd, spin[0]->handle);
+	gem_sync(gem_fd, spin[1]->handle);
+
+	igt_spin_batch_free(gem_fd, spin[0]);
+	igt_spin_batch_free(gem_fd, spin[1]);
+	close(fd);
+}
+
 /**
  * Tests that i915 PMU corectly errors out in invalid initialization.
  * i915 PMU is uncore PMU, thus:
@@ -1112,6 +1182,9 @@ igt_main
 		igt_subtest_f("init-sema-%s", e->name)
 			init(fd, e, I915_SAMPLE_SEMA);
 
+		igt_subtest_f("init-queued-%s", e->name)
+			init(fd, e, I915_SAMPLE_QUEUED);
+
 		/**
 		 * Test that engines show no load when idle.
 		 */
@@ -1166,6 +1239,12 @@ igt_main
 		 */
 		igt_subtest_f("multi-client-%s", e->name)
 			multi_client(fd, e);
+
+		/**
+		 * Test that queued metric works.
+		 */
+		igt_subtest_f("queued-%s", e->name)
+			queued(fd, e);
 	}
 
 	/**
-- 
2.14.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx