From mboxrd@z Thu Jan 1 00:00:00 1970 From: Zhenyu Wang Subject: [GIT PULL] gvt-fixes for 4.15-rc3 Date: Wed, 6 Dec 2017 15:51:05 +0800 Message-ID: <20171206075105.wlh2ojubjczlstox@zhen-hp.sh.intel.com> Reply-To: Zhenyu Wang Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1224816386==" Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Joonas Lahtinen , Jani Nikula , "Vivi, Rodrigo" Cc: intel-gfx , "Yuan, Hang" , "Xu, Terrence" , "Lv, Zhiyuan" , intel-gvt-dev List-Id: intel-gfx@lists.freedesktop.org --===============1224816386== Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="2agmdgryqydrdn2a" Content-Disposition: inline --2agmdgryqydrdn2a Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, Here's gvt-fixes for 4.15-rc3 with several fixes backported. thanks -- The following changes since commit b721b65af4eb46df6a1d9e34b14003225e403565: drm/i915/gvt: Correct ADDR_4K/2M/1G_MASK definition (2017-11-28 17:24:30 = +0800) are available in the Git repository at: https://github.com/intel/gvt-linux.git tags/gvt-fixes-2017-12-06 for you to fetch changes up to 11474e9091cf2002e948647fd9f63a7f027e488a: drm/i915/gvt: set max priority for gvt context (2017-12-06 11:38:21 +0800) ---------------------------------------------------------------- gvt-fixes-2017-12-06 - Fix invalid hw reg read value for vGPU (Xiong) - Fix qemu warning on PCI ROM bar missing (Changbin) - Workaround preemption regression (Zhenyu) ---------------------------------------------------------------- Changbin Du (1): drm/i915/gvt: Emulate PCI expansion ROM base address register Xiong Zhang (1): drm/i915/gvt: Limit read hw reg to active vgpu Zhenyu Wang (2): drm/i915/gvt: Don't mark vgpu context as inactive when preempted drm/i915/gvt: set max priority for gvt context Zhi Wang (1): drm/i915/gvt: Export intel_gvt_render_mmio_to_ring_id() drivers/gpu/drm/i915/gvt/cfg_space.c | 21 ++++++++++++++++ drivers/gpu/drm/i915/gvt/handlers.c | 47 ++++++++++++++++++++++++++++----= ---- drivers/gpu/drm/i915/gvt/mmio.h | 2 ++ drivers/gpu/drm/i915/gvt/scheduler.c | 22 ++++++++++++++++- 4 files changed, 81 insertions(+), 11 deletions(-) --=20 Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 --2agmdgryqydrdn2a Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iF0EARECAB0WIQTXuabgHDW6LPt9CICxBBozTXgYJwUCWiehaQAKCRCxBBozTXgY J/z/AJ9ydjPo2DIfRDqxiYqCINAGp6utXwCdEDAM1MhM8+XeSSQk6DZMvhfQF+w= =q8fh -----END PGP SIGNATURE----- --2agmdgryqydrdn2a-- --===============1224816386== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============1224816386==--