From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andrew Lunn <andrew@lunn.ch>
Subject: Re: [PATCH RFC 0/4] Fixes for Marvell MII paged register access races
Date: Sat, 9 Dec 2017 20:06:10 +0100
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References: <20171208154756.GF10595@n2100.armlinux.org.uk>
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Cc: Russell King - ARM Linux <linux@armlinux.org.uk>,
        netdev@vger.kernel.org
To: Florian Fainelli <f.fainelli@gmail.com>
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> > Another potential question is whether using the mdiobus lock (which
> > excludes all other MII bus access) is best - while it has the advantage
> > of also ensuring atomicity with userspace accesses, it means that no one
> > else can access an independent PHY on the same bus while a paged access
> > is on-going.  It feels like a big hammer, but I'm not convinced that we
> > will see a lot of contention on it.
> 
> Regarding that last topic, this could become a fairly contended lock on
> a switch with lots (e.g: > 5-6) of built-in PHYs, all being polled
> (which is usually the case right now). One would expect that the polling
> should be limited to 2 BMSR reads to minimize the bus utilization.

Hi Florian

In this case, we probably are not doing pages reads, just normal
reads. So there should not be any more contention than there already
is.

	Andrew