From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com ([192.55.52.115]:48311 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752778AbdLKTD1 (ORCPT ); Mon, 11 Dec 2017 14:03:27 -0500 Date: Mon, 11 Dec 2017 21:03:23 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: "Pandiyan, Dhinakaran" Cc: "intel-gfx@lists.freedesktop.org" , "stable@vger.kernel.org" , "Runyan, Arthur J" Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915: Disable DC states around GMBUS on GLK Message-ID: <20171211190323.GR10981@intel.com> References: <20171208213739.16388-1-ville.syrjala@linux.intel.com> <1513018949.24929.4.camel@dk-H97M-D3H> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1513018949.24929.4.camel@dk-H97M-D3H> Sender: stable-owner@vger.kernel.org List-ID: On Mon, Dec 11, 2017 at 06:41:05PM +0000, Pandiyan, Dhinakaran wrote: > On Fri, 2017-12-08 at 23:37 +0200, Ville Syrjala wrote: > > From: Ville Syrj�l� > > > > Prevent the DMC from destroying GMBUS transfers on GLK. GMBUS > > lives in PG1 so DC off is all we need. > > > Just so that I understand this correctly. DMC is expected to take care > of managing power for GMBUS transfers without the driver explicitly > turning on/off the power well 1 but it isn't. Do you know if this is a > DMC regression? No idea. The docs don't seem to even mention DMC and GMBUS in the same sentence. But since DP AUX needs DC off I don't see why GMBUS would be all that different. And with bit banging I would be somewhat surprised if DMC could maintain the state of the pins while in DC5. Although I suppose it might be possible that the hw automagically prevents DC5 when we're driving any of the pins. Art? > > > Cc: stable@vger.kernel.org > > Signed-off-by: Ville Syrj�l� > > --- > > drivers/gpu/drm/i915/intel_runtime_pm.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > > index 96ab74f3d101..522e0a63090f 100644 > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > > @@ -1792,6 +1792,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, > > BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ > > BIT_ULL(POWER_DOMAIN_MODESET) | \ > > BIT_ULL(POWER_DOMAIN_AUX_A) | \ > > + BIT_ULL(POWER_DOMAIN_GMBUS) | \ > > BIT_ULL(POWER_DOMAIN_INIT)) > > > > #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ -- Ville Syrj�l� Intel OTC From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915: Disable DC states around GMBUS on GLK Date: Mon, 11 Dec 2017 21:03:23 +0200 Message-ID: <20171211190323.GR10981@intel.com> References: <20171208213739.16388-1-ville.syrjala@linux.intel.com> <1513018949.24929.4.camel@dk-H97M-D3H> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Return-path: Content-Disposition: inline In-Reply-To: <1513018949.24929.4.camel@dk-H97M-D3H> Sender: stable-owner@vger.kernel.org To: "Pandiyan, Dhinakaran" Cc: "intel-gfx@lists.freedesktop.org" , "stable@vger.kernel.org" , "Runyan, Arthur J" List-Id: intel-gfx@lists.freedesktop.org On Mon, Dec 11, 2017 at 06:41:05PM +0000, Pandiyan, Dhinakaran wrote: > On Fri, 2017-12-08 at 23:37 +0200, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Prevent the DMC from destroying GMBUS transfers on GLK. GMBUS > > lives in PG1 so DC off is all we need. > > > Just so that I understand this correctly. DMC is expected to take care > of managing power for GMBUS transfers without the driver explicitly > turning on/off the power well 1 but it isn't. Do you know if this is a > DMC regression? No idea. The docs don't seem to even mention DMC and GMBUS in the same sentence. But since DP AUX needs DC off I don't see why GMBUS would be all that different. And with bit banging I would be somewhat surprised if DMC could maintain the state of the pins while in DC5. Although I suppose it might be possible that the hw automagically prevents DC5 when we're driving any of the pins. Art? > > > Cc: stable@vger.kernel.org > > Signed-off-by: Ville Syrjälä > > --- > > drivers/gpu/drm/i915/intel_runtime_pm.c | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > > index 96ab74f3d101..522e0a63090f 100644 > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > > @@ -1792,6 +1792,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, > > BIT_ULL(POWER_DOMAIN_GT_IRQ) | \ > > BIT_ULL(POWER_DOMAIN_MODESET) | \ > > BIT_ULL(POWER_DOMAIN_AUX_A) | \ > > + BIT_ULL(POWER_DOMAIN_GMBUS) | \ > > BIT_ULL(POWER_DOMAIN_INIT)) > > > > #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ -- Ville Syrjälä Intel OTC