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diff for duplicates of <20171212203515.gpnu7cnxilkdz4hc@rob-hp-laptop>

diff --git a/a/1.txt b/N1/1.txt
index 77c6642..a52b64a 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -53,7 +53,7 @@ Fine for a fallback, but please add SoC specific compatibles.
 > +
 > +1) An HFPLL for the L2 cache.
 > +
-> +	clock-controller@f9016000 {
+> +	clock-controller at f9016000 {
 > +		compatible = "qcom,hfpll";
 > +		reg = <0xf9016000 0x30>;
 > +		clock-output-names = "hfpll_l2";
@@ -61,7 +61,7 @@ Fine for a fallback, but please add SoC specific compatibles.
 > +
 > +2) An HFPLL for CPU0. This HFPLL has the alias register region.
 > +
-> +	clock-controller@f908a000 {
+> +	clock-controller at f908a000 {
 > +		compatible = "qcom,hfpll";
 > +		reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
 > +		clock-output-names = "hfpll0";
diff --git a/a/content_digest b/N1/content_digest
index 20dfd56..a39d215 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -5,26 +5,16 @@
   "ref\0001512726150-7204-5-git-send-email-sricharan\@codeaurora.org\0"
 ]
 [
-  "From\0Rob Herring <robh\@kernel.org>\0"
+  "From\0robh\@kernel.org (Rob Herring)\0"
 ]
 [
-  "Subject\0Re: [PATCH v4 04/12] clk: qcom: Add HFPLL driver\0"
+  "Subject\0[PATCH v4 04/12] clk: qcom: Add HFPLL driver\0"
 ]
 [
   "Date\0Tue, 12 Dec 2017 14:35:15 -0600\0"
 ]
 [
-  "To\0Sricharan R <sricharan\@codeaurora.org>\0"
-]
-[
-  "Cc\0mturquette\@baylibre.com",
-  " sboyd\@codeaurora.org",
-  " devicetree\@vger.kernel.org",
-  " linux-pm\@vger.kernel.org",
-  " linux-arm-msm\@vger.kernel.org",
-  " linux-kernel\@vger.kernel.org",
-  " viresh.kumar\@linaro.org",
-  " linux-arm-kernel\@lists.infradead.org\0"
+  "To\0linux-arm-kernel\@lists.infradead.org\0"
 ]
 [
   "\0000:1\0"
@@ -88,7 +78,7 @@
   "> +\n",
   "> +1) An HFPLL for the L2 cache.\n",
   "> +\n",
-  "> +\tclock-controller\@f9016000 {\n",
+  "> +\tclock-controller at f9016000 {\n",
   "> +\t\tcompatible = \"qcom,hfpll\";\n",
   "> +\t\treg = <0xf9016000 0x30>;\n",
   "> +\t\tclock-output-names = \"hfpll_l2\";\n",
@@ -96,7 +86,7 @@
   "> +\n",
   "> +2) An HFPLL for CPU0. This HFPLL has the alias register region.\n",
   "> +\n",
-  "> +\tclock-controller\@f908a000 {\n",
+  "> +\tclock-controller at f908a000 {\n",
   "> +\t\tcompatible = \"qcom,hfpll\";\n",
   "> +\t\treg = <0xf908a000 0x30>, <0xf900a000 0x30>;\n",
   "> +\t\tclock-output-names = \"hfpll0\";\n",
@@ -152,4 +142,4 @@
   "Rob"
 ]
 
-891b274be405dc1df1744b398d351b0bc84828f97cf0adf959d5f0d1103bda70
+2d85b6c1a0420265150e0099539fb4d2f2455b480ad90bb96ca8fd78c05ec063
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