From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751166AbdLNBIF (ORCPT ); Wed, 13 Dec 2017 20:08:05 -0500 Received: from mail-pg0-f49.google.com ([74.125.83.49]:45676 "EHLO mail-pg0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750748AbdLNBID (ORCPT ); Wed, 13 Dec 2017 20:08:03 -0500 X-Google-Smtp-Source: ACJfBottFfZQm9jnSqEZ/Xc0mCd4eCRr8Qcz6oxwEpDPoz2LSDFu7maDP5W9eA324d3xVc7D4Uo0CQ== Date: Thu, 14 Dec 2017 09:07:54 +0800 From: Leo Yan To: Valentin Schneider Cc: linux-kernel@vger.kernel.org, Wei Xu , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Dietmar Eggemann , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: Re: [PATCH] arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information Message-ID: <20171214010754.GC30419@leoy-linaro> References: <1513174866-6678-1-git-send-email-valentin.schneider@arm.com> <20171213145311.GA30463@leoy-ThinkPad-T440> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Dec 13, 2017 at 03:16:13PM +0000, Valentin Schneider wrote: > Hi Leo, > > > On 12/13/2017 02:53 PM, Leo Yan wrote: > >Hi Valentin, > > > >On Wed, Dec 13, 2017 at 02:21:06PM +0000, Valentin Schneider wrote: > >>The following dt entries are added: > >> cpus [0-3] (Cortex A53): > >> - capacity-dmips-mhz = <592>; > >> > >> cpus [4-7] (Cortex A73): > >> - capacity-dmips-mhz = <1024>; > >> > >>Those values were obtained by running dhrystone 2.1 on a > >>HiKey960 with the following procedure: > >>- Offline all CPUs but CPU0 (A53) > >>- Set CPU0 frequency to maximum > >>- Run Dhrystone 2.1 for 20 seconds > >> > >>- Offline all CPUs but CPU4 (A73) > >>- set CPU4 frequency to maximum > >>- Run Dhrystone 2.1 for 20 seconds > >> > >>The results are as follows: > >>A53: 129633887 loops > >>A73: 287034147 loops > >Seems to me the capacity-dmips-mhz should be: > > > >CA53: 129633887 / 20 / 1844 = 3515 > >CA73: 287034147 / 20 / 2362 = 6076 > > > >After normalized to range [0..1024], we could get: > > > >CA53: 592 > >CA73: 1024 > > Yes, that's the "direct approach". I wanted to underline the fact that there > are two different max frequencies so what I followed would be: > > 1) Computing the performance ratio: > (129633887 / 287034147) * 1024 = 462.47 > > 2) Scaling that to the same frequency scale: > 462.47 * (2362/1844) = 592.38 > > Which gives the same end result (it's the same equation but split in two > steps). Also it makes it easy to check that the cpu_capacity sysfs entry for > the A53s gets correctly set (to 462). Yeah, thanks for clear explanation. [...] Thanks, Leo Yan From mboxrd@z Thu Jan 1 00:00:00 1970 From: Leo Yan Subject: Re: [PATCH] arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information Date: Thu, 14 Dec 2017 09:07:54 +0800 Message-ID: <20171214010754.GC30419@leoy-linaro> References: <1513174866-6678-1-git-send-email-valentin.schneider@arm.com> <20171213145311.GA30463@leoy-ThinkPad-T440> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Valentin Schneider Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Wei Xu , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Dietmar Eggemann , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org On Wed, Dec 13, 2017 at 03:16:13PM +0000, Valentin Schneider wrote: > Hi Leo, > > > On 12/13/2017 02:53 PM, Leo Yan wrote: > >Hi Valentin, > > > >On Wed, Dec 13, 2017 at 02:21:06PM +0000, Valentin Schneider wrote: > >>The following dt entries are added: > >> cpus [0-3] (Cortex A53): > >> - capacity-dmips-mhz = <592>; > >> > >> cpus [4-7] (Cortex A73): > >> - capacity-dmips-mhz = <1024>; > >> > >>Those values were obtained by running dhrystone 2.1 on a > >>HiKey960 with the following procedure: > >>- Offline all CPUs but CPU0 (A53) > >>- Set CPU0 frequency to maximum > >>- Run Dhrystone 2.1 for 20 seconds > >> > >>- Offline all CPUs but CPU4 (A73) > >>- set CPU4 frequency to maximum > >>- Run Dhrystone 2.1 for 20 seconds > >> > >>The results are as follows: > >>A53: 129633887 loops > >>A73: 287034147 loops > >Seems to me the capacity-dmips-mhz should be: > > > >CA53: 129633887 / 20 / 1844 = 3515 > >CA73: 287034147 / 20 / 2362 = 6076 > > > >After normalized to range [0..1024], we could get: > > > >CA53: 592 > >CA73: 1024 > > Yes, that's the "direct approach". I wanted to underline the fact that there > are two different max frequencies so what I followed would be: > > 1) Computing the performance ratio: > (129633887 / 287034147) * 1024 = 462.47 > > 2) Scaling that to the same frequency scale: > 462.47 * (2362/1844) = 592.38 > > Which gives the same end result (it's the same equation but split in two > steps). Also it makes it easy to check that the cpu_capacity sysfs entry for > the A53s gets correctly set (to 462). Yeah, thanks for clear explanation. [...] Thanks, Leo Yan -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: leo.yan@linaro.org (Leo Yan) Date: Thu, 14 Dec 2017 09:07:54 +0800 Subject: [PATCH] arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information In-Reply-To: References: <1513174866-6678-1-git-send-email-valentin.schneider@arm.com> <20171213145311.GA30463@leoy-ThinkPad-T440> Message-ID: <20171214010754.GC30419@leoy-linaro> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Wed, Dec 13, 2017 at 03:16:13PM +0000, Valentin Schneider wrote: > Hi Leo, > > > On 12/13/2017 02:53 PM, Leo Yan wrote: > >Hi Valentin, > > > >On Wed, Dec 13, 2017 at 02:21:06PM +0000, Valentin Schneider wrote: > >>The following dt entries are added: > >> cpus [0-3] (Cortex A53): > >> - capacity-dmips-mhz = <592>; > >> > >> cpus [4-7] (Cortex A73): > >> - capacity-dmips-mhz = <1024>; > >> > >>Those values were obtained by running dhrystone 2.1 on a > >>HiKey960 with the following procedure: > >>- Offline all CPUs but CPU0 (A53) > >>- Set CPU0 frequency to maximum > >>- Run Dhrystone 2.1 for 20 seconds > >> > >>- Offline all CPUs but CPU4 (A73) > >>- set CPU4 frequency to maximum > >>- Run Dhrystone 2.1 for 20 seconds > >> > >>The results are as follows: > >>A53: 129633887 loops > >>A73: 287034147 loops > >Seems to me the capacity-dmips-mhz should be: > > > >CA53: 129633887 / 20 / 1844 = 3515 > >CA73: 287034147 / 20 / 2362 = 6076 > > > >After normalized to range [0..1024], we could get: > > > >CA53: 592 > >CA73: 1024 > > Yes, that's the "direct approach". I wanted to underline the fact that there > are two different max frequencies so what I followed would be: > > 1) Computing the performance ratio: > (129633887 / 287034147) * 1024 = 462.47 > > 2) Scaling that to the same frequency scale: > 462.47 * (2362/1844) = 592.38 > > Which gives the same end result (it's the same equation but split in two > steps). Also it makes it easy to check that the cpu_capacity sysfs entry for > the A53s gets correctly set (to 462). Yeah, thanks for clear explanation. [...] Thanks, Leo Yan