From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53334) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ePIpG-0005gL-Mk for qemu-devel@nongnu.org; Wed, 13 Dec 2017 21:00:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ePIpF-0003N6-El for qemu-devel@nongnu.org; Wed, 13 Dec 2017 21:00:42 -0500 Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 13 Dec 2017 23:00:18 -0300 Message-Id: <20171214020025.4004-2-f4bug@amsat.org> In-Reply-To: <20171214020025.4004-1-f4bug@amsat.org> References: <20171214020025.4004-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH 1/8] sdhci: add a "sd-spec-version" property List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alistair Francis , "Edgar E . Iglesias" , Prasad J Pandit , Peter Maydell , Andrzej Zaborowski , Andrew Baumann , Andrey Smirnov , Andrey Yurovsky Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Peter Crosthwaite , Sai Pavan Boddu default to SDHCI v2 Signed-off-by: Philippe Mathieu-Daudé --- I am not sure which real VENDOR is HCVER=0x24, we probably don't care. hw/sd/sdhci-internal.h | 4 ++-- include/hw/sd/sdhci.h | 10 ++++++++++ hw/sd/sdhci.c | 5 ++++- 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index e941bc2386..7e4a9d79d1 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -210,9 +210,9 @@ /* Slot interrupt status */ #define SDHC_SLOT_INT_STATUS 0xFC -/* HWInit Host Controller Version Register 0x0401 */ +/* HWInit Host Controller Version Register */ #define SDHC_HCVER 0xFE -#define SD_HOST_SPECv2_VERS 0x2401 +#define SDHC_HCVER_VENDOR 0x24 #define SDHC_REGISTERS_MAP_SIZE 0x100 #define SDHC_INSERTION_DELAY (NANOSECONDS_PER_SECOND) diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index 579e0ea644..f8e91ce903 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -88,6 +88,9 @@ typedef struct SDHCIState { /* Force Event Auto CMD12 Error Interrupt Reg - write only */ /* Force Event Error Interrupt Register- write only */ /* RO Host Controller Version Register always reads as 0x2401 */ + struct { + uint8_t spec_version; + } capabilities; } SDHCIState; #define TYPE_PCI_SDHCI "sdhci-pci" @@ -97,4 +100,11 @@ typedef struct SDHCIState { #define SYSBUS_SDHCI(obj) \ OBJECT_CHECK(SDHCIState, (obj), TYPE_SYSBUS_SDHCI) +/* Host Controller Specification Version */ +enum sdhci_spec_version { + SD_HOST_SPECv1_VERS = 0x00, + SD_HOST_SPECv2_VERS = 0x01, + SD_HOST_SPECv3_VERS = 0x02 +}; + #endif /* SDHCI_H */ diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index d8188fdc2a..d6145342fb 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -908,7 +908,8 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) ret = (uint32_t)(s->admasysaddr >> 32); break; case SDHC_SLOT_INT_STATUS: - ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s); + ret = (SDHC_HCVER_VENDOR << 24) | (s->capabilities.spec_version << 16); + ret |= sdhci_slotint(s); break; default: qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " " @@ -1263,6 +1264,8 @@ const VMStateDescription sdhci_vmstate = { /* Capabilities registers provide information on supported features of this * specific host controller implementation */ static Property sdhci_properties[] = { + DEFINE_PROP_UINT8("sd-spec-version", SDHCIState, + capabilities.spec_version, SD_HOST_SPECv2_VERS), DEFINE_PROP_UINT32("capareg", SDHCIState, capareg, UINT32_MAX), DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0), DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, -- 2.15.1