[PATCH v2] x86: update/correct opcodes map

[PATCH v2] x86: update/correct opcodes map

[Randy Dunlap]

From: Randy Dunlap <rdunlap@infradead.org>

Update x86-opcode-map.txt based on the October 2017 Intel SDM publication.
Correct INVPID to INVVPID.
Add UD0 and UD1 instruction opcodes.

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Masami Hiramatsu <mhiramat@kernel.org>
Cc: Masami Hiramatsu <masami.hiramatsu@gmail.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: x86 maintainers <x86@kernel.org>
---

v2 changes:
. correct email address.
. add full Grp10 table
. use # comments as requested

 arch/x86/lib/x86-opcode-map.txt |   15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)


--- lnx-415-rc3.orig/arch/x86/lib/x86-opcode-map.txt
+++ lnx-415-rc3/arch/x86/lib/x86-opcode-map.txt
@@ -533,7 +533,7 @@ b5: LGS Gv,Mp
 b6: MOVZX Gv,Eb
 b7: MOVZX Gv,Ew
 b8: JMPE (!F3) | POPCNT Gv,Ev (F3)
-b9: Grp10 (1A)
+b9: Grp10 (1A) # all UD1
 ba: Grp8 Ev,Ib (1A)
 bb: BTC Ev,Gv
 bc: BSF Gv,Ev (!F3) | TZCNT Gv,Ev (F3)
@@ -607,7 +607,7 @@ fb: psubq Pq,Qq | vpsubq Vx,Hx,Wx (66),(
 fc: paddb Pq,Qq | vpaddb Vx,Hx,Wx (66),(v1)
 fd: paddw Pq,Qq | vpaddw Vx,Hx,Wx (66),(v1)
 fe: paddd Pq,Qq | vpaddd Vx,Hx,Wx (66),(v1)
-ff:
+ff: UD0
 EndTable
 
 Table: 3-byte opcode 1 (0x0f 0x38)
@@ -717,7 +717,7 @@ AVXcode: 2
 7e: vpermt2d/q Vx,Hx,Wx (66),(ev)
 7f: vpermt2ps/d Vx,Hx,Wx (66),(ev)
 80: INVEPT Gy,Mdq (66)
-81: INVPID Gy,Mdq (66)
+81: INVVPID Gy,Mdq (66)
 82: INVPCID Gy,Mdq (66)
 83: vpmultishiftqb Vx,Hx,Wx (66),(ev)
 88: vexpandps/d Vpd,Wpd (66),(ev)
@@ -970,6 +970,15 @@ GrpTable: Grp9
 EndTable
 
 GrpTable: Grp10
+# all are UD1
+0: UD1
+1: UD1
+2: UD1
+3: UD1
+4: UD1
+5: UD1
+6: UD1
+7: UD1
 EndTable
 
 # Grp11A and Grp11B are expressed as Grp11 in Intel SDM

Re: [PATCH v2] x86: update/correct opcodes map

[Masami Hiramatsu]

On Mon, 11 Dec 2017 10:38:36 -0800
Randy Dunlap <rdunlap@infradead.org> wrote:

> From: Randy Dunlap <rdunlap@infradead.org>
> 
> Update x86-opcode-map.txt based on the October 2017 Intel SDM publication.
> Correct INVPID to INVVPID.
> Add UD0 and UD1 instruction opcodes.
> 

Looks good to me :)

Acked-by: Masami Hiramatsu <mhiramat@kernel.org>

Ingo, could you pull this change?

Thank you,

> Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
> Cc: Masami Hiramatsu <mhiramat@kernel.org>
> Cc: Masami Hiramatsu <masami.hiramatsu@gmail.com>
> Cc: Josh Poimboeuf <jpoimboe@redhat.com>
> Cc: x86 maintainers <x86@kernel.org>
> ---
> 
> v2 changes:
> . correct email address.
> . add full Grp10 table
> . use # comments as requested
> 
>  arch/x86/lib/x86-opcode-map.txt |   15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> 
> --- lnx-415-rc3.orig/arch/x86/lib/x86-opcode-map.txt
> +++ lnx-415-rc3/arch/x86/lib/x86-opcode-map.txt
> @@ -533,7 +533,7 @@ b5: LGS Gv,Mp
>  b6: MOVZX Gv,Eb
>  b7: MOVZX Gv,Ew
>  b8: JMPE (!F3) | POPCNT Gv,Ev (F3)
> -b9: Grp10 (1A)
> +b9: Grp10 (1A) # all UD1
>  ba: Grp8 Ev,Ib (1A)
>  bb: BTC Ev,Gv
>  bc: BSF Gv,Ev (!F3) | TZCNT Gv,Ev (F3)
> @@ -607,7 +607,7 @@ fb: psubq Pq,Qq | vpsubq Vx,Hx,Wx (66),(
>  fc: paddb Pq,Qq | vpaddb Vx,Hx,Wx (66),(v1)
>  fd: paddw Pq,Qq | vpaddw Vx,Hx,Wx (66),(v1)
>  fe: paddd Pq,Qq | vpaddd Vx,Hx,Wx (66),(v1)
> -ff:
> +ff: UD0
>  EndTable
>  
>  Table: 3-byte opcode 1 (0x0f 0x38)
> @@ -717,7 +717,7 @@ AVXcode: 2
>  7e: vpermt2d/q Vx,Hx,Wx (66),(ev)
>  7f: vpermt2ps/d Vx,Hx,Wx (66),(ev)
>  80: INVEPT Gy,Mdq (66)
> -81: INVPID Gy,Mdq (66)
> +81: INVVPID Gy,Mdq (66)
>  82: INVPCID Gy,Mdq (66)
>  83: vpmultishiftqb Vx,Hx,Wx (66),(ev)
>  88: vexpandps/d Vpd,Wpd (66),(ev)
> @@ -970,6 +970,15 @@ GrpTable: Grp9
>  EndTable
>  
>  GrpTable: Grp10
> +# all are UD1
> +0: UD1
> +1: UD1
> +2: UD1
> +3: UD1
> +4: UD1
> +5: UD1
> +6: UD1
> +7: UD1
>  EndTable
>  
>  # Grp11A and Grp11B are expressed as Grp11 in Intel SDM
> 
> 


-- 
Masami Hiramatsu <mhiramat@kernel.org>

Re: [PATCH v2] x86: update/correct opcodes map

[Ingo Molnar]

* Randy Dunlap <rdunlap@infradead.org> wrote:

> From: Randy Dunlap <rdunlap@infradead.org>
> 
> Update x86-opcode-map.txt based on the October 2017 Intel SDM publication.
> Correct INVPID to INVVPID.
> Add UD0 and UD1 instruction opcodes.
> 
> Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
> Cc: Masami Hiramatsu <mhiramat@kernel.org>
> Cc: Masami Hiramatsu <masami.hiramatsu@gmail.com>
> Cc: Josh Poimboeuf <jpoimboe@redhat.com>
> Cc: x86 maintainers <x86@kernel.org>
> ---
> 
> v2 changes:
> . correct email address.
> . add full Grp10 table
> . use # comments as requested
> 
>  arch/x86/lib/x86-opcode-map.txt |   15 ++++++++++++---
>  1 file changed, 12 insertions(+), 3 deletions(-)
> 
> 
> --- lnx-415-rc3.orig/arch/x86/lib/x86-opcode-map.txt
> +++ lnx-415-rc3/arch/x86/lib/x86-opcode-map.txt
> @@ -533,7 +533,7 @@ b5: LGS Gv,Mp
>  b6: MOVZX Gv,Eb
>  b7: MOVZX Gv,Ew
>  b8: JMPE (!F3) | POPCNT Gv,Ev (F3)
> -b9: Grp10 (1A)
> +b9: Grp10 (1A) # all UD1

This change breaks the tools/objtool parser:

  GEN      arch/x86/insn/inat-tables.c
 Semantic error at 536: # is not a separator
 arch/x86/Build:7: recipe for target 'arch/x86/insn/inat-tables.c' failed

so I left it out for the time being.

Thanks,

	Ingo

Re: [PATCH v2] x86: update/correct opcodes map

[Masami Hiramatsu]

On Fri, 15 Dec 2017 13:35:47 +0100
Ingo Molnar <mingo@kernel.org> wrote:

> 
> * Randy Dunlap <rdunlap@infradead.org> wrote:
> 
> > From: Randy Dunlap <rdunlap@infradead.org>
> > 
> > Update x86-opcode-map.txt based on the October 2017 Intel SDM publication.
> > Correct INVPID to INVVPID.
> > Add UD0 and UD1 instruction opcodes.
> > 
> > Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
> > Cc: Masami Hiramatsu <mhiramat@kernel.org>
> > Cc: Masami Hiramatsu <masami.hiramatsu@gmail.com>
> > Cc: Josh Poimboeuf <jpoimboe@redhat.com>
> > Cc: x86 maintainers <x86@kernel.org>
> > ---
> > 
> > v2 changes:
> > . correct email address.
> > . add full Grp10 table
> > . use # comments as requested
> > 
> >  arch/x86/lib/x86-opcode-map.txt |   15 ++++++++++++---
> >  1 file changed, 12 insertions(+), 3 deletions(-)
> > 
> > 
> > --- lnx-415-rc3.orig/arch/x86/lib/x86-opcode-map.txt
> > +++ lnx-415-rc3/arch/x86/lib/x86-opcode-map.txt
> > @@ -533,7 +533,7 @@ b5: LGS Gv,Mp
> >  b6: MOVZX Gv,Eb
> >  b7: MOVZX Gv,Ew
> >  b8: JMPE (!F3) | POPCNT Gv,Ev (F3)
> > -b9: Grp10 (1A)
> > +b9: Grp10 (1A) # all UD1
> 
> This change breaks the tools/objtool parser:
> 
>   GEN      arch/x86/insn/inat-tables.c
>  Semantic error at 536: # is not a separator
>  arch/x86/Build:7: recipe for target 'arch/x86/insn/inat-tables.c' failed
> 
> so I left it out for the time being.
>

Oops, thank you, I'll fix parser to support comment in line.

Thanks!
 
> Thanks,
> 
> 	Ingo


-- 
Masami Hiramatsu <mhiramat@kernel.org>

[tip:x86/urgent] x86/decoder: Fix and update the opcodes map

[tip-bot for Randy Dunlap]

Commit-ID:  f5b5fab1780c98b74526dbac527574bd02dc16f8
Gitweb:     https://git.kernel.org/tip/f5b5fab1780c98b74526dbac527574bd02dc16f8
Author:     Randy Dunlap <rdunlap@infradead.org>
AuthorDate: Mon, 11 Dec 2017 10:38:36 -0800
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Fri, 15 Dec 2017 13:45:20 +0100

x86/decoder: Fix and update the opcodes map

Update x86-opcode-map.txt based on the October 2017 Intel SDM publication.
Fix INVPID to INVVPID.
Add UD0 and UD1 instruction opcodes.

Also sync the objtool and perf tooling copies of this file.

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Acked-by: Masami Hiramatsu <mhiramat@kernel.org>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Masami Hiramatsu <masami.hiramatsu@gmail.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/aac062d7-c0f6-96e3-5c92-ed299e2bd3da@infradead.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/lib/x86-opcode-map.txt                     | 13 +++++++++++--
 tools/objtool/arch/x86/insn/x86-opcode-map.txt      | 15 ++++++++++++---
 tools/perf/util/intel-pt-decoder/x86-opcode-map.txt | 15 ++++++++++++---
 3 files changed, 35 insertions(+), 8 deletions(-)

diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt
index c4d5591..e0b8593 100644
--- a/arch/x86/lib/x86-opcode-map.txt
+++ b/arch/x86/lib/x86-opcode-map.txt
@@ -607,7 +607,7 @@ fb: psubq Pq,Qq | vpsubq Vx,Hx,Wx (66),(v1)
 fc: paddb Pq,Qq | vpaddb Vx,Hx,Wx (66),(v1)
 fd: paddw Pq,Qq | vpaddw Vx,Hx,Wx (66),(v1)
 fe: paddd Pq,Qq | vpaddd Vx,Hx,Wx (66),(v1)
-ff:
+ff: UD0
 EndTable
 
 Table: 3-byte opcode 1 (0x0f 0x38)
@@ -717,7 +717,7 @@ AVXcode: 2
 7e: vpermt2d/q Vx,Hx,Wx (66),(ev)
 7f: vpermt2ps/d Vx,Hx,Wx (66),(ev)
 80: INVEPT Gy,Mdq (66)
-81: INVPID Gy,Mdq (66)
+81: INVVPID Gy,Mdq (66)
 82: INVPCID Gy,Mdq (66)
 83: vpmultishiftqb Vx,Hx,Wx (66),(ev)
 88: vexpandps/d Vpd,Wpd (66),(ev)
@@ -970,6 +970,15 @@ GrpTable: Grp9
 EndTable
 
 GrpTable: Grp10
+# all are UD1
+0: UD1
+1: UD1
+2: UD1
+3: UD1
+4: UD1
+5: UD1
+6: UD1
+7: UD1
 EndTable
 
 # Grp11A and Grp11B are expressed as Grp11 in Intel SDM
diff --git a/tools/objtool/arch/x86/insn/x86-opcode-map.txt b/tools/objtool/arch/x86/insn/x86-opcode-map.txt
index 12e3771..e0b8593 100644
--- a/tools/objtool/arch/x86/insn/x86-opcode-map.txt
+++ b/tools/objtool/arch/x86/insn/x86-opcode-map.txt
@@ -607,7 +607,7 @@ fb: psubq Pq,Qq | vpsubq Vx,Hx,Wx (66),(v1)
 fc: paddb Pq,Qq | vpaddb Vx,Hx,Wx (66),(v1)
 fd: paddw Pq,Qq | vpaddw Vx,Hx,Wx (66),(v1)
 fe: paddd Pq,Qq | vpaddd Vx,Hx,Wx (66),(v1)
-ff:
+ff: UD0
 EndTable
 
 Table: 3-byte opcode 1 (0x0f 0x38)
@@ -717,7 +717,7 @@ AVXcode: 2
 7e: vpermt2d/q Vx,Hx,Wx (66),(ev)
 7f: vpermt2ps/d Vx,Hx,Wx (66),(ev)
 80: INVEPT Gy,Mdq (66)
-81: INVPID Gy,Mdq (66)
+81: INVVPID Gy,Mdq (66)
 82: INVPCID Gy,Mdq (66)
 83: vpmultishiftqb Vx,Hx,Wx (66),(ev)
 88: vexpandps/d Vpd,Wpd (66),(ev)
@@ -896,7 +896,7 @@ EndTable
 
 GrpTable: Grp3_1
 0: TEST Eb,Ib
-1:
+1: TEST Eb,Ib
 2: NOT Eb
 3: NEG Eb
 4: MUL AL,Eb
@@ -970,6 +970,15 @@ GrpTable: Grp9
 EndTable
 
 GrpTable: Grp10
+# all are UD1
+0: UD1
+1: UD1
+2: UD1
+3: UD1
+4: UD1
+5: UD1
+6: UD1
+7: UD1
 EndTable
 
 # Grp11A and Grp11B are expressed as Grp11 in Intel SDM
diff --git a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt
index 12e3771..e0b8593 100644
--- a/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt
+++ b/tools/perf/util/intel-pt-decoder/x86-opcode-map.txt
@@ -607,7 +607,7 @@ fb: psubq Pq,Qq | vpsubq Vx,Hx,Wx (66),(v1)
 fc: paddb Pq,Qq | vpaddb Vx,Hx,Wx (66),(v1)
 fd: paddw Pq,Qq | vpaddw Vx,Hx,Wx (66),(v1)
 fe: paddd Pq,Qq | vpaddd Vx,Hx,Wx (66),(v1)
-ff:
+ff: UD0
 EndTable
 
 Table: 3-byte opcode 1 (0x0f 0x38)
@@ -717,7 +717,7 @@ AVXcode: 2
 7e: vpermt2d/q Vx,Hx,Wx (66),(ev)
 7f: vpermt2ps/d Vx,Hx,Wx (66),(ev)
 80: INVEPT Gy,Mdq (66)
-81: INVPID Gy,Mdq (66)
+81: INVVPID Gy,Mdq (66)
 82: INVPCID Gy,Mdq (66)
 83: vpmultishiftqb Vx,Hx,Wx (66),(ev)
 88: vexpandps/d Vpd,Wpd (66),(ev)
@@ -896,7 +896,7 @@ EndTable
 
 GrpTable: Grp3_1
 0: TEST Eb,Ib
-1:
+1: TEST Eb,Ib
 2: NOT Eb
 3: NEG Eb
 4: MUL AL,Eb
@@ -970,6 +970,15 @@ GrpTable: Grp9
 EndTable
 
 GrpTable: Grp10
+# all are UD1
+0: UD1
+1: UD1
+2: UD1
+3: UD1
+4: UD1
+5: UD1
+6: UD1
+7: UD1
 EndTable
 
 # Grp11A and Grp11B are expressed as Grp11 in Intel SDM