From: Peter Zijlstra <peterz@infradead.org>
To: tglx@linutronix.de, linux-kernel@vger.kernel.org
Cc: x86@kernel.org, peterz@infradead.org, rui.zhang@intel.com,
len.brown@intel.com
Subject: [PATCH 2/3] x86/time: Unconditionally register legacy timer interrupt
Date: Fri, 22 Dec 2017 10:20:12 +0100 [thread overview]
Message-ID: <20171222092243.382623763@infradead.org> (raw)
In-Reply-To: 20171222092010.732743589@infradead.org
[-- Attachment #1: peterz-uncondition-legacy-timer.patch --]
[-- Type: text/plain, Size: 786 bytes --]
Even without a PIC/PIT we need the legacy timer interrupt for HPET in
legacy replacement mode.
Cc: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
arch/x86/kernel/time.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
--- a/arch/x86/kernel/time.c
+++ b/arch/x86/kernel/time.c
@@ -69,9 +69,12 @@ static struct irqaction irq0 = {
static void __init setup_default_timer_irq(void)
{
- if (!nr_legacy_irqs())
- return;
- setup_irq(0, &irq0);
+ /*
+ * Unconditionally register the legacy timer; even without legacy
+ * PIC/PIT we need this for the HPET0 in legacy replacement mode.
+ */
+ if (setup_irq(0, &irq0))
+ pr_info("Failed to register legacy timer interrupt\n");
}
/* Default timer init function */
next prev parent reply other threads:[~2017-12-22 9:24 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-22 9:20 [PATCH 0/3] x86 time bits Peter Zijlstra
2017-12-22 9:20 ` [PATCH 1/3] x86/tsc: Allow TSC calibration without PIT Peter Zijlstra
2018-01-14 19:21 ` [tip:x86/timers] " tip-bot for Peter Zijlstra
2017-12-22 9:20 ` Peter Zijlstra [this message]
2018-01-14 19:22 ` [tip:x86/timers] x86/time: Unconditionally register legacy timer interrupt tip-bot for Peter Zijlstra
2017-12-22 9:20 ` [PATCH 3/3] x86/tsc: Introduce early tsc clocksource Peter Zijlstra
2018-01-14 19:22 ` [tip:x86/timers] " tip-bot for Peter Zijlstra
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