* [PATCH 0/3] x86 time bits
@ 2017-12-22 9:20 Peter Zijlstra
2017-12-22 9:20 ` [PATCH 1/3] x86/tsc: Allow TSC calibration without PIT Peter Zijlstra
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Peter Zijlstra @ 2017-12-22 9:20 UTC (permalink / raw)
To: tglx, linux-kernel; +Cc: x86, peterz, rui.zhang, len.brown
Various x86 time keeping patches I've collected over the past week.
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 1/3] x86/tsc: Allow TSC calibration without PIT 2017-12-22 9:20 [PATCH 0/3] x86 time bits Peter Zijlstra @ 2017-12-22 9:20 ` Peter Zijlstra 2018-01-14 19:21 ` [tip:x86/timers] " tip-bot for Peter Zijlstra 2017-12-22 9:20 ` [PATCH 2/3] x86/time: Unconditionally register legacy timer interrupt Peter Zijlstra 2017-12-22 9:20 ` [PATCH 3/3] x86/tsc: Introduce early tsc clocksource Peter Zijlstra 2 siblings, 1 reply; 7+ messages in thread From: Peter Zijlstra @ 2017-12-22 9:20 UTC (permalink / raw) To: tglx, linux-kernel; +Cc: x86, peterz, rui.zhang, len.brown [-- Attachment #1: peterz-no-pit.patch --] [-- Type: text/plain, Size: 2250 bytes --] Zhang Rui reported that a Surface Pro 4 will fail to boot with lapic=notscdeadline. Part of the problem is that that machine doesn't have a PIC. If, for some reason, we fall back to TSC calibration, we rely on the PIT to be present. Allow TSC calibration to reliably fall back to HPET. The below results in an accurate TSC measurement when forced on my IVB: tsc: Unable to calibrate against PIT tsc: No reference (HPET/PMTIMER) available tsc: Unable to calibrate against PIT tsc: using HPET reference calibration tsc: Detected 2792.451 MHz processor Cc: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> --- arch/x86/include/asm/i8259.h | 5 +++++ arch/x86/kernel/tsc.c | 18 ++++++++++++++++++ 2 files changed, 23 insertions(+) --- a/arch/x86/include/asm/i8259.h +++ b/arch/x86/include/asm/i8259.h @@ -69,6 +69,11 @@ struct legacy_pic { extern struct legacy_pic *legacy_pic; extern struct legacy_pic null_legacy_pic; +static inline bool has_legacy_pic(void) +{ + return legacy_pic != &null_legacy_pic; +} + static inline int nr_legacy_irqs(void) { return legacy_pic->nr_legacy_irqs; --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -25,6 +25,7 @@ #include <asm/geode.h> #include <asm/apic.h> #include <asm/intel-family.h> +#include <asm/i8259.h> unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ EXPORT_SYMBOL(cpu_khz); @@ -363,6 +364,20 @@ static unsigned long pit_calibrate_tsc(u unsigned long tscmin, tscmax; int pitcnt; + if (!has_legacy_pic()) { + /* + * Relies on tsc_early_delay_calibrate() to have given us semi + * usable udelay(), wait for the same 50ms we would have with + * the PIT loop below. + */ + udelay(10 * USEC_PER_MSEC); + udelay(10 * USEC_PER_MSEC); + udelay(10 * USEC_PER_MSEC); + udelay(10 * USEC_PER_MSEC); + udelay(10 * USEC_PER_MSEC); + return ULONG_MAX; + } + /* Set the Gate high, disable speaker */ outb((inb(0x61) & ~0x02) | 0x01, 0x61); @@ -487,6 +502,9 @@ static unsigned long quick_pit_calibrate u64 tsc, delta; unsigned long d1, d2; + if (!has_legacy_pic()) + return 0; + /* Set the Gate high, disable speaker */ outb((inb(0x61) & ~0x02) | 0x01, 0x61); ^ permalink raw reply [flat|nested] 7+ messages in thread
* [tip:x86/timers] x86/tsc: Allow TSC calibration without PIT 2017-12-22 9:20 ` [PATCH 1/3] x86/tsc: Allow TSC calibration without PIT Peter Zijlstra @ 2018-01-14 19:21 ` tip-bot for Peter Zijlstra 0 siblings, 0 replies; 7+ messages in thread From: tip-bot for Peter Zijlstra @ 2018-01-14 19:21 UTC (permalink / raw) To: linux-tip-commits; +Cc: linux-kernel, tglx, hpa, peterz, mingo Commit-ID: 30c7e5b123673d5e570e238dbada2fb68a87212c Gitweb: https://git.kernel.org/tip/30c7e5b123673d5e570e238dbada2fb68a87212c Author: Peter Zijlstra <peterz@infradead.org> AuthorDate: Fri, 22 Dec 2017 10:20:11 +0100 Committer: Thomas Gleixner <tglx@linutronix.de> CommitDate: Sun, 14 Jan 2018 20:18:23 +0100 x86/tsc: Allow TSC calibration without PIT Zhang Rui reported that a Surface Pro 4 will fail to boot with lapic=notscdeadline. Part of the problem is that that machine doesn't have a PIT. If, for some reason, the TSC init has to fall back to TSC calibration, it relies on the PIT to be present. Allow TSC calibration to reliably fall back to HPET. The below results in an accurate TSC measurement when forced on a IVB: tsc: Unable to calibrate against PIT tsc: No reference (HPET/PMTIMER) available tsc: Unable to calibrate against PIT tsc: using HPET reference calibration tsc: Detected 2792.451 MHz processor Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: len.brown@intel.com Cc: rui.zhang@intel.com Link: https://lkml.kernel.org/r/20171222092243.333145937@infradead.org --- arch/x86/include/asm/i8259.h | 5 +++++ arch/x86/kernel/tsc.c | 18 ++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/arch/x86/include/asm/i8259.h b/arch/x86/include/asm/i8259.h index c8376b4..5cdcdbd 100644 --- a/arch/x86/include/asm/i8259.h +++ b/arch/x86/include/asm/i8259.h @@ -69,6 +69,11 @@ struct legacy_pic { extern struct legacy_pic *legacy_pic; extern struct legacy_pic null_legacy_pic; +static inline bool has_legacy_pic(void) +{ + return legacy_pic != &null_legacy_pic; +} + static inline int nr_legacy_irqs(void) { return legacy_pic->nr_legacy_irqs; diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index e169e85..a2c9dd8 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -25,6 +25,7 @@ #include <asm/geode.h> #include <asm/apic.h> #include <asm/intel-family.h> +#include <asm/i8259.h> unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */ EXPORT_SYMBOL(cpu_khz); @@ -363,6 +364,20 @@ static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) unsigned long tscmin, tscmax; int pitcnt; + if (!has_legacy_pic()) { + /* + * Relies on tsc_early_delay_calibrate() to have given us semi + * usable udelay(), wait for the same 50ms we would have with + * the PIT loop below. + */ + udelay(10 * USEC_PER_MSEC); + udelay(10 * USEC_PER_MSEC); + udelay(10 * USEC_PER_MSEC); + udelay(10 * USEC_PER_MSEC); + udelay(10 * USEC_PER_MSEC); + return ULONG_MAX; + } + /* Set the Gate high, disable speaker */ outb((inb(0x61) & ~0x02) | 0x01, 0x61); @@ -487,6 +502,9 @@ static unsigned long quick_pit_calibrate(void) u64 tsc, delta; unsigned long d1, d2; + if (!has_legacy_pic()) + return 0; + /* Set the Gate high, disable speaker */ outb((inb(0x61) & ~0x02) | 0x01, 0x61); ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] x86/time: Unconditionally register legacy timer interrupt 2017-12-22 9:20 [PATCH 0/3] x86 time bits Peter Zijlstra 2017-12-22 9:20 ` [PATCH 1/3] x86/tsc: Allow TSC calibration without PIT Peter Zijlstra @ 2017-12-22 9:20 ` Peter Zijlstra 2018-01-14 19:22 ` [tip:x86/timers] " tip-bot for Peter Zijlstra 2017-12-22 9:20 ` [PATCH 3/3] x86/tsc: Introduce early tsc clocksource Peter Zijlstra 2 siblings, 1 reply; 7+ messages in thread From: Peter Zijlstra @ 2017-12-22 9:20 UTC (permalink / raw) To: tglx, linux-kernel; +Cc: x86, peterz, rui.zhang, len.brown [-- Attachment #1: peterz-uncondition-legacy-timer.patch --] [-- Type: text/plain, Size: 786 bytes --] Even without a PIC/PIT we need the legacy timer interrupt for HPET in legacy replacement mode. Cc: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> --- arch/x86/kernel/time.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) --- a/arch/x86/kernel/time.c +++ b/arch/x86/kernel/time.c @@ -69,9 +69,12 @@ static struct irqaction irq0 = { static void __init setup_default_timer_irq(void) { - if (!nr_legacy_irqs()) - return; - setup_irq(0, &irq0); + /* + * Unconditionally register the legacy timer; even without legacy + * PIC/PIT we need this for the HPET0 in legacy replacement mode. + */ + if (setup_irq(0, &irq0)) + pr_info("Failed to register legacy timer interrupt\n"); } /* Default timer init function */ ^ permalink raw reply [flat|nested] 7+ messages in thread
* [tip:x86/timers] x86/time: Unconditionally register legacy timer interrupt 2017-12-22 9:20 ` [PATCH 2/3] x86/time: Unconditionally register legacy timer interrupt Peter Zijlstra @ 2018-01-14 19:22 ` tip-bot for Peter Zijlstra 0 siblings, 0 replies; 7+ messages in thread From: tip-bot for Peter Zijlstra @ 2018-01-14 19:22 UTC (permalink / raw) To: linux-tip-commits; +Cc: peterz, hpa, mingo, tglx, linux-kernel Commit-ID: 6d671e1b85c63e7a337ba76c1a154c091545cff8 Gitweb: https://git.kernel.org/tip/6d671e1b85c63e7a337ba76c1a154c091545cff8 Author: Peter Zijlstra <peterz@infradead.org> AuthorDate: Fri, 22 Dec 2017 10:20:12 +0100 Committer: Thomas Gleixner <tglx@linutronix.de> CommitDate: Sun, 14 Jan 2018 20:18:23 +0100 x86/time: Unconditionally register legacy timer interrupt Even without a PIC/PIT the legacy timer interrupt is required for HPET in legacy replacement mode. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: len.brown@intel.com Cc: rui.zhang@intel.com Link: https://lkml.kernel.org/r/20171222092243.382623763@infradead.org --- arch/x86/kernel/time.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/time.c b/arch/x86/kernel/time.c index 749d189..774ebaf 100644 --- a/arch/x86/kernel/time.c +++ b/arch/x86/kernel/time.c @@ -69,9 +69,12 @@ static struct irqaction irq0 = { static void __init setup_default_timer_irq(void) { - if (!nr_legacy_irqs()) - return; - setup_irq(0, &irq0); + /* + * Unconditionally register the legacy timer; even without legacy + * PIC/PIT we need this for the HPET0 in legacy replacement mode. + */ + if (setup_irq(0, &irq0)) + pr_info("Failed to register legacy timer interrupt\n"); } /* Default timer init function */ ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] x86/tsc: Introduce early tsc clocksource 2017-12-22 9:20 [PATCH 0/3] x86 time bits Peter Zijlstra 2017-12-22 9:20 ` [PATCH 1/3] x86/tsc: Allow TSC calibration without PIT Peter Zijlstra 2017-12-22 9:20 ` [PATCH 2/3] x86/time: Unconditionally register legacy timer interrupt Peter Zijlstra @ 2017-12-22 9:20 ` Peter Zijlstra 2018-01-14 19:22 ` [tip:x86/timers] " tip-bot for Peter Zijlstra 2 siblings, 1 reply; 7+ messages in thread From: Peter Zijlstra @ 2017-12-22 9:20 UTC (permalink / raw) To: tglx, linux-kernel; +Cc: x86, peterz, rui.zhang, len.brown, Len Brown [-- Attachment #1: peterz-tsc-early.patch --] [-- Type: text/plain, Size: 4051 bytes --] Without TSC_KNOWN_FREQ we register the TSC clocksource so late we first switch to the HPET. Using HPET on large CPU count machines is undesirable. Therefore register a tsc-early clocksource using the preliminary tsc_khz from quick calibration. Then when the final TSC calibration comes in, we can switch to that. The only notably problem is that we must mark the real tsc clocksource with CLOCK_SOURCE_VALID_FOR_HRES, otherwise we will not select it when unregistering tsc-early. And we cannot leave tsc-early registered, because then we'd fall back to it when we mark the tsc clocksource as unstable. Cc: Len Brown <lenb@kernel.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> --- arch/x86/kernel/tsc.c | 43 +++++++++++++++++++++++++++++++++---------- 1 file changed, 33 insertions(+), 10 deletions(-) --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -1005,8 +1005,6 @@ static void __init detect_art(void) /* clocksource code */ -static struct clocksource clocksource_tsc; - static void tsc_resume(struct clocksource *cs) { tsc_verify_tsc_adjust(true); @@ -1057,12 +1055,31 @@ static void tsc_cs_tick_stable(struct cl /* * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc() */ +static struct clocksource clocksource_tsc_early = { + .name = "tsc-early", + .rating = 299, + .read = read_tsc, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS | + CLOCK_SOURCE_MUST_VERIFY, + .archdata = { .vclock_mode = VCLOCK_TSC }, + .resume = tsc_resume, + .mark_unstable = tsc_cs_mark_unstable, + .tick_stable = tsc_cs_tick_stable, +}; + +/* + * Must mark VALID_FOR_HRES early such that when we unregister tsc_early + * this one will immediately take over. We will only register if TSC has + * been found good. + */ static struct clocksource clocksource_tsc = { .name = "tsc", .rating = 300, .read = read_tsc, .mask = CLOCKSOURCE_MASK(64), .flags = CLOCK_SOURCE_IS_CONTINUOUS | + CLOCK_SOURCE_VALID_FOR_HRES | CLOCK_SOURCE_MUST_VERIFY, .archdata = { .vclock_mode = VCLOCK_TSC }, .resume = tsc_resume, @@ -1186,8 +1203,8 @@ static void tsc_refine_calibration_work( int cpu; /* Don't bother refining TSC on unstable systems */ - if (check_tsc_unstable()) - goto out; + if (tsc_unstable) + return; /* * Since the work is started early in boot, we may be @@ -1239,9 +1256,13 @@ static void tsc_refine_calibration_work( set_cyc2ns_scale(tsc_khz, cpu, tsc_stop); out: + if (tsc_unstable) + return; + if (boot_cpu_has(X86_FEATURE_ART)) art_related_clocksource = &clocksource_tsc; clocksource_register_khz(&clocksource_tsc, tsc_khz); + clocksource_unregister(&clocksource_tsc_early); } @@ -1250,13 +1271,11 @@ static int __init init_tsc_clocksource(v if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_disabled > 0 || !tsc_khz) return 0; + if (check_tsc_unstable()) + return 0; + if (tsc_clocksource_reliable) clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; - /* lower the rating if we already know its unstable: */ - if (check_tsc_unstable()) { - clocksource_tsc.rating = 0; - clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS; - } if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3)) clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; @@ -1269,6 +1288,7 @@ static int __init init_tsc_clocksource(v if (boot_cpu_has(X86_FEATURE_ART)) art_related_clocksource = &clocksource_tsc; clocksource_register_khz(&clocksource_tsc, tsc_khz); + clocksource_unregister(&clocksource_tsc_early); return 0; } @@ -1367,9 +1387,12 @@ void __init tsc_init(void) check_system_tsc_reliable(); - if (unsynchronized_tsc()) + if (unsynchronized_tsc()) { mark_tsc_unstable("TSCs unsynchronized"); + return; + } + clocksource_register_khz(&clocksource_tsc_early, tsc_khz); detect_art(); } ^ permalink raw reply [flat|nested] 7+ messages in thread
* [tip:x86/timers] x86/tsc: Introduce early tsc clocksource 2017-12-22 9:20 ` [PATCH 3/3] x86/tsc: Introduce early tsc clocksource Peter Zijlstra @ 2018-01-14 19:22 ` tip-bot for Peter Zijlstra 0 siblings, 0 replies; 7+ messages in thread From: tip-bot for Peter Zijlstra @ 2018-01-14 19:22 UTC (permalink / raw) To: linux-tip-commits; +Cc: peterz, mingo, hpa, linux-kernel, tglx, lenb Commit-ID: aa83c45762a242acce9b35020363225a7b59d7c9 Gitweb: https://git.kernel.org/tip/aa83c45762a242acce9b35020363225a7b59d7c9 Author: Peter Zijlstra <peterz@infradead.org> AuthorDate: Fri, 22 Dec 2017 10:20:13 +0100 Committer: Thomas Gleixner <tglx@linutronix.de> CommitDate: Sun, 14 Jan 2018 20:18:23 +0100 x86/tsc: Introduce early tsc clocksource Without TSC_KNOWN_FREQ the TSC clocksource is registered so late that the kernel first switches to the HPET. Using HPET on large CPU count machines is undesirable. Therefore register a tsc-early clocksource using the preliminary tsc_khz from quick calibration. Then when the final TSC calibration is done, it can switch to the tuned frequency. The only notably problem is that the real tsc clocksource must be marked with CLOCK_SOURCE_VALID_FOR_HRES, otherwise it will not be selected when unregistering tsc-early. tsc-early cannot be left registered, because then the clocksource code would fall back to it when we tsc clocksource is marked unstable later. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: len.brown@intel.com Cc: rui.zhang@intel.com Cc: Len Brown <lenb@kernel.org> Link: https://lkml.kernel.org/r/20171222092243.431585460@infradead.org --- arch/x86/kernel/tsc.c | 43 +++++++++++++++++++++++++++++++++---------- 1 file changed, 33 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index a2c9dd8..fb43027 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -1006,8 +1006,6 @@ static void __init detect_art(void) /* clocksource code */ -static struct clocksource clocksource_tsc; - static void tsc_resume(struct clocksource *cs) { tsc_verify_tsc_adjust(true); @@ -1058,12 +1056,31 @@ static void tsc_cs_tick_stable(struct clocksource *cs) /* * .mask MUST be CLOCKSOURCE_MASK(64). See comment above read_tsc() */ +static struct clocksource clocksource_tsc_early = { + .name = "tsc-early", + .rating = 299, + .read = read_tsc, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS | + CLOCK_SOURCE_MUST_VERIFY, + .archdata = { .vclock_mode = VCLOCK_TSC }, + .resume = tsc_resume, + .mark_unstable = tsc_cs_mark_unstable, + .tick_stable = tsc_cs_tick_stable, +}; + +/* + * Must mark VALID_FOR_HRES early such that when we unregister tsc_early + * this one will immediately take over. We will only register if TSC has + * been found good. + */ static struct clocksource clocksource_tsc = { .name = "tsc", .rating = 300, .read = read_tsc, .mask = CLOCKSOURCE_MASK(64), .flags = CLOCK_SOURCE_IS_CONTINUOUS | + CLOCK_SOURCE_VALID_FOR_HRES | CLOCK_SOURCE_MUST_VERIFY, .archdata = { .vclock_mode = VCLOCK_TSC }, .resume = tsc_resume, @@ -1187,8 +1204,8 @@ static void tsc_refine_calibration_work(struct work_struct *work) int cpu; /* Don't bother refining TSC on unstable systems */ - if (check_tsc_unstable()) - goto out; + if (tsc_unstable) + return; /* * Since the work is started early in boot, we may be @@ -1240,9 +1257,13 @@ static void tsc_refine_calibration_work(struct work_struct *work) set_cyc2ns_scale(tsc_khz, cpu, tsc_stop); out: + if (tsc_unstable) + return; + if (boot_cpu_has(X86_FEATURE_ART)) art_related_clocksource = &clocksource_tsc; clocksource_register_khz(&clocksource_tsc, tsc_khz); + clocksource_unregister(&clocksource_tsc_early); } @@ -1251,13 +1272,11 @@ static int __init init_tsc_clocksource(void) if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_disabled > 0 || !tsc_khz) return 0; + if (check_tsc_unstable()) + return 0; + if (tsc_clocksource_reliable) clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; - /* lower the rating if we already know its unstable: */ - if (check_tsc_unstable()) { - clocksource_tsc.rating = 0; - clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS; - } if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3)) clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP; @@ -1270,6 +1289,7 @@ static int __init init_tsc_clocksource(void) if (boot_cpu_has(X86_FEATURE_ART)) art_related_clocksource = &clocksource_tsc; clocksource_register_khz(&clocksource_tsc, tsc_khz); + clocksource_unregister(&clocksource_tsc_early); return 0; } @@ -1374,9 +1394,12 @@ void __init tsc_init(void) check_system_tsc_reliable(); - if (unsynchronized_tsc()) + if (unsynchronized_tsc()) { mark_tsc_unstable("TSCs unsynchronized"); + return; + } + clocksource_register_khz(&clocksource_tsc_early, tsc_khz); detect_art(); } ^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-01-14 19:25 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2017-12-22 9:20 [PATCH 0/3] x86 time bits Peter Zijlstra 2017-12-22 9:20 ` [PATCH 1/3] x86/tsc: Allow TSC calibration without PIT Peter Zijlstra 2018-01-14 19:21 ` [tip:x86/timers] " tip-bot for Peter Zijlstra 2017-12-22 9:20 ` [PATCH 2/3] x86/time: Unconditionally register legacy timer interrupt Peter Zijlstra 2018-01-14 19:22 ` [tip:x86/timers] " tip-bot for Peter Zijlstra 2017-12-22 9:20 ` [PATCH 3/3] x86/tsc: Introduce early tsc clocksource Peter Zijlstra 2018-01-14 19:22 ` [tip:x86/timers] " tip-bot for Peter Zijlstra
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.