From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34411) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eWnt7-000409-O5 for qemu-devel@nongnu.org; Wed, 03 Jan 2018 13:35:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eWnt5-00083u-B6 for qemu-devel@nongnu.org; Wed, 03 Jan 2018 13:35:41 -0500 Received: from mail-qk0-x242.google.com ([2607:f8b0:400d:c09::242]:39996) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eWnt5-00083V-6k for qemu-devel@nongnu.org; Wed, 03 Jan 2018 13:35:39 -0500 Received: by mail-qk0-x242.google.com with SMTP id q14so2663341qke.7 for ; Wed, 03 Jan 2018 10:35:39 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 3 Jan 2018 15:34:18 -0300 Message-Id: <20180103183418.23730-26-f4bug@amsat.org> In-Reply-To: <20180103183418.23730-1-f4bug@amsat.org> References: <20180103183418.23730-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v4 25/25] sdhci: add Spec v4.2 register definitions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alistair Francis , "Edgar E . Iglesias" , Peter Maydell , Andrey Smirnov Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org, Peter Crosthwaite Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sdhci-internal.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index 1da91a27b4..8193aa1821 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -191,6 +191,10 @@ FIELD(SDHC_HOSTCTL2, V18_ENA, 3, 1); /* UHS-I only */ FIELD(SDHC_HOSTCTL2, DRIVER_STRENGTH, 4, 2); /* UHS-I only */ FIELD(SDHC_HOSTCTL2, EXECUTE_TUNING, 6, 1); /* UHS-I only */ FIELD(SDHC_HOSTCTL2, SAMPLING_CLKSEL, 7, 1); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, UHS_II_ENA, 8, 1); /* since v4 */ +FIELD(SDHC_HOSTCTL2, ADMA2_LENGTH, 10, 1); /* since v4 */ +FIELD(SDHC_HOSTCTL2, CMD23_ENA, 11, 1); /* since v4 */ +FIELD(SDHC_HOSTCTL2, VERSION4, 12, 1); /* since v4 */ FIELD(SDHC_HOSTCTL2, ASYNC_INT, 14, 1); FIELD(SDHC_HOSTCTL2, PRESET_ENA, 15, 1); @@ -219,12 +223,16 @@ FIELD(SDHC_CAPAB, DRIVER_TYPE_C, 37, 1); /* since v3 */ FIELD(SDHC_CAPAB, DRIVER_TYPE_D, 38, 1); /* since v3 */ FIELD(SDHC_CAPAB, TIMER_RETUNNING, 40, 4); /* since v3 */ FIELD(SDHC_CAPAB, SDR50_TUNNING, 45, 1); /* since v3 */ +FIELD(SDHC_CAPAB, CLK_MUL, 48, 8); /* since v4.20 */ +FIELD(SDHC_CAPAB, ADMA3, 59, 1); /* since v4.20 */ +FIELD(SDHC_CAPAB, V18_VDD2, 60, 1); /* since v4.20 */ /* HWInit Maximum Current Capabilities Register 0x0 */ #define SDHC_MAXCURR 0x48 FIELD(SDHC_MAXCURR, V33_VDD1, 0, 8); FIELD(SDHC_MAXCURR, V30_VDD1, 8, 8); FIELD(SDHC_MAXCURR, V18_VDD1, 16, 8); +FIELD(SDHC_MAXCURR, V18_VDD2, 32, 8); /* since v4.20 */ /* W Force Event Auto CMD12 Error Interrupt Register 0x0000 */ #define SDHC_FEAER 0x50 -- 2.15.1