[PATCH 3/6] net/mlx5: add SWP PCI parameter for TX common tunnel offloads

From: Xueming Li <xuemingl@mellanox.com>
To: Olivier MATZ <olivier.matz@6wind.com>,
	Thomas Monjalon <thomas@monjalon.net>,
	Jingjing Wu <jingjing.wu@intel.com>,
	Yongseok Koh <yskoh@mellanox.com>
Cc: Xueming Li <xuemingl@mellanox.com>,
	Shahaf Shuler <shahafs@mellanox.com>,
	dev@dpdk.org
Subject: [PATCH 3/6] net/mlx5: add SWP PCI parameter for TX common tunnel offloads
Date: Tue,  9 Jan 2018 22:11:07 +0800	[thread overview]
Message-ID: <20180109141110.146250-4-xuemingl@mellanox.com> (raw)
In-Reply-To: <20180109141110.146250-1-xuemingl@mellanox.com>

Add PCI parameter 'swp' to control TX SWP feature, enabled by default.

Signed-off-by: Xueming Li <xuemingl@mellanox.com>
---
 drivers/net/mlx5/mlx5.c     | 7 +++++++
 drivers/net/mlx5/mlx5.h     | 1 +
 drivers/net/mlx5/mlx5_txq.c | 2 +-
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 1c95f3520..c124465fd 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -91,6 +91,9 @@
 /* Device parameter to enable hardware Rx vector. */
 #define MLX5_RX_VEC_EN "rx_vec_en"
 
+/* Device parameter to enable TX SW parser. */
+#define MLX5_TX_SWP "swp"
+
 #ifndef HAVE_IBV_MLX5_MOD_MPW
 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
@@ -407,6 +410,8 @@ mlx5_args_check(const char *key, const char *val, void *opaque)
 		config->tx_vec_en = !!tmp;
 	} else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
 		config->rx_vec_en = !!tmp;
+	} else if (strcmp(MLX5_TX_SWP, key) == 0) {
+		config->swp = !!tmp;
 	} else {
 		WARN("%s: unknown parameter", key);
 		return -EINVAL;
@@ -437,6 +442,7 @@ mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
 		MLX5_TXQ_MAX_INLINE_LEN,
 		MLX5_TX_VEC_EN,
 		MLX5_RX_VEC_EN,
+		MLX5_TX_SWP,
 		NULL,
 	};
 	struct rte_kvargs *kvlist;
@@ -629,6 +635,7 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
 			.txq_inline = MLX5_ARG_UNSET,
 			.txqs_inline = MLX5_ARG_UNSET,
 			.inline_max_packet_sz = MLX5_ARG_UNSET,
+			.swp = 1,
 		};
 
 		mlx5_dev[idx].ports |= test;
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 8ee522069..4d5d12326 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -116,6 +116,7 @@ struct mlx5_dev_config {
 	unsigned int tx_vec_en:1; /* Tx vector is enabled. */
 	unsigned int rx_vec_en:1; /* Rx vector is enabled. */
 	unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
+	unsigned int swp:1; /* TX common tunnel csum and tso offloads. */
 	unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
 	unsigned int ind_table_max_size; /* Maximum indirection table size. */
 	int txq_inline; /* Maximum packet size for inlining. */
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index bd7ba0834..0e8498161 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -729,7 +729,7 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
 		txq_ctrl->txq.tso_en = 1;
 	}
 	txq_ctrl->txq.tunnel_en = config->tunnel_en;
-	txq_ctrl->txq.swp_en = 1;
+	txq_ctrl->txq.swp_en = config->swp;
 }
 
 /**
-- 
2.13.3
