[PATCH 19/27] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection

[Paulo Zanoni <paulo.r.zanoni@intel.com>]

From: Kelvin Gardiner <kelvin.gardiner@intel.com>

This patch adds support to detect ICL, slice, subslice and EU fuse
settings.

Add addresses for ICL 11 slice, subslice and EU fuses registers.
These register addresses are the same as previous platforms but the
format and / or the meaning of the information is different. Therefore
Gen11 defines for these registers are added.

Bspec: 9731
Bspec: 20643
Bspec: 20673

Signed-off-by: Kelvin Gardiner <kelvin.gardiner@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          |  9 +++++++++
 drivers/gpu/drm/i915/intel_device_info.c | 25 ++++++++++++++++++++++++-
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c9b62502ce69..d8b537570b8e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2809,6 +2809,15 @@ enum i915_power_well_id {
 #define GEN11_GT_VEBOX_DISABLE_SHIFT	16
 #define GEN11_GT_VEBOX_DISABLE_MASK	(0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
 
+#define GEN11_EU_DISABLE _MMIO(0x9134)
+#define GEN11_EU_DIS_MASK 0xFF
+
+#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
+#define GEN11_GT_S_ENA_MASK 0xFF
+
+#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
+#define GEN11_GT_SS_DIS_MASK 0xFF
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 3316470363a0..895c41ef4abf 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -120,6 +120,27 @@ void intel_device_info_dump(const struct intel_device_info *info,
 	intel_device_info_dump_flags(info, p);
 }
 
+static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+	int eu_max = 8;
+	u32 eu_disable;
+
+	sseu->slice_mask = I915_READ(GEN11_GT_SLICE_ENABLE) &
+				GEN11_GT_S_ENA_MASK;
+	sseu->subslice_mask = ~(I915_READ(GEN11_GT_SUBSLICE_DISABLE) &
+				GEN11_GT_SS_DIS_MASK);
+	eu_disable = I915_READ(GEN11_EU_DISABLE) & GEN11_GT_S_ENA_MASK;
+
+	sseu->eu_per_subslice = eu_max - hweight32(eu_disable);
+	sseu->eu_total = sseu->eu_per_subslice * hweight32(sseu->subslice_mask);
+
+	/* ICL has no power gating restrictions. */
+	sseu->has_slice_pg = 1;
+	sseu->has_subslice_pg = 1;
+	sseu->has_eu_pg = 1;
+}
+
 static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
 {
 	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
@@ -583,8 +604,10 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 		broadwell_sseu_info_init(dev_priv);
 	else if (INTEL_GEN(dev_priv) == 9)
 		gen9_sseu_info_init(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 10)
+	else if (INTEL_GEN(dev_priv) == 10)
 		gen10_sseu_info_init(dev_priv);
+	else if (INTEL_INFO(dev_priv)->gen >= 11)
+		gen11_sseu_info_init(dev_priv);
 
 	/* Initialize command stream timestamp frequency */
 	info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
-- 
2.14.3

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