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From: Paulo Zanoni <paulo.r.zanoni@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [PATCH 2/8] drm/i915/icl: Add initial Icelake definitions.
Date: Thu, 11 Jan 2018 16:00:04 -0200	[thread overview]
Message-ID: <20180111180010.24357-3-paulo.r.zanoni@intel.com> (raw)
In-Reply-To: <20180111180010.24357-1-paulo.r.zanoni@intel.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>

Icelake is an Intel® Processor containing an Intel® Graphics
Controller.

This is just an initial Icelake definition. PCI IDs, Icelake support
and new features coming in following patches.

v2: Add .ddb_size and .has_guc (Michal Wajdeczko).
v3: Add the ICL_FEATURES macro (Kelvin Gardiner).
v4 (from Paulo): Add missing __initconst (Paulo) and say "graphics
controller" instead of something that looks like an official marketing
name but isn't (Chris).

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          |  2 ++
 drivers/gpu/drm/i915/i915_pci.c          | 13 +++++++++++++
 drivers/gpu/drm/i915/intel_device_info.c |  1 +
 drivers/gpu/drm/i915/intel_device_info.h |  2 ++
 4 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a689396d0ff6..016920f58ae6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2595,6 +2595,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
 #define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
 #define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
+#define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
 #define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
 				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
@@ -2706,6 +2707,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
 #define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
 #define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
+#define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))
 
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 36d48422b475..f28c165fc49d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -579,6 +579,19 @@ static const struct intel_device_info intel_cannonlake_gt2_info __initconst = {
 	.gt = 2,
 };
 
+#define GEN11_FEATURES \
+	GEN10_FEATURES, \
+	.gen = 11, \
+	.ddb_size = 2048, \
+	.has_csr = 0
+
+static const struct intel_device_info intel_icelake_11_info __initconst = {
+	GEN11_FEATURES,
+	.platform = INTEL_ICELAKE,
+	.is_alpha_support = 1,
+	.has_resource_streamer = 0,
+};
+
 /*
  * Make sure any device matches here are from most specific to most
  * general.  For example, since the Quanta match is based on the subsystem
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index d28592e43512..a2c16140169f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -56,6 +56,7 @@ static const char * const platform_names[] = {
 	PLATFORM_NAME(GEMINILAKE),
 	PLATFORM_NAME(COFFEELAKE),
 	PLATFORM_NAME(CANNONLAKE),
+	PLATFORM_NAME(ICELAKE),
 };
 #undef PLATFORM_NAME
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 49cb27bd04c1..9542018d11d0 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -69,6 +69,8 @@ enum intel_platform {
 	INTEL_COFFEELAKE,
 	/* gen10 */
 	INTEL_CANNONLAKE,
+	/* gen11 */
+	INTEL_ICELAKE,
 	INTEL_MAX_PLATFORMS
 };
 
-- 
2.14.3

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  parent reply	other threads:[~2018-01-11 18:00 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-11 18:00 [PATCH 0/8] ICP initial support Paulo Zanoni
2018-01-11 18:00 ` [PATCH 1/8] drm/i915/cnl: Add Port F definition Paulo Zanoni
2018-01-11 19:37   ` Rodrigo Vivi
2018-01-11 18:00 ` Paulo Zanoni [this message]
2018-01-11 18:00 ` [PATCH 3/8] drm/i915/icp: Introduce Ice Lake PCH Paulo Zanoni
2018-01-11 18:00 ` [PATCH 4/8] drm/i915/icp: Get/set proper Raw clock frequency on ICP Paulo Zanoni
2018-01-11 18:00 ` [PATCH 5/8] drm/i915/icp: Add Panel Power Sequencing Support Paulo Zanoni
2018-01-11 18:00 ` [PATCH 6/8] drm/i915/icp: Add backlight Support for ICP Paulo Zanoni
2018-01-11 21:48   ` James Ausmus
2018-01-11 23:57     ` Rodrigo Vivi
2018-01-19 16:40       ` Paulo Zanoni
2018-01-19 17:26         ` Anusha Srivatsa
2018-01-19 17:56           ` Rodrigo Vivi
2018-01-19 18:25             ` Paulo Zanoni
2018-01-19 18:45               ` Srivatsa, Anusha
2018-01-19 18:14           ` James Ausmus
2018-01-19 18:48   ` Paulo Zanoni
2018-01-19 19:45     ` Ausmus, James
2018-01-19 19:56     ` Rodrigo Vivi
2018-01-11 18:00 ` [PATCH 7/8] drm/i915/icp: add ICP gmbus and gpio support Paulo Zanoni
2018-01-11 18:00 ` [PATCH 8/8] drm/i915/icp: Add the ID for ICL PCH - ICP Paulo Zanoni
2018-01-11 18:25 ` ✓ Fi.CI.BAT: success for ICP initial support Patchwork
2018-01-11 19:17 ` ✓ Fi.CI.IGT: " Patchwork
2018-01-19 19:48 ` ✓ Fi.CI.BAT: success for ICP initial support (rev2) Patchwork
2018-01-19 20:20 ` [PATCH 0/8] ICP initial support Paulo Zanoni
2018-01-20  3:33 ` ✓ Fi.CI.IGT: success for ICP initial support (rev2) Patchwork

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