From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753062AbeAQNUf (ORCPT + 1 other); Wed, 17 Jan 2018 08:20:35 -0500 Received: from foss.arm.com ([217.140.101.70]:40354 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750888AbeAQNUe (ORCPT ); Wed, 17 Jan 2018 08:20:34 -0500 Date: Fri, 12 Jan 2018 17:06:36 +0000 From: Liviu Dudau To: Ayan Halder Cc: brian.starkey@arm.com, malidp@foss.arm.com, airlied@linux.ie, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, nd@arm.com Subject: Re: [PATCH] drm/arm/malidp: Disable pixel alpha blending for colors that do not have alpha Message-ID: <20180112170636.GE11192@e110455-lin.cambridge.arm.com> References: <1515774787-19324-1-git-send-email-ayan.halder@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1515774787-19324-1-git-send-email-ayan.halder@arm.com> User-Agent: Mutt/1.9.2 (2017-12-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return-Path: Hi Ayan, On Fri, Jan 12, 2018 at 04:33:07PM +0000, Ayan Halder wrote: > Mali dp needs to disable pixel alpha blending (use layer alpha blending) to > display color formats that do not contain alpha bits per pixel In the future, please mention any dependencies on other patches that are not part of a series. In this case one needs your other patch, "drm: add drm_format_alpha_bits". Anyway, looks good to me. Signed-off-by: Liviu Dudau Many thanks, Liviu > > Signed-off-by: Ayan Kumar Halder > --- > drivers/gpu/drm/arm/malidp_planes.c | 27 ++++++++++++++++++++++----- > 1 file changed, 22 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c > index e741979..4d7d564 100644 > --- a/drivers/gpu/drm/arm/malidp_planes.c > +++ b/drivers/gpu/drm/arm/malidp_planes.c > @@ -35,6 +35,9 @@ > #define LAYER_COMP_MASK (0x3 << 12) > #define LAYER_COMP_PIXEL (0x3 << 12) > #define LAYER_COMP_PLANE (0x2 << 12) > +#define LAYER_ALPHA_OFFSET (16) > +#define LAYER_ALPHA_MASK (0xff) > +#define LAYER_ALPHA(x) (((x) & LAYER_ALPHA_MASK) << LAYER_ALPHA_OFFSET) > #define MALIDP_LAYER_COMPOSE 0x008 > #define MALIDP_LAYER_SIZE 0x00c > #define LAYER_H_VAL(x) (((x) & 0x1fff) << 0) > @@ -268,6 +271,7 @@ static void malidp_de_plane_update(struct drm_plane *plane, > struct malidp_plane_state *ms = to_malidp_plane_state(plane->state); > u32 src_w, src_h, dest_w, dest_h, val; > int i; > + u8 alpha_bits = plane->state->fb->format->alpha; > > mp = to_malidp_plane(plane); > > @@ -319,12 +323,25 @@ static void malidp_de_plane_update(struct drm_plane *plane, > if (plane->state->rotation & DRM_MODE_REFLECT_Y) > val |= LAYER_V_FLIP; > > - /* > - * always enable pixel alpha blending until we have a way to change > - * blend modes > - */ > val &= ~LAYER_COMP_MASK; > - val |= LAYER_COMP_PIXEL; > + if (alpha_bits > 0) { > + > + /* > + * always enable pixel alpha blending until we have a way to change > + * blend modes > + */ > + val |= LAYER_COMP_PIXEL; > + } else { > + > + /* > + * do not enable pixel alpha blending as the color channel does not > + * have any alpha information > + */ > + val |= LAYER_COMP_PLANE; > + > + /* Set layer alpha coefficient to 0xff ie fully opaque */ > + val |= LAYER_ALPHA(0xff); > + } > > val &= ~LAYER_FLOWCFG(LAYER_FLOWCFG_MASK); > if (plane->state->crtc) { > -- > 2.7.4 > -- ==================== | I would like to | | fix the world, | | but they're not | | giving me the | \ source code! / --------------- ¯\_(ツ)_/¯ From mboxrd@z Thu Jan 1 00:00:00 1970 From: Liviu Dudau Subject: Re: [PATCH] drm/arm/malidp: Disable pixel alpha blending for colors that do not have alpha Date: Fri, 12 Jan 2018 17:06:36 +0000 Message-ID: <20180112170636.GE11192@e110455-lin.cambridge.arm.com> References: <1515774787-19324-1-git-send-email-ayan.halder@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by gabe.freedesktop.org (Postfix) with ESMTP id 2513C6E43A for ; Wed, 17 Jan 2018 13:20:33 +0000 (UTC) Content-Disposition: inline In-Reply-To: <1515774787-19324-1-git-send-email-ayan.halder@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Ayan Halder Cc: airlied@linux.ie, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, malidp@foss.arm.com, nd@arm.com List-Id: dri-devel@lists.freedesktop.org SGkgQXlhbiwKCk9uIEZyaSwgSmFuIDEyLCAyMDE4IGF0IDA0OjMzOjA3UE0gKzAwMDAsIEF5YW4g SGFsZGVyIHdyb3RlOgo+IE1hbGkgZHAgbmVlZHMgdG8gZGlzYWJsZSBwaXhlbCBhbHBoYSBibGVu ZGluZyAodXNlIGxheWVyIGFscGhhIGJsZW5kaW5nKSB0bwo+IGRpc3BsYXkgY29sb3IgZm9ybWF0 cyB0aGF0IGRvIG5vdCBjb250YWluIGFscGhhIGJpdHMgcGVyIHBpeGVsCgpJbiB0aGUgZnV0dXJl LCBwbGVhc2UgbWVudGlvbiBhbnkgZGVwZW5kZW5jaWVzIG9uIG90aGVyIHBhdGNoZXMgdGhhdCBh cmUKbm90IHBhcnQgb2YgYSBzZXJpZXMuIEluIHRoaXMgY2FzZSBvbmUgbmVlZHMgeW91ciBvdGhl ciBwYXRjaCwgImRybTogYWRkCmRybV9mb3JtYXRfYWxwaGFfYml0cyIuCgpBbnl3YXksIGxvb2tz IGdvb2QgdG8gbWUuCgpTaWduZWQtb2ZmLWJ5OiBMaXZpdSBEdWRhdSA8bGl2aXUuZHVkYXVAYXJt LmNvbT4KCk1hbnkgdGhhbmtzLApMaXZpdQoKPiAKPiBTaWduZWQtb2ZmLWJ5OiBBeWFuIEt1bWFy IEhhbGRlciA8YXlhbi5oYWxkZXJAYXJtLmNvbT4KPiAtLS0KPiAgZHJpdmVycy9ncHUvZHJtL2Fy bS9tYWxpZHBfcGxhbmVzLmMgfCAyNyArKysrKysrKysrKysrKysrKysrKysrLS0tLS0KPiAgMSBm aWxlIGNoYW5nZWQsIDIyIGluc2VydGlvbnMoKyksIDUgZGVsZXRpb25zKC0pCj4gCj4gZGlmZiAt LWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9hcm0vbWFsaWRwX3BsYW5lcy5jIGIvZHJpdmVycy9ncHUv ZHJtL2FybS9tYWxpZHBfcGxhbmVzLmMKPiBpbmRleCBlNzQxOTc5Li40ZDdkNTY0IDEwMDY0NAo+ IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9hcm0vbWFsaWRwX3BsYW5lcy5jCj4gKysrIGIvZHJpdmVy cy9ncHUvZHJtL2FybS9tYWxpZHBfcGxhbmVzLmMKPiBAQCAtMzUsNiArMzUsOSBAQAo+ICAjZGVm aW5lICAgTEFZRVJfQ09NUF9NQVNLCQkoMHgzIDw8IDEyKQo+ICAjZGVmaW5lICAgTEFZRVJfQ09N UF9QSVhFTAkJKDB4MyA8PCAxMikKPiAgI2RlZmluZSAgIExBWUVSX0NPTVBfUExBTkUJCSgweDIg PDwgMTIpCj4gKyNkZWZpbmUgICBMQVlFUl9BTFBIQV9PRkZTRVQJKDE2KQo+ICsjZGVmaW5lICAg TEFZRVJfQUxQSEFfTUFTSwkJKDB4ZmYpCj4gKyNkZWZpbmUJICBMQVlFUl9BTFBIQSh4KQkJKCgo eCkgJiBMQVlFUl9BTFBIQV9NQVNLKSA8PCBMQVlFUl9BTFBIQV9PRkZTRVQpCj4gICNkZWZpbmUg TUFMSURQX0xBWUVSX0NPTVBPU0UJCTB4MDA4Cj4gICNkZWZpbmUgTUFMSURQX0xBWUVSX1NJWkUJ CTB4MDBjCj4gICNkZWZpbmUgICBMQVlFUl9IX1ZBTCh4KQkJKCgoeCkgJiAweDFmZmYpIDw8IDAp Cj4gQEAgLTI2OCw2ICsyNzEsNyBAQCBzdGF0aWMgdm9pZCBtYWxpZHBfZGVfcGxhbmVfdXBkYXRl KHN0cnVjdCBkcm1fcGxhbmUgKnBsYW5lLAo+ICAJc3RydWN0IG1hbGlkcF9wbGFuZV9zdGF0ZSAq bXMgPSB0b19tYWxpZHBfcGxhbmVfc3RhdGUocGxhbmUtPnN0YXRlKTsKPiAgCXUzMiBzcmNfdywg c3JjX2gsIGRlc3RfdywgZGVzdF9oLCB2YWw7Cj4gIAlpbnQgaTsKPiArCXU4IGFscGhhX2JpdHMg PSBwbGFuZS0+c3RhdGUtPmZiLT5mb3JtYXQtPmFscGhhOwo+ICAKPiAgCW1wID0gdG9fbWFsaWRw X3BsYW5lKHBsYW5lKTsKPiAgCj4gQEAgLTMxOSwxMiArMzIzLDI1IEBAIHN0YXRpYyB2b2lkIG1h bGlkcF9kZV9wbGFuZV91cGRhdGUoc3RydWN0IGRybV9wbGFuZSAqcGxhbmUsCj4gIAlpZiAocGxh bmUtPnN0YXRlLT5yb3RhdGlvbiAmIERSTV9NT0RFX1JFRkxFQ1RfWSkKPiAgCQl2YWwgfD0gTEFZ RVJfVl9GTElQOwo+ICAKPiAtCS8qCj4gLQkgKiBhbHdheXMgZW5hYmxlIHBpeGVsIGFscGhhIGJs ZW5kaW5nIHVudGlsIHdlIGhhdmUgYSB3YXkgdG8gY2hhbmdlCj4gLQkgKiBibGVuZCBtb2Rlcwo+ IC0JICovCj4gIAl2YWwgJj0gfkxBWUVSX0NPTVBfTUFTSzsKPiAtCXZhbCB8PSBMQVlFUl9DT01Q X1BJWEVMOwo+ICsJaWYgKGFscGhhX2JpdHMgPiAwKSB7Cj4gKwo+ICsJCS8qCj4gKwkJICogYWx3 YXlzIGVuYWJsZSBwaXhlbCBhbHBoYSBibGVuZGluZyB1bnRpbCB3ZSBoYXZlIGEgd2F5IHRvIGNo YW5nZQo+ICsJCSAqIGJsZW5kIG1vZGVzCj4gKwkJICovCj4gKwkJdmFsIHw9IExBWUVSX0NPTVBf UElYRUw7Cj4gKwl9IGVsc2Ugewo+ICsKPiArCQkvKgo+ICsJCSAqIGRvIG5vdCBlbmFibGUgcGl4 ZWwgYWxwaGEgYmxlbmRpbmcgYXMgdGhlIGNvbG9yIGNoYW5uZWwgZG9lcyBub3QKPiArCQkgKiBo YXZlIGFueSBhbHBoYSBpbmZvcm1hdGlvbgo+ICsJCSAqLwo+ICsJCXZhbCB8PSBMQVlFUl9DT01Q X1BMQU5FOwo+ICsKPiArCQkvKiBTZXQgbGF5ZXIgYWxwaGEgY29lZmZpY2llbnQgdG8gMHhmZiBp ZSBmdWxseSBvcGFxdWUgKi8KPiArCQl2YWwgfD0gTEFZRVJfQUxQSEEoMHhmZik7Cj4gKwl9Cj4g IAo+ICAJdmFsICY9IH5MQVlFUl9GTE9XQ0ZHKExBWUVSX0ZMT1dDRkdfTUFTSyk7Cj4gIAlpZiAo cGxhbmUtPnN0YXRlLT5jcnRjKSB7Cj4gLS0gCj4gMi43LjQKPiAKCi0tIAo9PT09PT09PT09PT09 PT09PT09PQp8IEkgd291bGQgbGlrZSB0byB8CnwgZml4IHRoZSB3b3JsZCwgIHwKfCBidXQgdGhl eSdyZSBub3QgfAp8IGdpdmluZyBtZSB0aGUgICB8CiBcIHNvdXJjZSBjb2RlISAgLwogIC0tLS0t LS0tLS0tLS0tLQogICAgwq9cXyjjg4QpXy/CrwpfX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0 cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9s aXN0aW5mby9kcmktZGV2ZWwK