From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: ACJfBov3SV4j1dukiZDMtQ8OWTBoL0WSd72HdgJBRfS7iinyvwdmYPUz47jBw/Ca5XkdeVBadFe3 ARC-Seal: i=1; a=rsa-sha256; t=1516299877; cv=none; d=google.com; s=arc-20160816; b=dlIye5diutWoGWEDn/hBQal5kHGNFT10sPxUjtikxH0mE5LhaIn2LdUk2ArcEXbldV gcpiPD5/qgcFsLx1KwxroGCdvTCT+HE/GknAVM+hY3QJgOShoz8G2Rn8gnzZWOsu1FHU S0nZ2jyyf6tR2lc1KmgRS/s+fLRFHO+jBmvqdBK4Bo6GwQmd1tzbelfMyx0y2lgmTTFo 0fIeZEvMc1wOFvRQnyPzNcL7T9xLwS6oQ1op/KBPinAL8XvvJ6rg+mbYgDfROrtBrWwz 48QDGuKNZjm5U3gqiPBR9o+4qPqAzGeFpQT7MORgA4Jz5YrTkxC8YIa1DoLkr05hPvHE QS6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=user-agent:in-reply-to:content-disposition:mime-version:references :message-id:subject:cc:to:from:date:arc-authentication-results; bh=XDZZ80DWLJjlbWmNoa+Mi1guqgIJ/3BxTYPcfZAxiXQ=; b=DmFl3EBoJBxkDtqxaU1nWCCSqNaDfdmPxQsuj38rO5UctgX+d1BFXYypWDX67hj9c9 to8eaI7zfCeAvkpUJv2h+GRrxSWpJNnraelnKp+wnDL891/XAfVT9clB91rIRR8Anw+p 9l3eFptMBY3h/wrEN+M77Kvf2fs07SMpDRYU0PFtJQqDD4UORGAUm2JJ8IAT/7oo1BW7 EAEId/EDQyclAogRzyOsMzGQ5Dp1K2zN5E6ml4RhqRzmmyUBTukKRBSQ8y/qJo9vOdP7 ppaOjWgCRtPwDMrC9ctKMgV+ZiECshT10QAXUzCvD5ejQ98BlfHBtLAvspcRl2FC85mX e34Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of jpoimboe@redhat.com designates 209.132.183.28 as permitted sender) smtp.mailfrom=jpoimboe@redhat.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Authentication-Results: mx.google.com; spf=pass (google.com: domain of jpoimboe@redhat.com designates 209.132.183.28 as permitted sender) smtp.mailfrom=jpoimboe@redhat.com; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Date: Thu, 18 Jan 2018 12:24:31 -0600 From: Josh Poimboeuf To: Paolo Bonzini Cc: Dave Hansen , Peter Zijlstra , David Woodhouse , Thomas Gleixner , linux-kernel@vger.kernel.org, Ashok Raj , Tim Chen , Andy Lutomirski , Linus Torvalds , Greg KH , Andrea Arcangeli , Andi Kleen , Arjan Van De Ven , Dan Williams , Jun Nakajima , Asit Mallick , Jason Baron Subject: Re: [PATCH 23/35] x86/speculation: Add basic speculation control code Message-ID: <20180118182431.xvmk6kzxpzu43b43@treble> References: <20180118134800.711245485@infradead.org> <20180118140152.830682032@infradead.org> <20180118163745.t5nmwdr53wjsl7o5@treble> <73a5735a-6a5b-0e0f-1f0b-e7cd955880d2@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.6.0.1 (2016-04-01) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-LABELS: =?utf-8?b?IlxcSW1wb3J0YW50Ig==?= X-GMAIL-THRID: =?utf-8?q?1589948948566960870?= X-GMAIL-MSGID: =?utf-8?q?1589955659708084395?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On Thu, Jan 18, 2018 at 06:12:36PM +0100, Paolo Bonzini wrote: > On 18/01/2018 18:08, Dave Hansen wrote: > > On 01/18/2018 08:37 AM, Josh Poimboeuf wrote: > >>> > >>> --- a/Documentation/admin-guide/kernel-parameters.txt > >>> +++ b/Documentation/admin-guide/kernel-parameters.txt > >>> @@ -3932,6 +3932,7 @@ > >>> retpoline - replace indirect branches > >>> retpoline,generic - google's original retpoline > >>> retpoline,amd - AMD-specific minimal thunk > >>> + ibrs - Intel: Indirect Branch Restricted Speculation > >> Are there plans to add spectre_v2=ibrs_always to prevent SMT-based > >> attacks? > > > > What does "ibrs_always" mean to you? Maybe ibrs_always isn't the best name. Basically we need an option to protect user-user attacks via SMT. It could be implemented with IBRS=1, or STIBP, or as part of the mythical IBRS_ATT. Maybe a 'user_smt' option, which could be appended to existing 'retpoline' or 'ibrs' options? Like spectre_v2=retpoline,user_smt or spectre_v2=ibrs,user_smt? > > There is a second bit in the MSR (STIBP) that is intended to keep > > hyperthreads from influencing each-other. That is behavior is implicit > > when IBRS is enabled. Does this bit exist yet? I've never seen any patches for it. > Yeah, I think we should have a mode to always leave that enabled, or > always set IBRS=1. > > > I think ibrs_always *should* probably be kept to refer to the future > > CPUs that can safely leave IBRS enabled all the time. > > Is that "safely" or "without throwing performance down the drain"? > > Does "always IBRS=1" *hinder* the mitigation on existing processor, as > long as you reset IBRS=1 on kernel entry and vmexit? Or is it just slow? Yes, enquiring minds want to know... -- Josh