From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: ACJfBouDV/R0mEgss2+KOg1Ug2q1BU2Eoi/yeMKXz1SQIwFF2Q+WgOSCOLzfsUL2YrMvQ+yBuHPH ARC-Seal: i=1; a=rsa-sha256; t=1516300283; cv=none; d=google.com; s=arc-20160816; b=KKXzO5S51z40RKDDP4o6JJHIBohT2QYffRUxqvPE7k3lfME1cMlhtrqkoRGqDpumOx yMqOJuj329mHR5i0MNcvzgpZdBY/MUWt3jTLq7Bo4UB86Vk+WwVMmnOQ/eWOMTKTqT0u GaTZDz05QcbRkt/5vSVVIgWJbVOQVmUcz5zpdsEmh6lHMBdgn4aNDxz0k6/DurCv6c9d bW2IZMEjAY+GjzHfILkzY4jSZmDx6drRjh4j1T2HZ8jIneQs8P0jtcVRYoRafmkoeAMW zP/s+8Qp2pivkVMDPetoR3P+hMkwklXOobwbVbnqE/zSQKJVG1lpptuzjPuf+odyLTGk q9rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=user-agent:in-reply-to:content-disposition:mime-version:references :message-id:subject:cc:to:from:date:arc-authentication-results; bh=wYE6VcJG/zqpuq+XhoDtxT+C09mwM8E7zNlFQfzPYmc=; b=EnQatPO+vKo7YydImi6nhVlFOsh+VZhlp3CyrE6KfcoVBXPPuVmJ5qmJJAGO+wY7/a 0tkeW59BI3CLhMZ0Pz5da533O7BH2efdn1DeyMEuTcJFPlgub95ikHw16khKnfnBq/Jl bEI9Jm16WmnIXbqHJLs9d8nIw5+XVHI7zvhj55SoaNmQZZiZmLrjQGN9P3crQ5EQeDct BEZlpNOJ5zAx6TKYYOdD4oc5ktPzkwqGmpeoWXWvWdu9+PXrJJfzWm9H+4l00UiuT6f1 WpMpc3hr/0+qpkUtpg36qX2qcPF69IPaXWBHQvExn8tR8K57uWxhVTm/W6IVOe6rCDtr A6fQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of bp@alien8.de designates 2a01:4f8:190:11c2::b:1457 as permitted sender) smtp.mailfrom=bp@alien8.de Authentication-Results: mx.google.com; spf=pass (google.com: domain of bp@alien8.de designates 2a01:4f8:190:11c2::b:1457 as permitted sender) smtp.mailfrom=bp@alien8.de Date: Thu, 18 Jan 2018 19:31:16 +0100 From: Borislav Petkov To: Peter Zijlstra Cc: David Woodhouse , Thomas Gleixner , Josh Poimboeuf , linux-kernel@vger.kernel.org, Dave Hansen , Ashok Raj , Tim Chen , Andy Lutomirski , Linus Torvalds , Greg KH , Andrea Arcangeli , Andi Kleen , Arjan Van De Ven , Dan Williams , Paolo Bonzini , Jun Nakajima , Asit Mallick , Jason Baron Subject: Re: [PATCH 29/35] x86/speculation: Add IPBP support Message-ID: <20180118183116.umu4btegm2a5v7ut@pd.tnic> References: <20180118134800.711245485@infradead.org> <20180118140153.200767455@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20180118140153.200767455@infradead.org> User-Agent: NeoMutt/20170609 (1.8.3) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-LABELS: =?utf-8?b?IlxcSW1wb3J0YW50Ig==?= X-GMAIL-THRID: =?utf-8?q?1589947990506198301?= X-GMAIL-MSGID: =?utf-8?q?1589956085525988531?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On Thu, Jan 18, 2018 at 02:48:29PM +0100, Peter Zijlstra wrote: > From: Thomas Gleixner <--- Add commit message here. > Signed-off-by: Thomas Gleixner > Signed-off-by: Peter Zijlstra (Intel) > --- > arch/x86/include/asm/cpufeatures.h | 4 +++- > arch/x86/include/asm/msr-index.h | 3 +++ > arch/x86/include/asm/nospec-branch.h | 9 +++++++++ > arch/x86/kernel/cpu/bugs.c | 2 ++ > arch/x86/kernel/cpu/specctrl.c | 9 +++++++++ > 5 files changed, 26 insertions(+), 1 deletion(-) > > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -212,8 +212,9 @@ > > #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ > #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ > -#define X86_FEATURE_SPEC_CTRL ( 7*32+20) /* Speculation Control */ > +#define X86_FEATURE_SPEC_CTRL ( 7*32+20) /* Speculation Control - Intel only */ > #define X86_FEATURE_IBRS ( 7*32+21) /* Indirect Branch Restricted Speculation */ > +#define X86_FEATURE_IBPB ( 7*32+22) /* Indirect Branch Prediction Barrier */ > > /* Virtualization flags: Linux defined, word 8 */ > #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ > @@ -273,6 +274,7 @@ > #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ > #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ > #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ > +#define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Barrier support */ I guess you could make that #define X86_FEATURE_AMD_IBPB (13*32+12) /* "" Indirect Branch Prediction Barrier support */ (note the "" in the comment) so that it doesn't appear in /proc/cpuinfo as those two flags denote the same thing. > /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ > #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -46,6 +46,9 @@ > #define SPEC_CTRL_DISABLE_IBRS (0 << 0) > #define SPEC_CTRL_ENABLE_IBRS (1 << 0) > > +#define MSR_IA32_PRED_CMD 0x00000049 > +#define PRED_CMD_IBPB (1 << 0) > + > #define MSR_IA32_PERFCTR0 0x000000c1 > #define MSR_IA32_PERFCTR1 0x000000c2 > #define MSR_FSB_FREQ 0x000000cd > --- a/arch/x86/include/asm/nospec-branch.h > +++ b/arch/x86/include/asm/nospec-branch.h > @@ -231,5 +231,14 @@ static inline void restart_indirect_bran > if (static_cpu_has(X86_FEATURE_IBRS)) > native_wrmsrl(MSR_IA32_SPEC_CTRL, SPEC_CTRL_DISABLE_IBRS); > } > + > +void specctrl_init_ibpb(void); > + > +static inline void indirect_branch_prediction_barrier(void) That's a long name: ibp_barrier() is what I had called it, with a comment above it. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.