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From: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>
To: jerin.jacob@caviumnetworks.com, bruce.richardson@intel.com,
	harry.van.haaren@intel.com
Cc: dev@dpdk.org, Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>
Subject: [PATCH v2 1/2] build: add support for ARM builds
Date: Fri, 19 Jan 2018 18:35:57 +0530	[thread overview]
Message-ID: <20180119130558.6719-1-pbhagavatula@caviumnetworks.com> (raw)
In-Reply-To: <20171219105338.198727-1-bruce.richardson@intel.com>

From: Bruce Richardson <bruce.richardson@intel.com>

Add files to enable compiling for ARM cross builds.
This can be tested by doing a cross-compile for armv8-a type using
the linaro gcc toolchain.

        meson arm-build --cross-file aarch64_cross.txt
        ninja -C arm-build

where aarch64_cross.txt contained the following

        [binaries]
        c = 'aarch64-linux-gnu-gcc'
        cpp = 'aarch64-linux-gnu-cpp'
        ar = 'aarch64-linux-gnu-ar'

        [host_machine]
        system = 'linux'
        cpu_family = 'aarch64'
        cpu = 'armv8-a'
        endian = 'little'

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@caviumnetworks.com>
---

 v2 Changes:
 - Merged RFC patch.
 - Added framework to easily other vendor specific flags
 - renamed machine_arg to machine_args

 config/arm/meson.build                             | 63 ++++++++++++++++++++++
 config/meson.build                                 |  4 +-
 lib/librte_eal/common/arch/arm/meson.build         | 33 ++++++++++++
 lib/librte_eal/common/include/arch/arm/meson.build | 57 ++++++++++++++++++++
 4 files changed, 156 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/meson.build
 create mode 100644 lib/librte_eal/common/arch/arm/meson.build
 create mode 100644 lib/librte_eal/common/include/arch/arm/meson.build

diff --git a/config/arm/meson.build b/config/arm/meson.build
new file mode 100644
index 000000000..0c2e57657
--- /dev/null
+++ b/config/arm/meson.build
@@ -0,0 +1,63 @@
+#   BSD LICENSE
+#
+#   Copyright(c) 2017 Intel Corporation.
+#   All rights reserved.
+#
+#   Redistribution and use in source and binary forms, with or without
+#   modification, are permitted provided that the following conditions
+#   are met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in
+#       the documentation and/or other materials provided with the
+#       distribution.
+#     * Neither the name of Intel Corporation nor the names of its
+#       contributors may be used to endorse or promote products derived
+#       from this software without specific prior written permission.
+#
+#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+# for checking defines we need to use the correct compiler flags
+march_opt = '-march=@0@'.format(machine)
+
+dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
+if cc.sizeof('void *') == 8
+	dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128)
+	dpdk_conf.set('RTE_ARCH_ARM64', 1)
+	dpdk_conf.set('RTE_ARCH_64', 1)
+else
+	dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
+	dpdk_conf.set('RTE_ARCH_ARM', 1)
+	dpdk_conf.set('RTE_ARCH_ARMv7', 1)
+endif
+
+if cc.get_define('__ARM_NEON', args: march_opt) != ''
+	dpdk_conf.set('RTE_MACHINE_CPUFLAG_NEON', 1)
+	compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
+endif
+
+if cc.get_define('__ARM_FEATURE_CRC32', args: march_opt) != ''
+	dpdk_conf.set('RTE_MACHINE_CPUFLAG_CRC32', 1)
+	compile_time_cpuflags += ['RTE_CPUFLAG_CRC32']
+endif
+
+if cc.get_define('__ARM_FEATURE_CRYPTO', args: march_opt) != ''
+	dpdk_conf.set('RTE_MACHINE_CPUFLAG_AES', 1)
+	dpdk_conf.set('RTE_MACHINE_CPUFLAG_PMULL', 1)
+	dpdk_conf.set('RTE_MACHINE_CPUFLAG_SHA1', 1)
+	dpdk_conf.set('RTE_MACHINE_CPUFLAG_SHA2', 1)
+	compile_time_cpuflags += ['RTE_CPUFLAG_AES', 'RTE_CPUFLAG_PMULL',
+	'RTE_CPUFLAG_SHA1', 'RTE_CPUFLAG_SHA2']
+endif
diff --git a/config/meson.build b/config/meson.build
index 95223042f..fa55c53a5 100644
--- a/config/meson.build
+++ b/config/meson.build
@@ -56,8 +56,10 @@ endforeach
 compile_time_cpuflags = []
 if host_machine.cpu_family().startswith('x86')
 	arch_subdir = 'x86'
-	subdir(arch_subdir)
+elif host_machine.cpu_family().startswith('arm') or host_machine.cpu_family().startswith('aarch')
+	arch_subdir = 'arm'
 endif
+subdir(arch_subdir)
 dpdk_conf.set('RTE_COMPILE_TIME_CPUFLAGS', ','.join(compile_time_cpuflags))

 # set the install path for the drivers
diff --git a/lib/librte_eal/common/arch/arm/meson.build b/lib/librte_eal/common/arch/arm/meson.build
new file mode 100644
index 000000000..57158271d
--- /dev/null
+++ b/lib/librte_eal/common/arch/arm/meson.build
@@ -0,0 +1,33 @@
+#   BSD LICENSE
+#
+#   Copyright(c) 2017 Intel Corporation.
+#   All rights reserved.
+#
+#   Redistribution and use in source and binary forms, with or without
+#   modification, are permitted provided that the following conditions
+#   are met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in
+#       the documentation and/or other materials provided with the
+#       distribution.
+#     * Neither the name of Intel Corporation nor the names of its
+#       contributors may be used to endorse or promote products derived
+#       from this software without specific prior written permission.
+#
+#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+eal_common_arch_sources = files('rte_cpuflags.c',
+	'rte_cycles.c')
diff --git a/lib/librte_eal/common/include/arch/arm/meson.build b/lib/librte_eal/common/include/arch/arm/meson.build
new file mode 100644
index 000000000..c5d399bf1
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/meson.build
@@ -0,0 +1,57 @@
+#   BSD LICENSE
+#
+#   Copyright(c) 2017 Intel Corporation.
+#   All rights reserved.
+#
+#   Redistribution and use in source and binary forms, with or without
+#   modification, are permitted provided that the following conditions
+#   are met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in
+#       the documentation and/or other materials provided with the
+#       distribution.
+#     * Neither the name of Intel Corporation nor the names of its
+#       contributors may be used to endorse or promote products derived
+#       from this software without specific prior written permission.
+#
+#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+install_headers(
+	'rte_atomic_32.h',
+	'rte_atomic_64.h',
+	'rte_atomic.h',
+	'rte_byteorder.h',
+	'rte_cpuflags_32.h',
+	'rte_cpuflags_64.h',
+	'rte_cpuflags.h',
+	'rte_cycles_32.h',
+	'rte_cycles_64.h',
+	'rte_cycles.h',
+	'rte_io_64.h',
+	'rte_io.h',
+	'rte_memcpy_32.h',
+	'rte_memcpy_64.h',
+	'rte_memcpy.h',
+	'rte_pause_32.h',
+	'rte_pause_64.h',
+	'rte_pause.h',
+	'rte_prefetch_32.h',
+	'rte_prefetch_64.h',
+	'rte_prefetch.h',
+	'rte_rwlock.h',
+	'rte_spinlock.h',
+	'rte_vect.h',
+	subdir: get_option('include_subdir_arch'))
--
2.14.1

  parent reply	other threads:[~2018-01-19 13:06 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-19 10:53 [RFC PATCH] RFC build: prototype support for ARM builds Bruce Richardson
2017-12-19 13:27 ` Luca Boccassi
2017-12-19 14:17   ` Bruce Richardson
2018-01-19 13:05 ` Pavan Nikhilesh [this message]
2018-01-19 13:05   ` [PATCH v2 2/2] build: add support for detecting march on ARM Pavan Nikhilesh
2018-01-19 13:52 ` [PATCH v3 1/2] build: add support for ARM builds Pavan Nikhilesh
2018-01-19 13:52   ` [PATCH v3 2/2] build: add support for detecting march on ARM Pavan Nikhilesh
2018-01-19 16:17     ` Bruce Richardson
2018-01-19 17:13       ` Pavan Nikhilesh
2018-01-19 17:30         ` Bruce Richardson
2018-01-19 16:24   ` [PATCH v3 1/2] build: add support for ARM builds Bruce Richardson
2018-01-19 16:49     ` Hemant Agrawal
2018-01-19 17:33       ` Bruce Richardson
2018-01-19 18:23 ` [PATCH v4 " Pavan Nikhilesh
2018-01-19 18:23   ` [PATCH v4 2/2] build: add support for detecting march on ARM Pavan Nikhilesh
2018-01-22  5:52     ` Herbert Guan
2018-01-22  7:16       ` Pavan Nikhilesh
2018-01-22 11:46 ` [PATCH v5 1/2] build: add support for ARM builds Pavan Nikhilesh
2018-01-22 11:46   ` [PATCH v5 2/2] build: add support for detecting march on ARM Pavan Nikhilesh
2018-01-22 12:30     ` Bruce Richardson
2018-01-22 12:37       ` Pavan Nikhilesh
2018-01-22 14:09         ` Bruce Richardson
2018-01-22 14:44           ` Pavan Nikhilesh
2018-01-22 15:26 ` [PATCH v6 1/4] build: add support for ARM builds Pavan Nikhilesh
2018-01-22 15:26   ` [PATCH v6 2/4] build: add support for detecting march on ARM Pavan Nikhilesh
2018-01-22 15:26   ` [PATCH v6 3/4] build: add support for vendor specific ARM cross builds Pavan Nikhilesh
2018-01-22 15:26   ` [PATCH v6 4/4] doc: add instructions to cross compile using meson Pavan Nikhilesh
2018-01-22 16:10   ` [PATCH v6 1/4] build: add support for ARM builds Bruce Richardson
2018-01-22 16:20   ` Jerin Jacob
2018-01-22 16:26     ` Bruce Richardson

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