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From: Paulo Zanoni <paulo.r.zanoni@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [PATCH 17/17] drm/i915/icl: Handle expanded PLANE_CTL_FORMAT field
Date: Tue, 23 Jan 2018 17:05:36 -0200	[thread overview]
Message-ID: <20180123190536.11208-18-paulo.r.zanoni@intel.com> (raw)
In-Reply-To: <20180123190536.11208-1-paulo.r.zanoni@intel.com>

From: James Ausmus <james.ausmus@intel.com>

ICL+ adds changes the PLANE_CTL_FORMAT field from [27:24] to [27:23],
however, all existing PLANE_CTL_FORMAT_* definitions still map to the
correct values.  Add an ICL_PLANE_CTL_FORMAT_MASK definition, and use
that for masking for the conversion to fourcc.

v2: No changes

v3: Change new definition name, drop comment (Rodrigo)

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 6 ++++++
 drivers/gpu/drm/i915/intel_display.c | 5 ++++-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0cb77cd18cdb..1218a6a88cd8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6372,6 +6372,11 @@ enum {
 #define _PLANE_CTL_3_A				0x70380
 #define   PLANE_CTL_ENABLE			(1 << 31)
 #define   PLANE_CTL_PIPE_GAMMA_ENABLE		(1 << 30)   /* Pre-GLK */
+/*
+ * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
+ * expanded to include bit 23 as well. However, the shift-24 based values
+ * correctly map to the same formats in ICL, as long as bit 23 is set to 0
+ */
 #define   PLANE_CTL_FORMAT_MASK			(0xf << 24)
 #define   PLANE_CTL_FORMAT_YUV422		(  0 << 24)
 #define   PLANE_CTL_FORMAT_NV12			(  1 << 24)
@@ -6381,6 +6386,7 @@ enum {
 #define   PLANE_CTL_FORMAT_AYUV			(  8 << 24)
 #define   PLANE_CTL_FORMAT_INDEXED		( 12 << 24)
 #define   PLANE_CTL_FORMAT_RGB_565		( 14 << 24)
+#define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
 #define   PLANE_CTL_PIPE_CSC_ENABLE		(1 << 23) /* Pre-GLK */
 #define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)
 #define   PLANE_CTL_KEY_ENABLE_SOURCE		(  1 << 21)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3eb2359c221b..7d5362e8bc3d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8516,7 +8516,10 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
 
 	val = I915_READ(PLANE_CTL(pipe, plane_id));
 
-	pixel_format = val & PLANE_CTL_FORMAT_MASK;
+	if (INTEL_GEN(dev_priv) >= 11)
+		pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK;
+	else
+		pixel_format = val & PLANE_CTL_FORMAT_MASK;
 
 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
 		alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id));
-- 
2.14.3

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  parent reply	other threads:[~2018-01-23 19:06 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-23 19:05 [PATCH 00/17] ICL display initialization and some plane bits Paulo Zanoni
2018-01-23 19:05 ` [PATCH 01/17] drm/i915/icl: add the main CDCLK functions Paulo Zanoni
2018-01-26 23:14   ` James Ausmus
2018-02-01 20:09     ` Paulo Zanoni
2018-01-29 10:51   ` Imre Deak
2018-02-01 20:08     ` Paulo Zanoni
2018-02-01 20:40       ` Imre Deak
2018-02-02 19:57   ` Paulo Zanoni
2018-02-02 22:12     ` James Ausmus
2018-01-23 19:05 ` [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values Paulo Zanoni
2018-01-24  0:32   ` James Ausmus
2018-01-26 20:24     ` Paulo Zanoni
2018-01-26 20:47       ` James Ausmus
2018-01-26 20:33   ` Ville Syrjälä
2018-02-02 16:23   ` Paulo Zanoni
2018-02-02 18:17     ` James Ausmus
2018-01-23 19:05 ` [PATCH 03/17] drm/i915/icl: implement the display init/uninit sequences Paulo Zanoni
2018-01-26 23:25   ` James Ausmus
2018-01-23 19:05 ` [PATCH 04/17] drm/i915/icl: Enable both DBuf slices during init Paulo Zanoni
2018-01-24  0:49   ` James Ausmus
2018-01-26 20:50     ` Paulo Zanoni
2018-01-29 17:47       ` Paulo Zanoni
2018-01-23 19:05 ` [PATCH 05/17] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL Paulo Zanoni
2018-01-24  0:58   ` James Ausmus
2018-01-23 19:05 ` [PATCH 06/17] drm/i915/icl: Do not fix dbuf block size to 512 Paulo Zanoni
2018-01-24  1:14   ` James Ausmus
2018-01-29 23:07   ` Paulo Zanoni
2018-01-29 23:32     ` James Ausmus
2018-01-23 19:05 ` [PATCH 07/17] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed Paulo Zanoni
2018-01-26 23:50   ` James Ausmus
2018-01-29 18:16     ` Paulo Zanoni
2018-01-29 23:08   ` [PATCH 07/13] " Paulo Zanoni
2018-01-23 19:05 ` [PATCH 08/17] drm/i915/icl: NV12 y-plane ddb is not in same plane Paulo Zanoni
2018-01-25 22:31   ` James Ausmus
2018-01-23 19:05 ` [PATCH 09/17] drm/i915/icl: Introduce MBus related registers Paulo Zanoni
2018-01-25 22:38   ` James Ausmus
2018-01-23 19:05 ` [PATCH 10/17] drm/i915/icl: initialize MBus during display init Paulo Zanoni
2018-01-25 22:39   ` James Ausmus
2018-01-23 19:05 ` [PATCH 11/17] drm/i915/icl: program mbus during pipe enable Paulo Zanoni
2018-01-25 22:42   ` James Ausmus
2018-01-23 19:05 ` [PATCH 12/17] drm/i915/icl: track dbuf slice-2 status Paulo Zanoni
2018-01-25 23:08   ` James Ausmus
2018-01-23 19:05 ` [PATCH 13/17] drm/i915/icl: Enable 2nd DBuf slice only when needed Paulo Zanoni
2018-01-25 22:56   ` James Ausmus
2018-03-14 16:19   ` [PATCH 2/2] " Mahesh Kumar
2018-01-23 19:05 ` [PATCH 14/17] drm/i915/icl: update ddb entry start/end mask during hw ddb readout Paulo Zanoni
2018-01-25 23:00   ` James Ausmus
2018-01-23 19:05 ` [PATCH 15/17] drm/i915/gen11: fix the SAGV block time for gen11 Paulo Zanoni
2018-01-25 23:09   ` James Ausmus
2018-01-23 19:05 ` [PATCH 16/17] drm/i915/icl: enable SAGV for ICL platform Paulo Zanoni
2018-01-25 23:09   ` James Ausmus
2018-01-29 22:07   ` Paulo Zanoni
2018-01-23 19:05 ` Paulo Zanoni [this message]
2018-01-23 19:32 ` ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits Patchwork
2018-01-23 20:32 ` Patchwork
2018-01-29 23:27 ` ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits (rev2) Patchwork
2018-02-02 17:10 ` ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits (rev4) Patchwork
2018-02-02 17:28 ` Patchwork
2018-02-02 20:22 ` ✗ Fi.CI.BAT: failure for ICL display initialization and some plane bits (rev5) Patchwork

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