From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH v3 02/45] target/hppa: Define the rest of the PSW
Date: Wed, 24 Jan 2018 15:25:42 -0800 [thread overview]
Message-ID: <20180124232625.30105-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org>
We don't actually do anything with most of the bits yet,
but at least they have names and we have somewhere to
store them.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/cpu.h | 47 ++++++++++++++++++++++++++++++++++++++++++++++
target/hppa/helper.c | 53 ++++++++++++++++++++++++++++++++++++++--------------
2 files changed, 86 insertions(+), 14 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 7fad92144c..ea7e495408 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -46,6 +46,52 @@
#define EXCP_SIGILL 4
#define EXCP_SIGFPE 5
+/* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
+#define PSW_I 0x00000001
+#define PSW_D 0x00000002
+#define PSW_P 0x00000004
+#define PSW_Q 0x00000008
+#define PSW_R 0x00000010
+#define PSW_F 0x00000020
+#define PSW_G 0x00000040 /* PA1.x only */
+#define PSW_O 0x00000080 /* PA2.0 only */
+#define PSW_CB 0x0000ff00
+#define PSW_M 0x00010000
+#define PSW_V 0x00020000
+#define PSW_C 0x00040000
+#define PSW_B 0x00080000
+#define PSW_X 0x00100000
+#define PSW_N 0x00200000
+#define PSW_L 0x00400000
+#define PSW_H 0x00800000
+#define PSW_T 0x01000000
+#define PSW_S 0x02000000
+#define PSW_E 0x04000000
+#ifdef TARGET_HPPA64
+#define PSW_W 0x08000000 /* PA2.0 only */
+#else
+#define PSW_W 0
+#endif
+#define PSW_Z 0x40000000 /* PA1.x only */
+#define PSW_Y 0x80000000 /* PA1.x only */
+
+#define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \
+ | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I)
+
+/* ssm/rsm instructions number PSW_W and PSW_E differently */
+#define PSW_SM_I PSW_I /* Enable External Interrupts */
+#define PSW_SM_D PSW_D
+#define PSW_SM_P PSW_P
+#define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */
+#define PSW_SM_R PSW_R /* Enable Recover Counter Trap */
+#ifdef TARGET_HPPA64
+#define PSW_SM_E 0x100
+#define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
+#else
+#define PSW_SM_E 0
+#define PSW_SM_W 0
+#endif
+
typedef struct CPUHPPAState CPUHPPAState;
struct CPUHPPAState {
@@ -56,6 +102,7 @@ struct CPUHPPAState {
target_ulong cr26;
target_ulong cr27;
+ target_long psw; /* All psw bits except the following: */
target_ulong psw_n; /* boolean */
target_long psw_v; /* in most significant bit */
diff --git a/target/hppa/helper.c b/target/hppa/helper.c
index d6d6f06cb0..4231ef3bff 100644
--- a/target/hppa/helper.c
+++ b/target/hppa/helper.c
@@ -39,10 +39,11 @@ target_ulong cpu_hppa_get_psw(CPUHPPAState *env)
/* .........................bcdefgh */
psw |= (psw >> 12) & 0xf;
psw |= env->psw_cb_msb << 7;
- psw <<= 8;
+ psw = (psw & 0xff) << 8;
- psw |= env->psw_n << 21;
- psw |= (env->psw_v < 0) << 17;
+ psw |= env->psw_n * PSW_N;
+ psw |= (env->psw_v < 0) * PSW_V;
+ psw |= env->psw;
return psw;
}
@@ -51,8 +52,9 @@ void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong psw)
{
target_ulong cb = 0;
- env->psw_n = (psw >> 21) & 1;
- env->psw_v = -((psw >> 17) & 1);
+ env->psw = psw & ~(PSW_N | PSW_V | PSW_CB);
+ env->psw_n = (psw / PSW_N) & 1;
+ env->psw_v = -((psw / PSW_V) & 1);
env->psw_cb_msb = (psw >> 15) & 1;
cb |= ((psw >> 14) & 1) << 28;
@@ -106,22 +108,45 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f,
{
HPPACPU *cpu = HPPA_CPU(cs);
CPUHPPAState *env = &cpu->env;
+ target_ulong psw = cpu_hppa_get_psw(env);
+ target_ulong psw_cb;
+ char psw_c[20];
int i;
- cpu_fprintf(f, "IA_F " TARGET_FMT_lx
- " IA_B " TARGET_FMT_lx
- " PSW " TARGET_FMT_lx
- " [N:" TARGET_FMT_ld " V:%d"
- " CB:" TARGET_FMT_lx "]\n ",
- env->iaoq_f, env->iaoq_b, cpu_hppa_get_psw(env),
- env->psw_n, env->psw_v < 0,
- ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28));
- for (i = 1; i < 32; i++) {
+ cpu_fprintf(f, "IA_F " TARGET_FMT_lx " IA_B " TARGET_FMT_lx "\n",
+ env->iaoq_f, env->iaoq_b);
+
+ psw_c[0] = (psw & PSW_W ? 'W' : '-');
+ psw_c[1] = (psw & PSW_E ? 'E' : '-');
+ psw_c[2] = (psw & PSW_S ? 'S' : '-');
+ psw_c[3] = (psw & PSW_T ? 'T' : '-');
+ psw_c[4] = (psw & PSW_H ? 'H' : '-');
+ psw_c[5] = (psw & PSW_L ? 'L' : '-');
+ psw_c[6] = (psw & PSW_N ? 'N' : '-');
+ psw_c[7] = (psw & PSW_X ? 'X' : '-');
+ psw_c[8] = (psw & PSW_B ? 'B' : '-');
+ psw_c[9] = (psw & PSW_C ? 'C' : '-');
+ psw_c[10] = (psw & PSW_V ? 'V' : '-');
+ psw_c[11] = (psw & PSW_M ? 'M' : '-');
+ psw_c[12] = (psw & PSW_F ? 'F' : '-');
+ psw_c[13] = (psw & PSW_R ? 'R' : '-');
+ psw_c[14] = (psw & PSW_Q ? 'Q' : '-');
+ psw_c[15] = (psw & PSW_P ? 'P' : '-');
+ psw_c[16] = (psw & PSW_D ? 'D' : '-');
+ psw_c[17] = (psw & PSW_I ? 'I' : '-');
+ psw_c[18] = '\0';
+ psw_cb = ((env->psw_cb >> 4) & 0x01111111) | (env->psw_cb_msb << 28);
+
+ cpu_fprintf(f, "PSW " TARGET_FMT_lx " CB " TARGET_FMT_lx " %s\n",
+ psw, psw_cb, psw_c);
+
+ for (i = 0; i < 32; i++) {
cpu_fprintf(f, "GR%02d " TARGET_FMT_lx " ", i, env->gr[i]);
if ((i % 4) == 3) {
cpu_fprintf(f, "\n");
}
}
+ cpu_fprintf(f, "\n");
/* ??? FR */
}
--
2.14.3
next prev parent reply other threads:[~2018-01-24 23:26 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-24 23:25 [Qemu-devel] [PATCH v3 00/45] hppa-softmmu Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 01/45] target/hppa: Skeleton support for hppa-softmmu Richard Henderson
2018-01-24 23:25 ` Richard Henderson [this message]
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 03/45] target/hppa: Disable gateway page emulation for system mode Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 04/45] target/hppa: Define hardware exception types Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 05/45] target/hppa: Split address size from register size Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 06/45] target/hppa: Implement mmu_idx from IA privilege level Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 07/45] target/hppa: Implement the system mask instructions Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 08/45] target/hppa: Add space registers Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 09/45] target/hppa: Add control registers Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 10/45] target/hppa: Adjust insn mask for mfctl, w Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 11/45] target/hppa: Implement rfi Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 12/45] target/hppa: Fill in hppa_cpu_do_interrupt/hppa_cpu_exec_interrupt Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 13/45] target/hppa: Implement unaligned access trap Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 14/45] target/hppa: Use space registers in data operations Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 15/45] target/hppa: Avoid privilege level decrease during branches Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 16/45] target/hppa: Implement IASQ Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 17/45] target/hppa: Implement tlb_fill Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 18/45] target/hppa: Implement external interrupts Richard Henderson
2018-01-24 23:25 ` [Qemu-devel] [PATCH v3 19/45] target/hppa: Implement the interval timer Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 20/45] target/hppa: Log unimplemented instructions Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 21/45] target/hppa: Implement I*TLBA and I*TLBP insns Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 22/45] target/hppa: Implement P*TLB and P*TLBE insns Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 23/45] target/hppa: Implement LDWA Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 24/45] target/hppa: Implement LPA Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 25/45] target/hppa: Implement LCI Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 26/45] target/hppa: Implement SYNCDMA insn Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 27/45] target/hppa: Implement halt and reset instructions Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 28/45] target/hppa: Optimize for flat addressing space Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 29/45] target/hppa: Add system registers to gdbstub Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 30/45] target/hppa: Add migration for the cpu Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 31/45] target/hppa: Implement B,GATE insn Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 32/45] target/hppa: Only use EXCP_DTLB_MISS Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 33/45] qom: Add MMU_DEBUG_LOAD Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 34/45] target/hppa: Use MMU_DEBUG_LOAD when reloading for CR[IIR] Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 35/45] target/hppa: Increase number of temp regs Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 36/45] target/hppa: Fix comment Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 37/45] target/hppa: Implement LDSID for system mode Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 38/45] target/hppa: Implement a pause instruction Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 39/45] target/hppa: Implement STWA Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 40/45] target/hppa: Enable MTTCG Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 41/45] hw/hppa: Implement DINO system board Richard Henderson
2018-01-25 11:22 ` Philippe Mathieu-Daudé
2018-01-27 13:22 ` Helge Deller
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 42/45] pc-bios: Add hppa-firmware.img and git submodule Richard Henderson
2018-02-04 22:40 ` Philippe Mathieu-Daudé
2018-02-06 7:35 ` Helge Deller
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 43/45] hw/hppa: Add MAINTAINERS entry Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 44/45] target/hppa: Fix 32-bit operand masks for 0E FCVT Richard Henderson
2018-01-24 23:26 ` [Qemu-devel] [PATCH v3 45/45] target/hppa: Implement PROBE for system mode Richard Henderson
2018-01-25 0:11 ` [Qemu-devel] [PATCH v3 00/45] hppa-softmmu no-reply
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