From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51467) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eeUS1-000592-2B for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eeURz-0002Du-GU for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:29 -0500 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:44785) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eeURz-0002Cr-At for qemu-devel@nongnu.org; Wed, 24 Jan 2018 18:27:27 -0500 Received: by mail-pf0-x243.google.com with SMTP id m26so4356011pfj.11 for ; Wed, 24 Jan 2018 15:27:27 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z19sm9760028pfh.185.2018.01.24.15.27.24 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 24 Jan 2018 15:27:25 -0800 (PST) From: Richard Henderson Date: Wed, 24 Jan 2018 15:26:19 -0800 Message-Id: <20180124232625.30105-40-richard.henderson@linaro.org> In-Reply-To: <20180124232625.30105-1-richard.henderson@linaro.org> References: <20180124232625.30105-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH v3 39/45] target/hppa: Implement STWA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Richard Henderson --- target/hppa/translate.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d84090d479..b9b097acc9 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3108,6 +3108,22 @@ static DisasJumpType trans_ldwa_idx_x(DisasContext *ctx, uint32_t insn, ctx->mmu_idx = hold_mmu_idx; return ret; } + +static DisasJumpType trans_stwa_idx_i(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + int hold_mmu_idx = ctx->mmu_idx; + DisasJumpType ret; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + + /* ??? needs fixing for hppa64 -- ldda does not follow the same + format wrt the sub-opcode in bits 6:9. */ + ctx->mmu_idx = MMU_PHYS_IDX; + ret = trans_st_idx_i(ctx, insn, di); + ctx->mmu_idx = hold_mmu_idx; + return ret; +} #endif static const DisasInsn table_index_mem[] = { @@ -3117,8 +3133,9 @@ static const DisasInsn table_index_mem[] = { { 0x0c0001c0u, 0xfc0003c0, trans_ldcw }, { 0x0c001300u, 0xfc0013c0, trans_stby }, #ifndef CONFIG_USER_ONLY - { 0x0c001180u, 0xfc00d3c0, trans_ldwa_idx_i }, /* LDWA, im */ { 0x0c000180u, 0xfc00d3c0, trans_ldwa_idx_x }, /* LDWA, rx */ + { 0x0c001180u, 0xfc00d3c0, trans_ldwa_idx_i }, /* LDWA, im */ + { 0x0c001380u, 0xfc00d3c0, trans_stwa_idx_i }, /* STWA, im */ #endif }; -- 2.14.3