From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x224kElAML3mzSrUjTGLqibkz84jb31HA2yU+9v/q5/SBgyDHKUtIzw6ZrFYhxY62MnVmqeZW ARC-Seal: i=1; a=rsa-sha256; t=1516873388; cv=none; d=google.com; s=arc-20160816; b=xd/i2Bzytrcg+kJoE0071ZiUskBMqdXA5TOGTZcmJmhFqRrzqSoDq1Ajr8/uRdO5+y hegNAC1fJmB2qRVePlDaFxkrv6AtOyeVA0E11uthcoNG2K4XsN5GyJrVdAkOuKUq6GgI SzHPhdSWNUMtPfKV4VJbWYS0BOxVHsulTyqK+GTSpWtGkkL/ceDWQUUNel9I8MX6UVL4 6BRWik4vUPXa4I25LIsC2/sQ0vVdgs2G1UY5PTNu8p//T1wgJBjIRSWrZEmGbaWUDEv5 77wF5akcCCkEYJDL9s6N7/IUbZ0GlxqH5i9f17ddrMApJj5VWRoO33sg9vo7gFNTycJq yAZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=user-agent:in-reply-to:content-disposition:mime-version:references :message-id:subject:cc:to:from:date:dkim-signature :arc-authentication-results; bh=UZSgVl7OJmFjSahAiDZ052mrc+SgDV8i2mc+EpXJcwA=; b=rfsLJ/cn+xj+BIlV3Us2oVG0wcUHEaJTQ/UmyG09D239cmdqoj4t+h22ohY72xwDaX AazVoWKRjkblhxh72AAdVkSF68LBa64AM0/zxnczzhgKcpy8+sRRkAYsLN0pZpVuLyWO jrOEdGUTKZqCjWkPi5iFZ3ATpkHB5Ko0VYbm0P3xsBA3nBuhiHxHjGjGqycqN/4paWju IkYwkcVyPHbCvEAqGtTNAFIB/aOIECEbBSdbe52PuM1qSjBxDLbst/nUTy3Sd/CBPYoa cey0fK51OLqbOhntleGkz8FMhUSknYUWvOtpOtp76BMAx0yunOQpoigE21RPK1Mcx0W9 EldA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b=sHZoH47a; spf=pass (google.com: best guess record for domain of peterz@infradead.org designates 65.50.211.133 as permitted sender) smtp.mailfrom=peterz@infradead.org Authentication-Results: mx.google.com; dkim=pass header.i=@infradead.org header.s=bombadil.20170209 header.b=sHZoH47a; spf=pass (google.com: best guess record for domain of peterz@infradead.org designates 65.50.211.133 as permitted sender) smtp.mailfrom=peterz@infradead.org Date: Thu, 25 Jan 2018 10:42:58 +0100 From: Peter Zijlstra To: David Woodhouse Cc: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org, dave.hansen@intel.com, gnomes@lxorguk.ukuu.org.uk, ashok.raj@intel.com, mingo@kernel.org Subject: Re: [PATCH v4 5/7] x86/pti: Do not enable PTI on processors which are not vulnerable to Meltdown Message-ID: <20180125094258.GZ2228@hirez.programming.kicks-ass.net> References: <1516872189-16577-1-git-send-email-dwmw@amazon.co.uk> <1516872189-16577-6-git-send-email-dwmw@amazon.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1516872189-16577-6-git-send-email-dwmw@amazon.co.uk> User-Agent: Mutt/1.9.2 (2017-12-15) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590555846213033818?= X-GMAIL-MSGID: =?utf-8?q?1590557029786665014?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On Thu, Jan 25, 2018 at 09:23:07AM +0000, David Woodhouse wrote: > +static bool __init early_cpu_vulnerable_meltdown(struct cpuinfo_x86 *c) > +{ > + u64 ia32_cap = 0; > + > + if (x86_match_cpu(cpu_no_meltdown)) > + return false; > + > + if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) > + rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); I think it was suggested a while back to write this like: if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES) && !rdmsrl_safe(MSR_IA32_ARCH_CAPABILITIES, ia32_cap)) to deal with funny virt scenarios where they accidentally advertise the CPUID bit but don't in fact provide the MSR. > + > + /* Rogue Data Cache Load? No! */ > + if (ia32_cap & ARCH_CAP_RDCL_NO) > + return false; > + > + return true; > +}