From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x2270Zx/+0RaKnP1TotSxIpt3CgUXPFl3oxvFlfx+WhPRKz3V3OpaqRbUJpjn0QJ/BqKxWw5s ARC-Seal: i=1; a=rsa-sha256; t=1516880497; cv=none; d=google.com; s=arc-20160816; b=dxYSr3Mt0cpAx2/zidCnPuZ9wHxLKuQS4kfNKWT9q4SRWf4APL8q45ruclxNa+4vC/ /x48JCMd1xtvf1KPVDkWNX6ceawayCmBwUZozTqw3isJPhrtxsS3q7pa3LlBo0uNwdXM rFgND+Nr6w9pGbQpdTIQIYoJbEFth+PZTloiDqz9jinDgH2acqHY58eyufHYQPdhj5cV zq0mQJYvFimOsO8vnq+/FwUwbabS1gd5yuVPeMqAmV7AEkGbfnHM20e07sEgD8UwFCJO Yfz2x3d2ZqYrLbH93J/uHdmBf04CRlfWoB3ho2WgWcYkK9K69mkIykwliXizfTLqRqbl UV7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=user-agent:in-reply-to:content-disposition:mime-version:references :message-id:subject:cc:to:from:date:arc-authentication-results; bh=dqOfbCDK9fVDMaYZD3neKZKck75nNgmBnWrbWAZvNYw=; b=0TZ0Qlcf1bsfyOF1CvypdSJle5yFK6f5mYnDUa6gezRrbw5ZEkNCNRljpjCRsXEGQR RWyUyzG65V86AC3XYtRI41+G+R5939mtVnQPF1VojIJllzIOCvrM3v08y6oXJltIPwyG hyFsvVysSIF61Snu9ZXznLJDYr4drHqePDFEWPurZWthBWt/CBh8qcOcw8XRbbcZAL6j Ze9EIW/slnc0nk2TtBRM8GdDkpD9kz5u46NTIK1/NRF6o1NyAfd+HmTNIfWrgEsHm/rR P3ijpclcDmIlW9HmzMq2YIwilpfPDlGrSxjW0ibxgJdPerZBsa02GE/f1YcxH+7KK2Tv hahA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of bp@alien8.de designates 2a01:4f8:190:11c2::b:1457 as permitted sender) smtp.mailfrom=bp@alien8.de Authentication-Results: mx.google.com; spf=pass (google.com: domain of bp@alien8.de designates 2a01:4f8:190:11c2::b:1457 as permitted sender) smtp.mailfrom=bp@alien8.de Date: Thu, 25 Jan 2018 12:41:27 +0100 From: Borislav Petkov To: David Woodhouse Cc: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org, dave.hansen@intel.com, gnomes@lxorguk.ukuu.org.uk, ashok.raj@intel.com, mingo@kernel.org Subject: Re: [PATCH v4 7/7] x86/speculation: Add basic IBPB (Indirect Branch Prediction Barrier) support Message-ID: <20180125114127.5iw4vy56bb2cs5mr@pd.tnic> References: <1516872189-16577-1-git-send-email-dwmw@amazon.co.uk> <1516872189-16577-8-git-send-email-dwmw@amazon.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1516872189-16577-8-git-send-email-dwmw@amazon.co.uk> User-Agent: NeoMutt/20170609 (1.8.3) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590556144645656370?= X-GMAIL-MSGID: =?utf-8?q?1590564484843881346?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On Thu, Jan 25, 2018 at 09:23:09AM +0000, David Woodhouse wrote: > Expose indirect_branch_prediction_barrier() for use in subsequent patches. > > [karahmed: remove the special-casing of skylake for using IBPB (wtf?), > switch to using ALTERNATIVES instead of static_cpu_has] > [dwmw2: set up ax/cx/dx in the asm too so it gets NOP'd out] > > Signed-off-by: Thomas Gleixner > Signed-off-by: KarimAllah Ahmed > Signed-off-by: David Woodhouse > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/include/asm/nospec-branch.h | 13 +++++++++++++ > arch/x86/kernel/cpu/bugs.c | 7 +++++++ > 3 files changed, 21 insertions(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index ae3212f..6b988278 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -207,6 +207,7 @@ > #define X86_FEATURE_RETPOLINE_AMD ( 7*32+13) /* AMD Retpoline mitigation for Spectre variant 2 */ > #define X86_FEATURE_INTEL_PPIN ( 7*32+14) /* Intel Processor Inventory Number */ > > +#define X86_FEATURE_IBPB ( 7*32+16) /* Using Indirect Branch Prediction Barrier */ > #define X86_FEATURE_MBA ( 7*32+18) /* Memory Bandwidth Allocation */ > #define X86_FEATURE_RSB_CTXSW ( 7*32+19) /* Fill RSB on context switches */ > > diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h > index 4ad4108..34e384c 100644 > --- a/arch/x86/include/asm/nospec-branch.h > +++ b/arch/x86/include/asm/nospec-branch.h > @@ -218,5 +218,18 @@ static inline void vmexit_fill_RSB(void) > #endif > } > > +static inline void indirect_branch_prediction_barrier(void) > +{ > + asm volatile(ALTERNATIVE("", > + "movl %[msr], %%ecx\n\t" > + "movl %[val], %%eax\n\t" > + "movl $0, %%edx\n\t" > + "wrmsr", > + X86_FEATURE_IBPB) > + : : [msr] "i" (MSR_IA32_PRED_CMD), > + [val] "i" (PRED_CMD_IBPB) > + : "eax", "ecx", "edx", "memory"); Lemme paste my simplification suggestion from the other day: "Btw, we can simplify this a bit by dropping the inputs and marking the 3 GPRs as clobbered: alternative_input("", "mov $0x49, %%ecx\n\t" "mov $1, %%eax\n\t" "xor %%edx, %%edx\n\t" "wrmsr\n\t", X86_FEATURE_IBPB, ASM_NO_INPUT_CLOBBER("eax", "ecx", "edx", "memory")); " -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.