From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x224snDTi0w9n5SO4r9L0KIqgRmSkib8aAQYXJHe8EJmCrVr0hDyJ9fpjP44qce/bYB7FGK7/ ARC-Seal: i=1; a=rsa-sha256; t=1516915859; cv=none; d=google.com; s=arc-20160816; b=l1pDRcb0PfJoSLj9rYjNqqgt80JKfJ12aj+8ghSa4fbhZlnA5J4HI+KmORiEn+zyiN feGXoC7YUonNQLXEBLZWyTM32kHK1FGnxh+BFduqq2Y3ucTfriiOjcENevxTbj4HAdtC PkVIYr/wKvZJWvJybORwBbwaLcAuR3fe6QSiYczF6gyQQMPt/3KaOb9zlTY+f1BoovRG L1hMbs51O4wm5tyTPqfiQNh3eOSAwuRAFsjo781W7Qf095ZzczVsHbcvDRGp7BemFsyq iEwOY7M7qIpvAYQSsYrYcf/2pJrMrHWZ0VOhaXRf6j9Bttro3ehjdFoGJ3nrPrQa+iX/ qWRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=user-agent:in-reply-to:content-disposition:mime-version:references :message-id:subject:cc:to:from:date:arc-authentication-results; bh=Kli7bsKqs+eaBYyWTfWH9d84SaYxv5pRWLRnBCnNC4Q=; b=RDEcBDHv2gaRpqMtRz/up+MuFaZ0M5QCyS0M5tL84qa+kN9ly0WW34x6EWE2UthpqE mKAydVKrWCiulGxKocTRlBhjRbQwtugnEjROln5QoxnPgpRoSJo03jjqJlNCsJ/zltgI QMS5Pnl/6/FfIl/r/fmxYyhdv+Y/WKH+VdiWUb0RoZ0wVw5Kdi5zLWaYei6Yu8+a4Su9 KBCAYu4F7Jtmm6q2BN//SUlcF6mwWWzRkPsXITgc0KSzFl8HDncbwlCLg+UUzDXWWFkF SOnwEaYaqTajj2L7eNXlAfKKoDSz/k4KbcAxpU3PY4wjaFgVO3H1/CGEgpw+5fThSrB0 SJ/Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of bp@alien8.de designates 2a01:4f8:190:11c2::b:1457 as permitted sender) smtp.mailfrom=bp@alien8.de Authentication-Results: mx.google.com; spf=pass (google.com: domain of bp@alien8.de designates 2a01:4f8:190:11c2::b:1457 as permitted sender) smtp.mailfrom=bp@alien8.de Date: Thu, 25 Jan 2018 22:30:48 +0100 From: Borislav Petkov To: David Woodhouse , Tom Lendacky Cc: arjan@linux.intel.com, tglx@linutronix.de, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org, dave.hansen@intel.com, gnomes@lxorguk.ukuu.org.uk, ashok.raj@intel.com, mingo@kernel.org Subject: Re: [PATCH v5 3/7] x86/cpufeatures: Add AMD feature bits for Speculation Control Message-ID: <20180125213048.yd5cloxh2ttggeas@pd.tnic> References: <1516896855-7642-1-git-send-email-dwmw@amazon.co.uk> <1516896855-7642-4-git-send-email-dwmw@amazon.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1516896855-7642-4-git-send-email-dwmw@amazon.co.uk> User-Agent: NeoMutt/20170609 (1.8.3) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590555819438908618?= X-GMAIL-MSGID: =?utf-8?q?1590601563966015850?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: + Tom. On Thu, Jan 25, 2018 at 04:14:11PM +0000, David Woodhouse wrote: > AMD exposes the PRED_CMD/SPEC_CTRL MSRs slightly differently to Intel. > See http://lkml.kernel.org/r/2b3e25cc-286d-8bd0-aeaf-9ac4aae39de8@amd.com > > Signed-off-by: David Woodhouse > Reviewed-by: Greg Kroah-Hartman > --- > arch/x86/include/asm/cpufeatures.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 0a51070..ae3212f 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -269,6 +269,9 @@ > #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ > #define X86_FEATURE_IRPERF (13*32+ 1) /* Instructions Retired Count */ > #define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* Always save/restore FP error pointers */ > +#define X86_FEATURE_AMD_PRED_CMD (13*32+12) /* Prediction Command MSR (AMD) */ > +#define X86_FEATURE_AMD_SPEC_CTRL (13*32+14) /* Speculation Control MSR only (AMD) */ > +#define X86_FEATURE_AMD_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors (AMD) */ So this leaf is AMD-specific so you can drop the AMD strings above. Also, let's simplify this as those flags appear in /proc/cpuinfo: #define X86_FEATURE_IBPB (13*32+12) /* Indirect Branch Prediction Barrier: Prediction Command MSR */ #define X86_FEATURE_IBRS (13*32+14) /* Speculation Control MSR only */ #define X86_FEATURE_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors */ so that we have "ibpb", "ibrs" and "stibp" respectively. Thx. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.