[PATCH 3/3] drm/i915/bxt, glk: Avoid long atomic poll during CDCLK change

[Imre Deak <imre.deak@intel.com>]

There is no requirement for doing the PCODE request polling atomically,
so do that only for a short time switching to sleeping poll afterwards.
The specification requires a 150usec timeout for the change notification,
so let's use that for the atomic poll. Do the extra 2ms poll - needed as
a workaround on BXT/GLK - in sleeping mode.

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_cdclk.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 8d06a6f66f29..f94e14c8cd0a 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1377,7 +1377,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	 */
 	mutex_lock(&dev_priv->pcu_lock);
 	ret = snb_pcode_request(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
-				0x80000000, NULL, 2000, 0);
+				0x80000000, NULL, 150, 2);
 	mutex_unlock(&dev_priv->pcu_lock);
 
 	if (ret) {
@@ -1415,7 +1415,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
 	 * the next PCODE request based on BSpec.
 	 */
 	ret = snb_pcode_request(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
-				cdclk_state->voltage_level, NULL, 2000, 0);
+				cdclk_state->voltage_level, NULL, 150, 2);
 	mutex_unlock(&dev_priv->pcu_lock);
 
 	if (ret) {
-- 
2.13.2

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