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From: Andi Shyti <andi.shyti@samsung.com>
To: Andrzej Hajda <a.hajda@samsung.com>
Cc: Wolfram Sang <wsa@the-dreams.de>,
	Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>,
	Marek Szyprowski <m.szyprowski@samsung.com>,
	"open list:I2C SUBSYSTEM" <linux-i2c@vger.kernel.org>,
	"moderated list:ARM/SAMSUNG EXYNOS ARM ARCHITECTURES"
	<linux-samsung-soc@vger.kernel.org>
Subject: Re: [PATCH] i2c: exynos5: rework HSI2C_MASTER_ST_LOSE state handling
Date: Thu, 01 Feb 2018 16:51:23 +0900	[thread overview]
Message-ID: <20180201075123.GH7575@gangnam.samsung> (raw)
In-Reply-To: <20180126120950.9934-1-a.hajda@samsung.com>

Hi Andrzej,

On Fri, Jan 26, 2018 at 01:09:50PM +0100, Andrzej Hajda wrote:
> HSI2C_MASTER_ST_LOSE state is not documented properly, extensive tests
> show that hardware is usually able to recover from this state without
> interrupting the transfer. Moreover documentation says that
> such state can be caused by slave clock stretching, and should not be
> treated as an error during transaction. The only place it indicates
> an error is just before starting transaction. In such case bus recovery
> procedure should be performed - master should pulse SCL line nine times
> and then send STOP condition, it can be repeated until SDA goes high.
> The procedure can be performed using manual commands HSI2C_CMD_READ_DATA
> and HSI2C_CMD_SEND_STOP.
> 
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>

Thank you, looks good to me.

Please add:

Reviewed-by: Andi Shyti <andi.shyti@samsung.com>
Tested-by: Andi Shyti <andi.shyti@samsung.com>

Thanks,
Andi

  reply	other threads:[~2018-02-01  7:51 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20180126121001eucas1p2931738af133ad3e5bf1cd824058ba8d0@eucas1p2.samsung.com>
2018-01-26 12:09 ` [PATCH] i2c: exynos5: rework HSI2C_MASTER_ST_LOSE state handling Andrzej Hajda
2018-02-01  7:51   ` Andi Shyti [this message]
2018-02-12  8:04   ` Andrzej Hajda

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