* [PATCH v3] drm/i915/icl: remove port A/E lane sharing limitation.
@ 2018-02-06 6:08 Mahesh Kumar
2018-02-06 8:36 ` ✓ Fi.CI.BAT: success for drm/i915/icl: remove port A/E lane sharing limitation. (rev3) Patchwork
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Mahesh Kumar @ 2018-02-06 6:08 UTC (permalink / raw)
To: intel-gfx
Platforms before Gen11 were sharing lanes between port-A & port-E.
This limitation is no more there.
Changes since V1:
- optimize the code (Shashank/Jani)
- create helper function to get max lanes (ville)
Changes since V2:
- Include BIOS fail fix-up in same helper function (ville)
Changes since V3:
- remove confusing if/else (jani)
- group intel_encoder initialization
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 85 ++++++++++++++++++----------------------
1 file changed, 39 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cfcd9cb37d5d..60fe2ba4b29c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2842,39 +2842,45 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
return false;
}
+static int
+intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
+{
+ struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
+ enum port port = intel_dport->base.port;
+ int max_lanes = 4;
+
+ if (INTEL_GEN(dev_priv) >= 11)
+ return max_lanes;
+
+ if (port == PORT_A || port == PORT_E) {
+ if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
+ max_lanes = port == PORT_A ? 4 : 0;
+ else
+ /* Both A and E share 2 lanes */
+ max_lanes = 2;
+ }
+
+ /*
+ * Some BIOS might fail to set this bit on port A if eDP
+ * wasn't lit up at boot. Force this bit set when needed
+ * so we use the proper lane count for our calculations.
+ */
+ if (intel_ddi_a_force_4_lanes(intel_dport)) {
+ DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
+ intel_dport->saved_port_bits |= DDI_A_4_LANES;
+ max_lanes = 4;
+ }
+
+ return max_lanes;
+}
+
void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
{
struct intel_digital_port *intel_dig_port;
struct intel_encoder *intel_encoder;
struct drm_encoder *encoder;
bool init_hdmi, init_dp, init_lspcon = false;
- int max_lanes;
- if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
- switch (port) {
- case PORT_A:
- max_lanes = 4;
- break;
- case PORT_E:
- max_lanes = 0;
- break;
- default:
- max_lanes = 4;
- break;
- }
- } else {
- switch (port) {
- case PORT_A:
- max_lanes = 2;
- break;
- case PORT_E:
- max_lanes = 2;
- break;
- default:
- max_lanes = 4;
- break;
- }
- }
init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
dev_priv->vbt.ddi_port_info[port].supports_hdmi);
@@ -2920,10 +2926,17 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
intel_encoder->get_config = intel_ddi_get_config;
intel_encoder->suspend = intel_dp_encoder_suspend;
intel_encoder->get_power_domains = intel_ddi_get_power_domains;
+ intel_encoder->type = INTEL_OUTPUT_DDI;
+ intel_encoder->power_domain = intel_port_to_power_domain(port);
+ intel_encoder->port = port;
+ intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
+ intel_encoder->cloneable = 0;
intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
(DDI_BUF_PORT_REVERSAL |
DDI_A_4_LANES);
+ intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
+ intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
switch (port) {
case PORT_A:
@@ -2954,26 +2967,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
MISSING_CASE(port);
}
- /*
- * Some BIOS might fail to set this bit on port A if eDP
- * wasn't lit up at boot. Force this bit set when needed
- * so we use the proper lane count for our calculations.
- */
- if (intel_ddi_a_force_4_lanes(intel_dig_port)) {
- DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
- intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
- max_lanes = 4;
- }
-
- intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
- intel_dig_port->max_lanes = max_lanes;
-
- intel_encoder->type = INTEL_OUTPUT_DDI;
- intel_encoder->power_domain = intel_port_to_power_domain(port);
- intel_encoder->port = port;
- intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
- intel_encoder->cloneable = 0;
-
intel_infoframe_init(intel_dig_port);
if (init_dp) {
--
2.14.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/icl: remove port A/E lane sharing limitation. (rev3)
2018-02-06 6:08 [PATCH v3] drm/i915/icl: remove port A/E lane sharing limitation Mahesh Kumar
@ 2018-02-06 8:36 ` Patchwork
2018-02-06 9:51 ` ✓ Fi.CI.IGT: " Patchwork
2018-03-05 6:53 ` [PATCH v3] drm/i915/icl: remove port A/E lane sharing limitation Kumar, Mahesh
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2018-02-06 8:36 UTC (permalink / raw)
To: Mahesh Kumar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: remove port A/E lane sharing limitation. (rev3)
URL : https://patchwork.freedesktop.org/series/37325/
State : success
== Summary ==
Series 37325v3 drm/i915/icl: remove port A/E lane sharing limitation.
https://patchwork.freedesktop.org/api/1.0/series/37325/revisions/3/mbox/
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass -> FAIL (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:422s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:423s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:375s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:492s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:286s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:482s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:483s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:471s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:459s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:565s
fi-cnl-y3 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:580s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:417s
fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:293s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:512s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:390s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:400s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:412s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:448s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:415s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:459s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:497s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:453s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:500s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:592s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:436s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:509s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:527s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:492s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:479s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:414s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:431s
fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:402s
Blacklisted hosts:
fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:471s
89ac14dcb4d010748c1b54dba54885db1a8c13e3 drm-tip: 2018y-02m-05d-19h-08m-24s UTC integration manifest
64cc47684098 drm/i915/icl: remove port A/E lane sharing limitation.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7898/issues.html
_______________________________________________
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^ permalink raw reply [flat|nested] 5+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/icl: remove port A/E lane sharing limitation. (rev3)
2018-02-06 6:08 [PATCH v3] drm/i915/icl: remove port A/E lane sharing limitation Mahesh Kumar
2018-02-06 8:36 ` ✓ Fi.CI.BAT: success for drm/i915/icl: remove port A/E lane sharing limitation. (rev3) Patchwork
@ 2018-02-06 9:51 ` Patchwork
2018-03-05 6:53 ` [PATCH v3] drm/i915/icl: remove port A/E lane sharing limitation Kumar, Mahesh
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2018-02-06 9:51 UTC (permalink / raw)
To: Mahesh Kumar; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: remove port A/E lane sharing limitation. (rev3)
URL : https://patchwork.freedesktop.org/series/37325/
State : success
== Summary ==
Test gem_eio:
Subgroup in-flight-contexts:
pass -> DMESG-WARN (shard-snb) fdo#104058
Test perf:
Subgroup blocking:
pass -> FAIL (shard-hsw) fdo#102252
Test gem_exec_schedule:
Subgroup preempt-self-vebox:
fail -> PASS (shard-apl) fdo#102848
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> INCOMPLETE (shard-hsw) fdo#103375
Test kms_flip:
Subgroup wf_vblank-ts-check-interruptible:
fail -> PASS (shard-hsw) fdo#100368
Subgroup dpms-vs-vblank-race-interruptible:
pass -> FAIL (shard-hsw) fdo#103060
Test kms_sysfs_edid_timing:
warn -> PASS (shard-apl) fdo#100047
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102848 https://bugs.freedesktop.org/show_bug.cgi?id=102848
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
shard-apl total:3348 pass:1728 dwarn:1 dfail:0 fail:21 skip:1597 time:12494s
shard-hsw total:3423 pass:1745 dwarn:1 dfail:0 fail:13 skip:1662 time:11250s
shard-snb total:3442 pass:1349 dwarn:2 dfail:0 fail:10 skip:2081 time:6640s
Blacklisted hosts:
shard-kbl total:3442 pass:1894 dwarn:14 dfail:1 fail:22 skip:1511 time:9714s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7898/shards.html
_______________________________________________
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3] drm/i915/icl: remove port A/E lane sharing limitation.
2018-02-06 6:08 [PATCH v3] drm/i915/icl: remove port A/E lane sharing limitation Mahesh Kumar
2018-02-06 8:36 ` ✓ Fi.CI.BAT: success for drm/i915/icl: remove port A/E lane sharing limitation. (rev3) Patchwork
2018-02-06 9:51 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-03-05 6:53 ` Kumar, Mahesh
2018-03-05 10:58 ` Jani Nikula
2 siblings, 1 reply; 5+ messages in thread
From: Kumar, Mahesh @ 2018-03-05 6:53 UTC (permalink / raw)
To: intel-gfx
Please review.
thanks,
-Mahesh
On 2/6/2018 11:38 AM, Mahesh Kumar wrote:
> Platforms before Gen11 were sharing lanes between port-A & port-E.
> This limitation is no more there.
>
> Changes since V1:
> - optimize the code (Shashank/Jani)
> - create helper function to get max lanes (ville)
> Changes since V2:
> - Include BIOS fail fix-up in same helper function (ville)
> Changes since V3:
> - remove confusing if/else (jani)
> - group intel_encoder initialization
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 85 ++++++++++++++++++----------------------
> 1 file changed, 39 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index cfcd9cb37d5d..60fe2ba4b29c 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2842,39 +2842,45 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
> return false;
> }
>
> +static int
> +intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
> +{
> + struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
> + enum port port = intel_dport->base.port;
> + int max_lanes = 4;
> +
> + if (INTEL_GEN(dev_priv) >= 11)
> + return max_lanes;
> +
> + if (port == PORT_A || port == PORT_E) {
> + if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
> + max_lanes = port == PORT_A ? 4 : 0;
> + else
> + /* Both A and E share 2 lanes */
> + max_lanes = 2;
> + }
> +
> + /*
> + * Some BIOS might fail to set this bit on port A if eDP
> + * wasn't lit up at boot. Force this bit set when needed
> + * so we use the proper lane count for our calculations.
> + */
> + if (intel_ddi_a_force_4_lanes(intel_dport)) {
> + DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
> + intel_dport->saved_port_bits |= DDI_A_4_LANES;
> + max_lanes = 4;
> + }
> +
> + return max_lanes;
> +}
> +
> void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> {
> struct intel_digital_port *intel_dig_port;
> struct intel_encoder *intel_encoder;
> struct drm_encoder *encoder;
> bool init_hdmi, init_dp, init_lspcon = false;
> - int max_lanes;
>
> - if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
> - switch (port) {
> - case PORT_A:
> - max_lanes = 4;
> - break;
> - case PORT_E:
> - max_lanes = 0;
> - break;
> - default:
> - max_lanes = 4;
> - break;
> - }
> - } else {
> - switch (port) {
> - case PORT_A:
> - max_lanes = 2;
> - break;
> - case PORT_E:
> - max_lanes = 2;
> - break;
> - default:
> - max_lanes = 4;
> - break;
> - }
> - }
>
> init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
> dev_priv->vbt.ddi_port_info[port].supports_hdmi);
> @@ -2920,10 +2926,17 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> intel_encoder->get_config = intel_ddi_get_config;
> intel_encoder->suspend = intel_dp_encoder_suspend;
> intel_encoder->get_power_domains = intel_ddi_get_power_domains;
> + intel_encoder->type = INTEL_OUTPUT_DDI;
> + intel_encoder->power_domain = intel_port_to_power_domain(port);
> + intel_encoder->port = port;
> + intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
> + intel_encoder->cloneable = 0;
>
> intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
> (DDI_BUF_PORT_REVERSAL |
> DDI_A_4_LANES);
> + intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
> + intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
>
> switch (port) {
> case PORT_A:
> @@ -2954,26 +2967,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> MISSING_CASE(port);
> }
>
> - /*
> - * Some BIOS might fail to set this bit on port A if eDP
> - * wasn't lit up at boot. Force this bit set when needed
> - * so we use the proper lane count for our calculations.
> - */
> - if (intel_ddi_a_force_4_lanes(intel_dig_port)) {
> - DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
> - intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> - max_lanes = 4;
> - }
> -
> - intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
> - intel_dig_port->max_lanes = max_lanes;
> -
> - intel_encoder->type = INTEL_OUTPUT_DDI;
> - intel_encoder->power_domain = intel_port_to_power_domain(port);
> - intel_encoder->port = port;
> - intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
> - intel_encoder->cloneable = 0;
> -
> intel_infoframe_init(intel_dig_port);
>
> if (init_dp) {
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3] drm/i915/icl: remove port A/E lane sharing limitation.
2018-03-05 6:53 ` [PATCH v3] drm/i915/icl: remove port A/E lane sharing limitation Kumar, Mahesh
@ 2018-03-05 10:58 ` Jani Nikula
0 siblings, 0 replies; 5+ messages in thread
From: Jani Nikula @ 2018-03-05 10:58 UTC (permalink / raw)
To: Kumar, Mahesh, intel-gfx
On Mon, 05 Mar 2018, "Kumar, Mahesh" <mahesh1.kumar@intel.com> wrote:
> Please review.
Pushed to drm-intel-next-queued, thanks for the patch.
Personally, I would have split this into 2-3 patches: 1) code movement
to allow 2) abstraction of the function and 3) functional change of the
limit on icl. It would have been faster and easier to review, and easier
to figure out what went wrong in case a bisect ever lands on the commit.
BR,
Jani.
>
> thanks,
>
> -Mahesh
>
> On 2/6/2018 11:38 AM, Mahesh Kumar wrote:
>> Platforms before Gen11 were sharing lanes between port-A & port-E.
>> This limitation is no more there.
>>
>> Changes since V1:
>> - optimize the code (Shashank/Jani)
>> - create helper function to get max lanes (ville)
>> Changes since V2:
>> - Include BIOS fail fix-up in same helper function (ville)
>> Changes since V3:
>> - remove confusing if/else (jani)
>> - group intel_encoder initialization
>>
>> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
>> ---
>> drivers/gpu/drm/i915/intel_ddi.c | 85 ++++++++++++++++++----------------------
>> 1 file changed, 39 insertions(+), 46 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>> index cfcd9cb37d5d..60fe2ba4b29c 100644
>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>> @@ -2842,39 +2842,45 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport)
>> return false;
>> }
>>
>> +static int
>> +intel_ddi_max_lanes(struct intel_digital_port *intel_dport)
>> +{
>> + struct drm_i915_private *dev_priv = to_i915(intel_dport->base.base.dev);
>> + enum port port = intel_dport->base.port;
>> + int max_lanes = 4;
>> +
>> + if (INTEL_GEN(dev_priv) >= 11)
>> + return max_lanes;
>> +
>> + if (port == PORT_A || port == PORT_E) {
>> + if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
>> + max_lanes = port == PORT_A ? 4 : 0;
>> + else
>> + /* Both A and E share 2 lanes */
>> + max_lanes = 2;
>> + }
>> +
>> + /*
>> + * Some BIOS might fail to set this bit on port A if eDP
>> + * wasn't lit up at boot. Force this bit set when needed
>> + * so we use the proper lane count for our calculations.
>> + */
>> + if (intel_ddi_a_force_4_lanes(intel_dport)) {
>> + DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
>> + intel_dport->saved_port_bits |= DDI_A_4_LANES;
>> + max_lanes = 4;
>> + }
>> +
>> + return max_lanes;
>> +}
>> +
>> void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>> {
>> struct intel_digital_port *intel_dig_port;
>> struct intel_encoder *intel_encoder;
>> struct drm_encoder *encoder;
>> bool init_hdmi, init_dp, init_lspcon = false;
>> - int max_lanes;
>>
>> - if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
>> - switch (port) {
>> - case PORT_A:
>> - max_lanes = 4;
>> - break;
>> - case PORT_E:
>> - max_lanes = 0;
>> - break;
>> - default:
>> - max_lanes = 4;
>> - break;
>> - }
>> - } else {
>> - switch (port) {
>> - case PORT_A:
>> - max_lanes = 2;
>> - break;
>> - case PORT_E:
>> - max_lanes = 2;
>> - break;
>> - default:
>> - max_lanes = 4;
>> - break;
>> - }
>> - }
>>
>> init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
>> dev_priv->vbt.ddi_port_info[port].supports_hdmi);
>> @@ -2920,10 +2926,17 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>> intel_encoder->get_config = intel_ddi_get_config;
>> intel_encoder->suspend = intel_dp_encoder_suspend;
>> intel_encoder->get_power_domains = intel_ddi_get_power_domains;
>> + intel_encoder->type = INTEL_OUTPUT_DDI;
>> + intel_encoder->power_domain = intel_port_to_power_domain(port);
>> + intel_encoder->port = port;
>> + intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
>> + intel_encoder->cloneable = 0;
>>
>> intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
>> (DDI_BUF_PORT_REVERSAL |
>> DDI_A_4_LANES);
>> + intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
>> + intel_dig_port->max_lanes = intel_ddi_max_lanes(intel_dig_port);
>>
>> switch (port) {
>> case PORT_A:
>> @@ -2954,26 +2967,6 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
>> MISSING_CASE(port);
>> }
>>
>> - /*
>> - * Some BIOS might fail to set this bit on port A if eDP
>> - * wasn't lit up at boot. Force this bit set when needed
>> - * so we use the proper lane count for our calculations.
>> - */
>> - if (intel_ddi_a_force_4_lanes(intel_dig_port)) {
>> - DRM_DEBUG_KMS("Forcing DDI_A_4_LANES for port A\n");
>> - intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
>> - max_lanes = 4;
>> - }
>> -
>> - intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
>> - intel_dig_port->max_lanes = max_lanes;
>> -
>> - intel_encoder->type = INTEL_OUTPUT_DDI;
>> - intel_encoder->power_domain = intel_port_to_power_domain(port);
>> - intel_encoder->port = port;
>> - intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
>> - intel_encoder->cloneable = 0;
>> -
>> intel_infoframe_init(intel_dig_port);
>>
>> if (init_dp) {
>
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-03-05 10:57 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-02-06 6:08 [PATCH v3] drm/i915/icl: remove port A/E lane sharing limitation Mahesh Kumar
2018-02-06 8:36 ` ✓ Fi.CI.BAT: success for drm/i915/icl: remove port A/E lane sharing limitation. (rev3) Patchwork
2018-02-06 9:51 ` ✓ Fi.CI.IGT: " Patchwork
2018-03-05 6:53 ` [PATCH v3] drm/i915/icl: remove port A/E lane sharing limitation Kumar, Mahesh
2018-03-05 10:58 ` Jani Nikula
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