[PATCH 00/20] ICL GEM enabling (v2)

[PATCH 00/20] ICL GEM enabling (v2)

[Mika Kuoppala]

I have gathered the r-bs from previous series posted by Paulo,
picked few newer versions from list and rebased where had to.
Some patches have already landed so this is a bit thinner series.

I could not yet merge the "drm/i915/icl: Prepare for more rings"
as that needs "drm/i915/gvt: Do not use I915_NUM_ENGINES to iterate
over the mocs regs array" to land from gvt for not to break dinq.

If you have patches you think should be included in this series,
please let me know.

-Mika

Ceraolo Spurio, Daniele (1):
  drm/i915/icl: new context descriptor support

Daniele Ceraolo Spurio (1):
  drm/i915/icl: Gen11 forcewake support

Kelvin Gardiner (2):
  drm/i915/icl: Update subslice define for ICL 11
  drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection

Michel Thierry (2):
  drm/i915/icl: Add Indirect Context Offset for Gen11
  drm/i915/icl: Add reset control register changes

Oscar Mateo (6):
  drm/i915/icl: Correctly initialize the Gen11 engines
  drm/i915/icl: Check for fused-off VDBOX and VEBOX instances
  drm/i915/icl: Enable the extra video decode and enhancement boxes for
    Icelake 11
  drm/i915/icl: Split out the servicing of the Selector and Shared IIR
    registers
  drm/i915/icl: Handle RPS interrupts correctly for Gen11
  drm/i915/icl: Enable RC6 and RPS in Gen11

Paulo Zanoni (2):
  drm/i915/icl: Add the ICL PCI IDs
  drm/i915/icl: add icelake_init_clock_gating()

Thomas Daniel (1):
  drm/i915/icl: Enhanced execution list support

Tomasz Lis (1):
  drm/i915/icl: Add configuring MOCS in new Icelake engines

Tvrtko Ursulin (4):
  drm/i915/icl: Show interrupt registers in debugfs
  drm/i915/icl: Prepare for more rings
  drm/i915/icl: Interrupt handling
  drm/i915/icl: Ringbuffer interrupt handling

 drivers/gpu/drm/i915/i915_debugfs.c           |  92 ++++++++-
 drivers/gpu/drm/i915/i915_drv.c               |   2 +
 drivers/gpu/drm/i915/i915_drv.h               |   7 +
 drivers/gpu/drm/i915/i915_gem.h               |   2 +-
 drivers/gpu/drm/i915/i915_gem_context.c       |  11 +-
 drivers/gpu/drm/i915/i915_irq.c               | 274 +++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_pci.c               |   5 +-
 drivers/gpu/drm/i915/i915_reg.h               |  50 ++++-
 drivers/gpu/drm/i915/intel_breadcrumbs.c      |  20 +-
 drivers/gpu/drm/i915/intel_device_info.c      |  82 +++++++-
 drivers/gpu/drm/i915/intel_device_info.h      |   5 +-
 drivers/gpu/drm/i915/intel_drv.h              |   1 +
 drivers/gpu/drm/i915/intel_engine_cs.c        |  66 ++++++-
 drivers/gpu/drm/i915/intel_lrc.c              | 103 ++++++++--
 drivers/gpu/drm/i915/intel_lrc.h              |   3 +
 drivers/gpu/drm/i915/intel_lrc_reg.h          |   1 +
 drivers/gpu/drm/i915/intel_mocs.c             |   5 +-
 drivers/gpu/drm/i915/intel_pm.c               |  22 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.h       |  28 ++-
 drivers/gpu/drm/i915/intel_uncore.c           | 210 ++++++++++++++++++--
 drivers/gpu/drm/i915/intel_uncore.h           |  23 ++-
 drivers/gpu/drm/i915/selftests/intel_uncore.c |  31 ++-
 include/drm/i915_pciids.h                     |  12 ++
 23 files changed, 968 insertions(+), 87 deletions(-)

-- 
2.14.1

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[PATCH 01/20] drm/i915/icl: Add the ICL PCI IDs

[Mika Kuoppala]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

This is the current PCI ID list in our documentation.

Let's leave the _gt#_ part out for now since our current documentation
is not 100% clear and we don't need this info now anyway.

v2: Use the new ICL_11 naming (Kelvin Gardiner).
v3: Latest IDs as per BSpec (Oscar).
v4: Make it compile (Paulo).
v5: Remove comments (Lucas).
v6: Multile rebases (Paulo).
v7: Rebase (Mika)

Reviewed-by: Anuj Phogat <anuj.phogat@intel.com> (v1)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c |  1 +
 include/drm/i915_pciids.h       | 12 ++++++++++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4e7a10c89782..c94a76bef763 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -650,6 +650,7 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
 	INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
 	INTEL_CNL_IDS(&intel_cannonlake_info),
+	INTEL_ICL_11_IDS(&intel_icelake_11_info),
 	{0, 0, 0}
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 9e1fe6634424..4afcdb4492f1 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -430,4 +430,16 @@
 	INTEL_VGA_DEVICE(0x5A5C, info), \
 	INTEL_VGA_DEVICE(0x5A44, info)
 
+/* ICL */
+#define INTEL_ICL_11_IDS(info) \
+	INTEL_VGA_DEVICE(0x8A50, info), \
+	INTEL_VGA_DEVICE(0x8A51, info), \
+	INTEL_VGA_DEVICE(0x8A5C, info), \
+	INTEL_VGA_DEVICE(0x8A5D, info), \
+	INTEL_VGA_DEVICE(0x8A52, info), \
+	INTEL_VGA_DEVICE(0x8A5A, info), \
+	INTEL_VGA_DEVICE(0x8A5B, info), \
+	INTEL_VGA_DEVICE(0x8A71, info), \
+	INTEL_VGA_DEVICE(0x8A70, info)
+
 #endif /* _I915_PCIIDS_H */
-- 
2.14.1

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[PATCH 02/20] drm/i915/icl: add icelake_init_clock_gating()

[Mika Kuoppala]

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

For now it does nothing, except for avoiding a MISSING_CASE.

v2: Rebase.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b026b020d8b8..d88f107b0d50 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8493,6 +8493,11 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
 		   CNP_PWM_CGE_GATING_DISABLE);
 }
 
+static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
+{
+
+}
+
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
 {
 	u32 val;
@@ -9003,7 +9008,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-	if (IS_CANNONLAKE(dev_priv))
+	if (IS_ICELAKE(dev_priv))
+		dev_priv->display.init_clock_gating = icl_init_clock_gating;
+	else if (IS_CANNONLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
 	else if (IS_COFFEELAKE(dev_priv))
 		dev_priv->display.init_clock_gating = cfl_init_clock_gating;
-- 
2.14.1

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[PATCH 03/20] drm/i915/icl: Show interrupt registers in debugfs

[Mika Kuoppala]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

v2: Update for POR changes. (Daniele Ceraolo Spurio)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 82 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 81 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 960302668649..49d5bed87798 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -703,6 +703,64 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 				   i, I915_READ(GEN8_GT_IER(i)));
 		}
 
+		seq_printf(m, "PCU interrupt mask:\t%08x\n",
+			   I915_READ(GEN8_PCU_IMR));
+		seq_printf(m, "PCU interrupt identity:\t%08x\n",
+			   I915_READ(GEN8_PCU_IIR));
+		seq_printf(m, "PCU interrupt enable:\t%08x\n",
+			   I915_READ(GEN8_PCU_IER));
+	} else if (INTEL_GEN(dev_priv) >= 11) {
+		seq_printf(m, "Master Interrupt Control:  %08x\n",
+			   I915_READ(GEN11_GFX_MSTR_IRQ));
+
+		seq_printf(m, "Render/Copy Intr Enable:   %08x\n",
+			   I915_READ(GEN11_RENDER_COPY_INTR_ENABLE));
+		seq_printf(m, "VCS/VECS Intr Enable:      %08x\n",
+			   I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
+		seq_printf(m, "GUC/SG Intr Enable:\t   %08x\n",
+			   I915_READ(GEN11_GUC_SG_INTR_ENABLE));
+		seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
+			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE));
+		seq_printf(m, "Crypto Intr Enable:\t   %08x\n",
+			   I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE));
+		seq_printf(m, "GUnit/CSME Intr Enable:\t   %08x\n",
+			   I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE));
+
+		seq_printf(m, "Display Interrupt Control:\t%08x\n",
+			   I915_READ(GEN11_DISPLAY_INT_CTL));
+
+		for_each_pipe(dev_priv, pipe) {
+			if (!intel_display_power_is_enabled(dev_priv,
+						POWER_DOMAIN_PIPE(pipe))) {
+				seq_printf(m, "Pipe %c power disabled\n",
+					   pipe_name(pipe));
+				continue;
+			}
+			seq_printf(m, "Pipe %c IMR:\t%08x\n",
+				   pipe_name(pipe),
+				   I915_READ(GEN8_DE_PIPE_IMR(pipe)));
+			seq_printf(m, "Pipe %c IIR:\t%08x\n",
+				   pipe_name(pipe),
+				   I915_READ(GEN8_DE_PIPE_IIR(pipe)));
+			seq_printf(m, "Pipe %c IER:\t%08x\n",
+				   pipe_name(pipe),
+				   I915_READ(GEN8_DE_PIPE_IER(pipe)));
+		}
+
+		seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
+			   I915_READ(GEN8_DE_PORT_IMR));
+		seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
+			   I915_READ(GEN8_DE_PORT_IIR));
+		seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
+			   I915_READ(GEN8_DE_PORT_IER));
+
+		seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
+			   I915_READ(GEN8_DE_MISC_IMR));
+		seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
+			   I915_READ(GEN8_DE_MISC_IIR));
+		seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
+			   I915_READ(GEN8_DE_MISC_IER));
+
 		seq_printf(m, "PCU interrupt mask:\t%08x\n",
 			   I915_READ(GEN8_PCU_IMR));
 		seq_printf(m, "PCU interrupt identity:\t%08x\n",
@@ -846,13 +904,35 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
 			   I915_READ(GTIMR));
 	}
-	if (INTEL_GEN(dev_priv) >= 6) {
+
+	if (INTEL_GEN(dev_priv) >= 11) {
+		seq_printf(m, "RCS Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_RCS0_RSVD_INTR_MASK));
+		seq_printf(m, "BCS Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_BCS_RSVD_INTR_MASK));
+		seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
+		seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
+		seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_VECS0_VECS1_INTR_MASK));
+		seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_GUC_SG_INTR_MASK));
+		seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
+			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK));
+		seq_printf(m, "Crypto Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK));
+		seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_GUNIT_CSME_INTR_MASK));
+
+	} else if (INTEL_GEN(dev_priv) >= 6) {
 		for_each_engine(engine, dev_priv, id) {
 			seq_printf(m,
 				   "Graphics Interrupt mask (%s):	%08x\n",
 				   engine->name, I915_READ_IMR(engine));
 		}
 	}
+
 	intel_runtime_pm_put(dev_priv);
 
 	return 0;
-- 
2.14.1

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[PATCH 04/20] drm/i915/icl: Prepare for more rings

[Mika Kuoppala]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Gen11 will add more VCS and VECS rings so prepare the
infrastructure to support that.

Bspec: 7021

v2: Rebase.
v3: Rebase.
v4: Rebase.
v5: Rebase.
v6:
  - Update for POR changes. (Daniele Ceraolo Spurio)
  - Add provisional guc engine ids - to be checked and confirmed.
v7:
  - Rebased.
  - Added the new ring masks.
  - Added the new HW ids.
v8:
  - Introduce I915_MAX_VCS/VECS to avoid magic numbers (Michal)

v9: increase MAX_ENGINE_INSTANCE to 3

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h          | 3 +++
 drivers/gpu/drm/i915/i915_gem.h          | 2 +-
 drivers/gpu/drm/i915/i915_reg.h          | 5 ++++-
 drivers/gpu/drm/i915/intel_device_info.c | 3 +++
 drivers/gpu/drm/i915/intel_device_info.h | 4 +++-
 drivers/gpu/drm/i915/intel_ringbuffer.h  | 9 ++++++++-
 6 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3f8d824dc313..e7fead9eec21 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2732,6 +2732,9 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define BLT_RING	ENGINE_MASK(BCS)
 #define VEBOX_RING	ENGINE_MASK(VECS)
 #define BSD2_RING	ENGINE_MASK(VCS2)
+#define BSD3_RING	ENGINE_MASK(VCS3)
+#define BSD4_RING	ENGINE_MASK(VCS4)
+#define VEBOX2_RING	ENGINE_MASK(VECS2)
 #define ALL_ENGINES	(~0)
 
 #define HAS_ENGINE(dev_priv, id) \
diff --git a/drivers/gpu/drm/i915/i915_gem.h b/drivers/gpu/drm/i915/i915_gem.h
index e920dab7f1b8..1b61b7f8c2ec 100644
--- a/drivers/gpu/drm/i915/i915_gem.h
+++ b/drivers/gpu/drm/i915/i915_gem.h
@@ -54,6 +54,6 @@
 #define GEM_TRACE(...) do { } while (0)
 #endif
 
-#define I915_NUM_ENGINES 5
+#define I915_NUM_ENGINES 8
 
 #endif /* __I915_GEM_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f6afa5e5e7c1..5a499e1eddc3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -178,6 +178,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define BCS_HW		2
 #define VECS_HW		3
 #define VCS2_HW		4
+#define VCS3_HW		6
+#define VCS4_HW		7
+#define VECS2_HW	12
 
 /* Engine class */
 
@@ -188,7 +191,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define OTHER_CLASS		4
 #define MAX_ENGINE_CLASS	4
 
-#define MAX_ENGINE_INSTANCE    1
+#define MAX_ENGINE_INSTANCE    3
 
 /* PCI config space */
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 298f8996cc54..9352f34e75c4 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -489,6 +489,9 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 		info->num_scalers[PIPE_C] = 1;
 	}
 
+	BUILD_BUG_ON(I915_NUM_ENGINES >
+		     sizeof(intel_ring_mask_t) * BITS_PER_BYTE);
+
 	/*
 	 * Skylake and Broxton currently don't expose the topmost plane as its
 	 * use is exclusive with the legacy cursor and we only want to expose
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 71fdfb0451ef..4c6f83b2dd6a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -125,6 +125,8 @@ struct sseu_dev_info {
 	u8 has_eu_pg:1;
 };
 
+typedef u8 intel_ring_mask_t;
+
 struct intel_device_info {
 	u16 device_id;
 	u16 gen_mask;
@@ -132,7 +134,7 @@ struct intel_device_info {
 	u8 gen;
 	u8 gt; /* GT number, 0 if undefined */
 	u8 num_rings;
-	u8 ring_mask; /* Rings supported by the HW */
+	intel_ring_mask_t ring_mask; /* Rings supported by the HW */
 
 	enum intel_platform platform;
 	u32 platform_mask;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 51523ad049de..f743351c441f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -158,6 +158,9 @@ struct i915_ctx_workarounds {
 
 struct drm_i915_gem_request;
 
+#define I915_MAX_VCS	4
+#define I915_MAX_VECS	2
+
 /*
  * Engine IDs definitions.
  * Keep instances of the same type engine together.
@@ -167,8 +170,12 @@ enum intel_engine_id {
 	BCS,
 	VCS,
 	VCS2,
+	VCS3,
+	VCS4,
 #define _VCS(n) (VCS + (n))
-	VECS
+	VECS,
+	VECS2
+#define _VECS(n) (VECS + (n))
 };
 
 struct i915_priolist {
-- 
2.14.1

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[PATCH 05/20] drm/i915/icl: Interrupt handling

[Mika Kuoppala]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

v2: Rebase.

v3:
  * Remove DPF, it has been removed from SKL+.
  * Fix -internal rebase wrt. execlists interrupt handling.

v4: Rebase.

v5:
  * Updated for POR changes. (Daniele Ceraolo Spurio)
  * Merged with irq handling fixes by Daniele Ceraolo Spurio:
      * Simplify the code by using gen8_cs_irq_handler.
      * Fix interrupt handling for the upstream kernel.

v6:
  * Remove early bringup debug messages (Tvrtko)
  * Add NB about arbitrary spin wait timeout (Tvrtko)

v7 (from Paulo):
  * Don't try to write RO bits to registers.
  * Don't check for PCH types that don't exist. PCH interrupts are not
    here yet.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 210 ++++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_pm.c |   7 +-
 2 files changed, 216 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b886bd459acc..3a1de4e2a941 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -415,6 +415,9 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 	if (READ_ONCE(rps->interrupts_enabled))
 		return;
 
+	if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
+		return;
+
 	spin_lock_irq(&dev_priv->irq_lock);
 	WARN_ON_ONCE(rps->pm_iir);
 	WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
@@ -431,6 +434,9 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 	if (!READ_ONCE(rps->interrupts_enabled))
 		return;
 
+	if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
+		return;
+
 	spin_lock_irq(&dev_priv->irq_lock);
 	rps->interrupts_enabled = false;
 
@@ -2746,6 +2752,131 @@ static void __fini_wedge(struct wedge_me *w)
 	     (W)->i915;							\
 	     __fini_wedge((W)))
 
+static __always_inline void
+gen11_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
+{
+	gen8_cs_irq_handler(engine, iir, 0);
+}
+
+static irqreturn_t
+gen11_gt_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
+{
+	irqreturn_t ret = IRQ_NONE;
+	u16 irq[2][32];
+	u32 dw, ident;
+	unsigned long tmp;
+	unsigned int bank, bit, engine;
+	unsigned long wait_start, wait_end;
+
+	memset(irq, 0, sizeof(irq));
+
+	for (bank = 0; bank < 2; bank++) {
+		if (master_ctl & GEN11_GT_DW_IRQ(bank)) {
+			dw = I915_READ_FW(GEN11_GT_INTR_DW(bank));
+			if (!dw)
+				DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
+			tmp = dw;
+			for_each_set_bit(bit, &tmp, 32) {
+				I915_WRITE_FW(GEN11_IIR_REG_SELECTOR(bank), 1 << bit);
+				wait_start = local_clock() >> 10;
+				/* NB: Specs do not specify how long to spin wait.
+				 * Taking 100us as an educated guess */
+				wait_end = wait_start + 100;
+				do {
+					ident = I915_READ_FW(GEN11_INTR_IDENTITY_REG(bank));
+				} while (!(ident & GEN11_INTR_DATA_VALID) &&
+					 !time_after((unsigned long)local_clock() >> 10, wait_end));
+
+				if (!(ident & GEN11_INTR_DATA_VALID))
+					DRM_ERROR("INTR_IDENTITY_REG%u:%u timed out!\n",
+						  bank, bit);
+
+				irq[bank][bit] = ident & GEN11_INTR_ENGINE_MASK;
+				if (!irq[bank][bit])
+					DRM_ERROR("INTR_IDENTITY_REG%u:%u blank!\n",
+						  bank, bit);
+				I915_WRITE_FW(GEN11_INTR_IDENTITY_REG(bank), ident);
+			}
+			I915_WRITE_FW(GEN11_GT_INTR_DW(bank), dw);
+		}
+	}
+
+	if (irq[0][GEN11_RCS0]) {
+		gen11_cs_irq_handler(dev_priv->engine[RCS],
+				     irq[0][GEN11_RCS0]);
+		ret = IRQ_HANDLED;
+	}
+
+	if (irq[0][GEN11_BCS]) {
+		gen11_cs_irq_handler(dev_priv->engine[BCS],
+				     irq[0][GEN11_BCS]);
+		ret = IRQ_HANDLED;
+	}
+
+	for (engine = 0; engine < 4; engine++) {
+		if (irq[1][GEN11_VCS(engine)]) {
+			gen11_cs_irq_handler(dev_priv->engine[_VCS(engine)],
+					     irq[1][GEN11_VCS(engine)]);
+			ret = IRQ_HANDLED;
+		}
+	}
+
+	for (engine = 0; engine < 2; engine++) {
+		if (irq[1][GEN11_VECS(engine)]) {
+			gen11_cs_irq_handler(dev_priv->engine[_VECS(engine)],
+					     irq[1][GEN11_VECS(engine)]);
+			ret = IRQ_HANDLED;
+		}
+	}
+
+	if (irq[0][GEN11_GTPM] & dev_priv->pm_rps_events) {
+		ret = IRQ_HANDLED;
+		gen6_rps_irq_handler(dev_priv, tmp);
+	}
+
+	return ret;
+}
+
+static irqreturn_t gen11_irq_handler(int irq, void *arg)
+{
+	struct drm_device *dev = arg;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 master_ctl;
+	u32 disp_ctl;
+	irqreturn_t ret;
+
+	if (!intel_irqs_enabled(dev_priv))
+		return IRQ_NONE;
+
+	master_ctl = I915_READ_FW(GEN11_GFX_MSTR_IRQ);
+
+	master_ctl &= ~GEN11_MASTER_IRQ;
+	if (!master_ctl)
+		return IRQ_NONE;
+
+	/* Disable interrupts. */
+	I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, 0);
+
+	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
+	disable_rpm_wakeref_asserts(dev_priv);
+
+	/* Find, clear, then process each source of interrupt. */
+	ret = gen11_gt_irq_handler(dev_priv, master_ctl);
+
+	if (master_ctl & GEN11_DISPLAY_IRQ) {
+		disp_ctl = I915_READ_FW(GEN11_DISPLAY_INT_CTL);
+		ret |= gen8_de_irq_handler(dev_priv, disp_ctl);
+	}
+
+	/* Acknowledge and enable interrupts. */
+	I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
+	POSTING_READ_FW(GEN11_GFX_MSTR_IRQ);
+
+	enable_rpm_wakeref_asserts(dev_priv);
+
+	return ret;
+}
+
 /**
  * i915_reset_device - do process context error handling work
  * @dev_priv: i915 device private
@@ -3159,6 +3290,42 @@ static void gen8_irq_reset(struct drm_device *dev)
 		ibx_irq_reset(dev_priv);
 }
 
+static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
+{
+	/* Disable RCS, BCS, VCS and VECS class engines. */
+	I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0);
+	I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE,	  0);
+
+	/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
+	I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK,	~0);
+	I915_WRITE(GEN11_BCS_RSVD_INTR_MASK,	~0);
+	I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,	~0);
+	I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,	~0);
+	I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,	~0);
+}
+
+static void gen11_irq_reset(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int pipe;
+
+	I915_WRITE(GEN11_GFX_MSTR_IRQ, 0);
+	POSTING_READ(GEN11_GFX_MSTR_IRQ);
+
+	gen11_gt_irq_reset(dev_priv);
+
+	I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
+
+	for_each_pipe(dev_priv, pipe)
+		if (intel_display_power_is_enabled(dev_priv,
+						   POWER_DOMAIN_PIPE(pipe)))
+			GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
+
+	GEN3_IRQ_RESET(GEN8_DE_PORT_);
+	GEN3_IRQ_RESET(GEN8_DE_MISC_);
+	GEN3_IRQ_RESET(GEN8_PCU_);
+}
+
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 				     u8 pipe_mask)
 {
@@ -3656,6 +3823,41 @@ static int gen8_irq_postinstall(struct drm_device *dev)
 	return 0;
 }
 
+static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+	const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
+
+	BUILD_BUG_ON(irqs & 0xffff0000);
+
+	/* Enable RCS, BCS, VCS and VECS class interrupts. */
+	I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs);
+	I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE,	  irqs << 16 | irqs);
+
+	/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
+	I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK,	~(irqs << 16));
+	I915_WRITE(GEN11_BCS_RSVD_INTR_MASK,	~(irqs << 16));
+	I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,	~(irqs | irqs << 16));
+	I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,	~(irqs | irqs << 16));
+	I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,	~(irqs | irqs << 16));
+
+	dev_priv->pm_imr = 0xffffffff; /* TODO */
+}
+
+static int gen11_irq_postinstall(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	gen11_gt_irq_postinstall(dev_priv);
+	gen8_de_irq_postinstall(dev_priv);
+
+	I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
+
+	I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
+	POSTING_READ(GEN11_GFX_MSTR_IRQ);
+
+	return 0;
+}
+
 static int cherryview_irq_postinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -4104,6 +4306,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		dev->driver->enable_vblank = i965_enable_vblank;
 		dev->driver->disable_vblank = i965_disable_vblank;
 		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+	} else if (INTEL_GEN(dev_priv) >= 11) {
+		dev->driver->irq_handler = gen11_irq_handler;
+		dev->driver->irq_preinstall = gen11_irq_reset;
+		dev->driver->irq_postinstall = gen11_irq_postinstall;
+		dev->driver->irq_uninstall = gen11_irq_reset;
+		dev->driver->enable_vblank = gen8_enable_vblank;
+		dev->driver->disable_vblank = gen8_disable_vblank;
+		dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
 	} else if (INTEL_GEN(dev_priv) >= 8) {
 		dev->driver->irq_handler = gen8_irq_handler;
 		dev->driver->irq_preinstall = gen8_irq_reset;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d88f107b0d50..087f981461e7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8027,7 +8027,10 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 	dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
 	intel_disable_gt_powersave(dev_priv);
 
-	gen6_reset_rps_interrupts(dev_priv);
+	if (INTEL_GEN(dev_priv) < 11)
+		gen6_reset_rps_interrupts(dev_priv);
+	else
+		WARN_ON_ONCE(1);
 }
 
 static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
@@ -8140,6 +8143,8 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
 		cherryview_enable_rps(dev_priv);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
 		valleyview_enable_rps(dev_priv);
+	} else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) {
+		/* TODO */
 	} else if (INTEL_GEN(dev_priv) >= 9) {
 		gen9_enable_rps(dev_priv);
 	} else if (IS_BROADWELL(dev_priv)) {
-- 
2.14.1

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[PATCH 06/20] drm/i915/icl: Ringbuffer interrupt handling

[Mika Kuoppala]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Since it is not possible to mask individual engine instances
and they are all permanently unmasked we do not need to do
anything for engine interrupt management.

v2: Rebase.
v3: Remove gen 11 extra check in logical_render_ring_init.
v4: Rebase fixes.
v5: Rebase/refactor.
v6: Rebase.
v7: Rebase.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/intel_breadcrumbs.c | 20 ++++++++++++--------
 drivers/gpu/drm/i915/intel_lrc.c         | 11 +++++++++--
 drivers/gpu/drm/i915/intel_ringbuffer.h  |  5 +++++
 3 files changed, 26 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
index b955f7d7bd0f..69c727f97eb5 100644
--- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
+++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
@@ -167,18 +167,22 @@ static void irq_enable(struct intel_engine_cs *engine)
 	 */
 	set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
 
-	/* Caller disables interrupts */
-	spin_lock(&engine->i915->irq_lock);
-	engine->irq_enable(engine);
-	spin_unlock(&engine->i915->irq_lock);
+	if (engine->irq_enable) {
+		/* Caller disables interrupts */
+		spin_lock(&engine->i915->irq_lock);
+		engine->irq_enable(engine);
+		spin_unlock(&engine->i915->irq_lock);
+	}
 }
 
 static void irq_disable(struct intel_engine_cs *engine)
 {
-	/* Caller disables interrupts */
-	spin_lock(&engine->i915->irq_lock);
-	engine->irq_disable(engine);
-	spin_unlock(&engine->i915->irq_lock);
+	if (engine->irq_disable) {
+		/* Caller disables interrupts */
+		spin_lock(&engine->i915->irq_lock);
+		engine->irq_disable(engine);
+		spin_unlock(&engine->i915->irq_lock);
+	}
 }
 
 void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c2c8380a0121..da396c46b345 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1989,8 +1989,15 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
 
 	engine->set_default_submission = execlists_set_default_submission;
 
-	engine->irq_enable = gen8_logical_ring_enable_irq;
-	engine->irq_disable = gen8_logical_ring_disable_irq;
+	if (INTEL_GEN(engine->i915) < 11) {
+		engine->irq_enable = gen8_logical_ring_enable_irq;
+		engine->irq_disable = gen8_logical_ring_disable_irq;
+	} else {
+		/*
+		 * On Gen11 interrupts are permanently unmasked and there
+		 * are no per-engine instance mask bits.
+		 */
+	}
 	engine->emit_bb_start = gen8_emit_bb_start;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index f743351c441f..caed64bb02da 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -393,6 +393,11 @@ struct intel_engine_cs {
 
 	u32             irq_keep_mask; /* always keep these interrupts */
 	u32		irq_enable_mask; /* bitmask to enable ring interrupt */
+
+	/*
+	 * irq_enable and irq_disable do not have to be provided for
+	 * an engine. In other words they can be NULL.
+	 */
 	void		(*irq_enable)(struct intel_engine_cs *engine);
 	void		(*irq_disable)(struct intel_engine_cs *engine);
 
-- 
2.14.1

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[PATCH 07/20] drm/i915/icl: Correctly initialize the Gen11 engines

[Mika Kuoppala]

From: Oscar Mateo <oscar.mateo@intel.com>

Gen11 has up to 4 VCS and up to 2 VECS engines, this patch adds mmio
base definitions for all of them.

Bspec: 20944
Bspec: 7021

v2: Set the correct mmio_base in intel_engines_init_mmio; updating the
base mmio values any later would cause incorrect reads in
i915_gem_sanitize (Michel).

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h        |  6 +++++
 drivers/gpu/drm/i915/intel_engine_cs.c | 44 +++++++++++++++++++++++++++++++++-
 2 files changed, 49 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5a499e1eddc3..34feceb2e74e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2345,7 +2345,13 @@ enum i915_power_well_id {
 #define BSD_RING_BASE		0x04000
 #define GEN6_BSD_RING_BASE	0x12000
 #define GEN8_BSD2_RING_BASE	0x1c000
+#define GEN11_BSD_RING_BASE	0x1c0000
+#define GEN11_BSD2_RING_BASE	0x1c4000
+#define GEN11_BSD3_RING_BASE	0x1d0000
+#define GEN11_BSD4_RING_BASE	0x1d4000
 #define VEBOX_RING_BASE		0x1a000
+#define GEN11_VEBOX_RING_BASE		0x1c8000
+#define GEN11_VEBOX2_RING_BASE		0x1d8000
 #define BLT_RING_BASE		0x22000
 #define RING_TAIL(base)		_MMIO((base)+0x30)
 #define RING_HEAD(base)		_MMIO((base)+0x34)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index f3c5100d629e..e8a95628fc69 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -123,6 +123,22 @@ static const struct engine_info intel_engines[] = {
 		.mmio_base = GEN8_BSD2_RING_BASE,
 		.irq_shift = GEN8_VCS2_IRQ_SHIFT,
 	},
+	[VCS3] = {
+		.hw_id = VCS3_HW,
+		.uabi_id = I915_EXEC_BSD,
+		.class = VIDEO_DECODE_CLASS,
+		.instance = 2,
+		.mmio_base = GEN11_BSD3_RING_BASE,
+		.irq_shift = 0, /* not used */
+	},
+	[VCS4] = {
+		.hw_id = VCS4_HW,
+		.uabi_id = I915_EXEC_BSD,
+		.class = VIDEO_DECODE_CLASS,
+		.instance = 3,
+		.mmio_base = GEN11_BSD4_RING_BASE,
+		.irq_shift = 0, /* not used */
+	},
 	[VECS] = {
 		.hw_id = VECS_HW,
 		.uabi_id = I915_EXEC_VEBOX,
@@ -131,6 +147,14 @@ static const struct engine_info intel_engines[] = {
 		.mmio_base = VEBOX_RING_BASE,
 		.irq_shift = GEN8_VECS_IRQ_SHIFT,
 	},
+	[VECS2] = {
+		.hw_id = VECS2_HW,
+		.uabi_id = I915_EXEC_VEBOX,
+		.class = VIDEO_ENHANCEMENT_CLASS,
+		.instance = 1,
+		.mmio_base = GEN11_VEBOX2_RING_BASE,
+		.irq_shift = 0, /* not used */
+	},
 };
 
 /**
@@ -230,7 +254,25 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
 			 class_info->name, info->instance) >=
 		sizeof(engine->name));
 	engine->hw_id = engine->guc_id = info->hw_id;
-	engine->mmio_base = info->mmio_base;
+	if (INTEL_GEN(dev_priv) >= 11) {
+		switch (engine->id) {
+		case VCS:
+			engine->mmio_base = GEN11_BSD_RING_BASE;
+			break;
+		case VCS2:
+			engine->mmio_base = GEN11_BSD2_RING_BASE;
+			break;
+		case VECS:
+			engine->mmio_base = GEN11_VEBOX_RING_BASE;
+			break;
+		default:
+			/* take the original value for all other engines  */
+			engine->mmio_base = info->mmio_base;
+			break;
+		}
+	} else {
+		engine->mmio_base = info->mmio_base;
+	}
 	engine->irq_shift = info->irq_shift;
 	engine->class = info->class;
 	engine->instance = info->instance;
-- 
2.14.1

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[PATCH 08/20] drm/i915/icl: new context descriptor support

[Mika Kuoppala]

From: "Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com>

Starting from Gen11 the context descriptor format has been updated in
the HW. The hw_id field has been considerably reduced in size and engine
class and instance fields have been added.

There is a slight name clashing issue because the field that we call
hw_id is actually called SW Context ID in the specs for Gen11+.

With the current size of the hw_id field we can have a maximum of 2k
contexts at any time, but we could use the sw_counter field (which is sw
defined) to increase that because the HW requirement is that
engine_id + sw id + sw_counter is a unique number.
GuC uses a similar method to support more contexts but does its tracking
at lrc level. To avoid doing an implementation that will need to be
reworked once GuC support lands, defer it for now and mark it as TODO.

v2: rebased, add documentation, fix GEN11_ENGINE_INSTANCE_SHIFT
v3: rebased, bring back lost code from i915_gem_context.c
v4: make TODO comment more generic

Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |  1 +
 drivers/gpu/drm/i915/i915_gem_context.c | 11 +++++++++--
 drivers/gpu/drm/i915/i915_reg.h         |  4 ++++
 drivers/gpu/drm/i915/intel_lrc.c        | 28 +++++++++++++++++++++++++++-
 4 files changed, 41 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e7fead9eec21..9f8259e0ce6e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2093,6 +2093,7 @@ struct drm_i915_private {
 		 */
 		struct ida hw_ida;
 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
+#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
 	} contexts;
 
 	u32 fdi_rx_config;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 3d75f484f6e5..45b0b78aca3f 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -211,9 +211,15 @@ static void context_close(struct i915_gem_context *ctx)
 static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
 {
 	int ret;
+	unsigned int max;
+
+	if (INTEL_GEN(dev_priv) >= 11)
+		max = GEN11_MAX_CONTEXT_HW_ID;
+	else
+		max = MAX_CONTEXT_HW_ID;
 
 	ret = ida_simple_get(&dev_priv->contexts.hw_ida,
-			     0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
+			     0, max, GFP_KERNEL);
 	if (ret < 0) {
 		/* Contexts are only released when no longer active.
 		 * Flush any pending retires to hopefully release some
@@ -221,7 +227,7 @@ static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
 		 */
 		i915_gem_retire_requests(dev_priv);
 		ret = ida_simple_get(&dev_priv->contexts.hw_ida,
-				     0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
+				     0, max, GFP_KERNEL);
 		if (ret < 0)
 			return ret;
 	}
@@ -463,6 +469,7 @@ int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
 
 	/* Using the simple ida interface, the max is limited by sizeof(int) */
 	BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
+	BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > INT_MAX);
 	ida_init(&dev_priv->contexts.hw_ida);
 
 	/* lowest priority; idle task */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 34feceb2e74e..43cda512d7b4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3905,6 +3905,10 @@ enum {
 
 #define GEN8_CTX_ID_SHIFT 32
 #define GEN8_CTX_ID_WIDTH 21
+#define GEN11_SW_CTX_ID_SHIFT 37
+#define GEN11_SW_CTX_ID_WIDTH 11
+#define GEN11_ENGINE_CLASS_SHIFT 61
+#define GEN11_ENGINE_INSTANCE_SHIFT 48
 
 #define CHV_CLK_CTL1			_MMIO(0x101100)
 #define VLV_CLK_CTL2			_MMIO(0x101104)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index da396c46b345..b23eec6147a6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -187,6 +187,18 @@ static void execlists_init_reg_state(u32 *reg_state,
  *      bits 32-52:    ctx ID, a globally unique tag
  *      bits 53-54:    mbz, reserved for use by hardware
  *      bits 55-63:    group ID, currently unused and set to 0
+ *
+ * Starting from Gen11, the upper dword of the descriptor has a new format:
+ *
+ *      bits 32-36:    reserved
+ *      bits 37-47:    SW context ID
+ *      bits 48:53:    engine instance
+ *      bit 54:        mbz, reserved for use by hardware
+ *      bits 55-60:    SW counter
+ *      bits 61-63:    engine class
+ *
+ * engine info, SW context ID and SW counter need to form a unique number
+ * (Context ID) per lrc.
  */
 static void
 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
@@ -196,11 +208,25 @@ intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
 	u64 desc;
 
 	BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
+	BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (1<<GEN11_SW_CTX_ID_WIDTH));
 
 	desc = ctx->desc_template;				/* bits  0-11 */
 	desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
 								/* bits 12-31 */
-	desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT;		/* bits 32-52 */
+
+	if (INTEL_GEN(ctx->i915) >= 11) {
+		desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
+								/* bits 61-63 */
+
+		/* TODO: decide what to do with SW counter (bits 60-55) */
+
+		desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
+								/* bits 53-48 */
+		desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
+								/* bits 37-47 */
+	} else {
+		desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT;	/* bits 32-52 */
+	}
 
 	ce->lrc_desc = desc;
 }
-- 
2.14.1

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[PATCH 09/20] drm/i915/icl: Enhanced execution list support

[Mika Kuoppala]

From: Thomas Daniel <thomas.daniel@intel.com>

Enhanced Execlists is an upgraded version of execlists which supports
up to 8 ports. The lrcs to be submitted are written to a submit queue
(the ExecLists Submission Queue - ELSQ), which is then loaded on the
HW. When writing to the ELSP register, the lrcs are written cyclically
in the queue from position 0 to position 7. Alternatively, it is
possible to write directly in the individual positions of the queue
using the ELSQC registers. To be able to re-use all the existing code
we're using the latter method and we're currently limiting ourself to
only using 2 elements.

v2: Rebase.
v3: Switch from !IS_GEN11 to GEN < 11 (Daniele Ceraolo Spurio).
v4: Use the elsq registers instead of elsp. (Daniele Ceraolo Spurio)
v5: Reword commit, rename regs to be closer to specs, turn off
    preemption (Daniele), reuse engine->execlists.elsp (Chris)
v6: use has_logical_ring_elsq to differentiate the new paths
v7: add preemption support, rename els to submit_reg (Chris)
v8: save the ctrl register inside the execlists struct, drop CSB
    handling updates (superseded by preempt_complete_status) (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Thomas Daniel <thomas.daniel@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_drv.h          |  2 ++
 drivers/gpu/drm/i915/i915_pci.c          |  3 +-
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 drivers/gpu/drm/i915/intel_lrc.c         | 60 ++++++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_lrc.h         |  3 ++
 drivers/gpu/drm/i915/intel_ringbuffer.h  | 12 +++++--
 6 files changed, 63 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9f8259e0ce6e..65e674668b2e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2758,6 +2758,8 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
 		((dev_priv)->info.has_logical_ring_contexts)
+#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
+		((dev_priv)->info.has_logical_ring_elsq)
 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
 		((dev_priv)->info.has_logical_ring_preemption)
 
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index c94a76bef763..8c72a2bd315e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -583,7 +583,8 @@ static const struct intel_device_info intel_cannonlake_info = {
 	GEN10_FEATURES, \
 	.gen = 11, \
 	.ddb_size = 2048, \
-	.has_csr = 0
+	.has_csr = 0, \
+	.has_logical_ring_elsq = 1
 
 static const struct intel_device_info intel_icelake_11_info = {
 	GEN11_FEATURES,
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4c6f83b2dd6a..9fd2af470c90 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -96,6 +96,7 @@ enum intel_platform {
 	func(has_l3_dpf); \
 	func(has_llc); \
 	func(has_logical_ring_contexts); \
+	func(has_logical_ring_elsq); \
 	func(has_logical_ring_preemption); \
 	func(has_overlay); \
 	func(has_pooled_eu); \
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index b23eec6147a6..ad79f4d9dbe9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -399,18 +399,30 @@ static u64 execlists_update_context(struct drm_i915_gem_request *rq)
 	return ce->lrc_desc;
 }
 
-static inline void elsp_write(u64 desc, u32 __iomem *elsp)
+static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)
 {
-	writel(upper_32_bits(desc), elsp);
-	writel(lower_32_bits(desc), elsp);
+	if (execlists->ctrl_reg) {
+		writel(lower_32_bits(desc), execlists->submit_reg + port * 2);
+		writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1);
+	} else {
+		writel(upper_32_bits(desc), execlists->submit_reg);
+		writel(lower_32_bits(desc), execlists->submit_reg);
+	}
 }
 
 static void execlists_submit_ports(struct intel_engine_cs *engine)
 {
-	struct execlist_port *port = engine->execlists.port;
+	struct intel_engine_execlists *execlists = &engine->execlists;
+	struct execlist_port *port = execlists->port;
 	unsigned int n;
 
-	for (n = execlists_num_ports(&engine->execlists); n--; ) {
+	/*
+	 * ELSQ note: the submit queue is not cleared after being submitted
+	 * to the HW so we need to make sure we always clean it up. This is
+	 * currently ensured by the fact that we always write the same number
+	 * of elsq entries, keep this in mind before changing the loop below.
+	 */
+	for (n = execlists_num_ports(execlists); n--; ) {
 		struct drm_i915_gem_request *rq;
 		unsigned int count;
 		u64 desc;
@@ -433,9 +445,14 @@ static void execlists_submit_ports(struct intel_engine_cs *engine)
 			desc = 0;
 		}
 
-		elsp_write(desc, engine->execlists.elsp);
+		write_desc(execlists, desc, n);
 	}
-	execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK);
+
+	/* we need to manually load the submit queue */
+	if (execlists->ctrl_reg)
+		writel(EL_CTRL_LOAD, execlists->ctrl_reg);
+
+	execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
 }
 
 static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
@@ -469,11 +486,12 @@ static void port_assign(struct execlist_port *port,
 
 static void inject_preempt_context(struct intel_engine_cs *engine)
 {
+	struct intel_engine_execlists *execlists = &engine->execlists;
 	struct intel_context *ce =
 		&engine->i915->preempt_context->engine[engine->id];
 	unsigned int n;
 
-	GEM_BUG_ON(engine->execlists.preempt_complete_status !=
+	GEM_BUG_ON(execlists->preempt_complete_status !=
 		   upper_32_bits(ce->lrc_desc));
 	GEM_BUG_ON(!IS_ALIGNED(ce->ring->size, WA_TAIL_BYTES));
 
@@ -489,11 +507,16 @@ static void inject_preempt_context(struct intel_engine_cs *engine)
 				      CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT));
 
 	GEM_TRACE("%s\n", engine->name);
-	for (n = execlists_num_ports(&engine->execlists); --n; )
-		elsp_write(0, engine->execlists.elsp);
+	for (n = execlists_num_ports(execlists); --n; )
+		write_desc(execlists, 0, n);
+
+	write_desc(execlists, ce->lrc_desc, n);
+
+	/* we need to manually load the submit queue */
+	if (execlists->ctrl_reg)
+		writel(EL_CTRL_LOAD, execlists->ctrl_reg);
 
-	elsp_write(ce->lrc_desc, engine->execlists.elsp);
-	execlists_clear_active(&engine->execlists, EXECLISTS_ACTIVE_HWACK);
+	execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
 }
 
 static void execlists_dequeue(struct intel_engine_cs *engine)
@@ -2075,8 +2098,15 @@ static int logical_ring_init(struct intel_engine_cs *engine)
 	if (ret)
 		goto error;
 
-	engine->execlists.elsp =
-		engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
+	if (HAS_LOGICAL_RING_ELSQ(engine->i915)) {
+		engine->execlists.submit_reg = engine->i915->regs +
+			i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine));
+		engine->execlists.ctrl_reg = engine->i915->regs +
+			i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine));
+	} else {
+		engine->execlists.submit_reg = engine->i915->regs +
+			i915_mmio_reg_offset(RING_ELSP(engine));
+	}
 
 	engine->execlists.preempt_complete_status = ~0u;
 	if (engine->i915->preempt_context)
@@ -2345,7 +2375,7 @@ populate_lr_context(struct i915_gem_context *ctx,
 	if (!engine->default_state)
 		regs[CTX_CONTEXT_CONTROL + 1] |=
 			_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
-	if (ctx == ctx->i915->preempt_context)
+	if (ctx == ctx->i915->preempt_context && INTEL_GEN(engine->i915) < 11)
 		regs[CTX_CONTEXT_CONTROL + 1] |=
 			_MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
 					   CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT);
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 636ced41225d..59d7b86012e9 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -42,6 +42,9 @@
 #define RING_CONTEXT_STATUS_BUF_LO(engine, i)	_MMIO((engine)->mmio_base + 0x370 + (i) * 8)
 #define RING_CONTEXT_STATUS_BUF_HI(engine, i)	_MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
 #define RING_CONTEXT_STATUS_PTR(engine)		_MMIO((engine)->mmio_base + 0x3a0)
+#define RING_EXECLIST_SQ_CONTENTS(engine)	_MMIO((engine)->mmio_base + 0x510)
+#define RING_EXECLIST_CONTROL(engine)		_MMIO((engine)->mmio_base + 0x550)
+#define	  EL_CTRL_LOAD				(1 << 0)
 
 /* The docs specify that the write pointer wraps around after 5h, "After status
  * is written out to the last available status QW at offset 5h, this pointer
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index caed64bb02da..e56e0f95a723 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -207,9 +207,17 @@ struct intel_engine_execlists {
 	bool no_priolist;
 
 	/**
-	 * @elsp: the ExecList Submission Port register
+	 * @submit_reg: gen-specific execlist submission register
+	 * set to the ExecList Submission Port (elsp) register pre-Gen11 and to
+	 * the ExecList Submission Queue Contents register array for Gen11+
 	 */
-	u32 __iomem *elsp;
+	u32 __iomem *submit_reg;
+
+	/**
+	 * @ctrl_reg: the enhanced execlists control register, used to load the
+	 * submit queue on the HW and to request preemptions to idle
+	 */
+	u32 __iomem *ctrl_reg;
 
 	/**
 	 * @port: execlist port states
-- 
2.14.1

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[PATCH 10/20] drm/i915/icl: Add Indirect Context Offset for Gen11

[Mika Kuoppala]

From: Michel Thierry <michel.thierry@intel.com>

v2: rebased to intel_lr_indirect_ctx_offset
v3: rebase, move define to intel_lrc_reg.h

BSpec: 11740
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c     | 4 ++++
 drivers/gpu/drm/i915/intel_lrc_reg.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ad79f4d9dbe9..3cf3f1c93a60 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2216,6 +2216,10 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
 	default:
 		MISSING_CASE(INTEL_GEN(engine->i915));
 		/* fall through */
+	case 11:
+		indirect_ctx_offset =
+			GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
+		break;
 	case 10:
 		indirect_ctx_offset =
 			GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
diff --git a/drivers/gpu/drm/i915/intel_lrc_reg.h b/drivers/gpu/drm/i915/intel_lrc_reg.h
index a53336e2fc97..169a2239d6c7 100644
--- a/drivers/gpu/drm/i915/intel_lrc_reg.h
+++ b/drivers/gpu/drm/i915/intel_lrc_reg.h
@@ -63,5 +63,6 @@
 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x17
 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x26
 #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x19
+#define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x1A
 
 #endif /* _INTEL_LRC_REG_H_ */
-- 
2.14.1

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[PATCH 11/20] drm/i915/icl: Gen11 forcewake support

[Mika Kuoppala]

From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

The main difference with previous GENs is that starting from Gen11
each VCS and VECS engine has its own power well, which only exist
if the related engine exists in the HW.
The fallback forcewake request workaround is only needed on gen9
according to the HSDES WA entry (1604254524), so we can go back to using
the simpler fw_domains_get/put functions.

BSpec: 18331

v2: fix fwtable, use array to test shadow tables, create new
    accessors to avoid check on every access (Tvrtko)
v3 (from Paulo): Rebase.
v4:
  - Range 09400-097FF should be FORCEWAKE_ALL (Daniele)
  - Use the BIT macro for forcewake domains (Daniele)
  - Add a comment about the range ordering (Oscar)
  - Updated commit message (Oscar)
v5: Rebased
v6: Use I915_MAX_VCS/VECS (Michal)
v7: translate FORCEWAKE_ALL to available domains
v8: rebase, add clarification on fallback ack in commit message.
v9: fix rebase issue, change check in fw_domains_init from IS_GEN11
    to GEN >= 11
v10: Generate is_genX_shadowed with a macro (Daniele)
     Include gen11_fw_ranges in the selftest (Michel)
v11: Simplify FORCEWAKE_ALL, new line between NEEDS_FORCEWAKEs (Tvrtko)

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Acked-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h               |   4 +
 drivers/gpu/drm/i915/intel_uncore.c           | 157 ++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_uncore.h           |  23 +++-
 drivers/gpu/drm/i915/selftests/intel_uncore.c |  31 +++--
 4 files changed, 189 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 43cda512d7b4..b6cd725ff0b7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7989,9 +7989,13 @@ enum {
 #define   VLV_GTLC_PW_RENDER_STATUS_MASK	(1 << 7)
 #define  FORCEWAKE_MT				_MMIO(0xa188) /* multi-threaded */
 #define  FORCEWAKE_MEDIA_GEN9			_MMIO(0xa270)
+#define  FORCEWAKE_MEDIA_VDBOX_GEN11(n)		_MMIO(0xa540 + (n) * 4)
+#define  FORCEWAKE_MEDIA_VEBOX_GEN11(n)		_MMIO(0xa560 + (n) * 4)
 #define  FORCEWAKE_RENDER_GEN9			_MMIO(0xa278)
 #define  FORCEWAKE_BLITTER_GEN9			_MMIO(0xa188)
 #define  FORCEWAKE_ACK_MEDIA_GEN9		_MMIO(0x0D88)
+#define  FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n)	_MMIO(0x0D50 + (n) * 4)
+#define  FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n)	_MMIO(0x0D70 + (n) * 4)
 #define  FORCEWAKE_ACK_RENDER_GEN9		_MMIO(0x0D84)
 #define  FORCEWAKE_ACK_BLITTER_GEN9		_MMIO(0x130044)
 #define   FORCEWAKE_KERNEL			BIT(0)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 5ae9a62712ca..4df7c2ef8576 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -37,6 +37,12 @@ static const char * const forcewake_domain_names[] = {
 	"render",
 	"blitter",
 	"media",
+	"vdbox0",
+	"vdbox1",
+	"vdbox2",
+	"vdbox3",
+	"vebox0",
+	"vebox1",
 };
 
 const char *
@@ -774,6 +780,9 @@ void assert_forcewakes_active(struct drm_i915_private *dev_priv,
 /* We give fast paths for the really cool registers */
 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 
+#define GEN11_NEEDS_FORCE_WAKE(reg) \
+	((reg) < 0x40000 || ((reg) >= 0x1c0000 && (reg) < 0x1dc000))
+
 #define __gen6_reg_read_fw_domains(offset) \
 ({ \
 	enum forcewake_domains __fwd; \
@@ -826,6 +835,14 @@ find_fw_domain(struct drm_i915_private *dev_priv, u32 offset)
 	if (!entry)
 		return 0;
 
+	/*
+	 * The list of FW domains depends on the SKU in gen11+ so we
+	 * can't determine it statically. We use FORCEWAKE_ALL and
+	 * translate it here to the list of available domains.
+	 */
+	if (entry->domains == FORCEWAKE_ALL)
+		return dev_priv->uncore.fw_domains;
+
 	WARN(entry->domains & ~dev_priv->uncore.fw_domains,
 	     "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n",
 	     entry->domains & ~dev_priv->uncore.fw_domains, offset);
@@ -860,6 +877,14 @@ static const struct intel_forcewake_range __vlv_fw_ranges[] = {
 	__fwd; \
 })
 
+#define __gen11_fwtable_reg_read_fw_domains(offset) \
+({ \
+	enum forcewake_domains __fwd = 0; \
+	if (GEN11_NEEDS_FORCE_WAKE((offset))) \
+		__fwd = find_fw_domain(dev_priv, offset); \
+	__fwd; \
+})
+
 /* *Must* be sorted by offset! See intel_shadow_table_check(). */
 static const i915_reg_t gen8_shadowed_regs[] = {
 	RING_TAIL(RENDER_RING_BASE),	/* 0x2000 (base) */
@@ -871,6 +896,20 @@ static const i915_reg_t gen8_shadowed_regs[] = {
 	/* TODO: Other registers are not yet used */
 };
 
+static const i915_reg_t gen11_shadowed_regs[] = {
+	RING_TAIL(RENDER_RING_BASE),		/* 0x2000 (base) */
+	GEN6_RPNSWREQ,				/* 0xA008 */
+	GEN6_RC_VIDEO_FREQ,			/* 0xA00C */
+	RING_TAIL(BLT_RING_BASE),		/* 0x22000 (base) */
+	RING_TAIL(GEN11_BSD_RING_BASE),		/* 0x1C0000 (base) */
+	RING_TAIL(GEN11_BSD2_RING_BASE),	/* 0x1C4000 (base) */
+	RING_TAIL(GEN11_VEBOX_RING_BASE),	/* 0x1C8000 (base) */
+	RING_TAIL(GEN11_BSD3_RING_BASE),	/* 0x1D0000 (base) */
+	RING_TAIL(GEN11_BSD4_RING_BASE),	/* 0x1D4000 (base) */
+	RING_TAIL(GEN11_VEBOX2_RING_BASE),	/* 0x1D8000 (base) */
+	/* TODO: Other registers are not yet used */
+};
+
 static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
 {
 	u32 offset = i915_mmio_reg_offset(*reg);
@@ -883,14 +922,17 @@ static int mmio_reg_cmp(u32 key, const i915_reg_t *reg)
 		return 0;
 }
 
-static bool is_gen8_shadowed(u32 offset)
-{
-	const i915_reg_t *regs = gen8_shadowed_regs;
-
-	return BSEARCH(offset, regs, ARRAY_SIZE(gen8_shadowed_regs),
-		       mmio_reg_cmp);
+#define __is_genX_shadowed(x) \
+static bool is_gen##x##_shadowed(u32 offset) \
+{ \
+	const i915_reg_t *regs = gen##x##_shadowed_regs; \
+	return BSEARCH(offset, regs, ARRAY_SIZE(gen##x##_shadowed_regs), \
+		       mmio_reg_cmp); \
 }
 
+__is_genX_shadowed(8)
+__is_genX_shadowed(11)
+
 #define __gen8_reg_write_fw_domains(offset) \
 ({ \
 	enum forcewake_domains __fwd; \
@@ -929,6 +971,14 @@ static const struct intel_forcewake_range __chv_fw_ranges[] = {
 	__fwd; \
 })
 
+#define __gen11_fwtable_reg_write_fw_domains(offset) \
+({ \
+	enum forcewake_domains __fwd = 0; \
+	if (GEN11_NEEDS_FORCE_WAKE((offset)) && !is_gen11_shadowed(offset)) \
+		__fwd = find_fw_domain(dev_priv, offset); \
+	__fwd; \
+})
+
 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 static const struct intel_forcewake_range __gen9_fw_ranges[] = {
 	GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
@@ -965,6 +1015,40 @@ static const struct intel_forcewake_range __gen9_fw_ranges[] = {
 	GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
 };
 
+/* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
+static const struct intel_forcewake_range __gen11_fw_ranges[] = {
+	GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */
+	GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0x8500, 0x8bff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_ALL),
+	GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0xb480, 0xdfff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0xe900, 0x243ff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER),
+	GEN_FW_RANGE(0x24800, 0x3ffff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x40000, 0x1bffff, 0),
+	GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0),
+	GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1),
+	GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0),
+	GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_BLITTER),
+	GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2),
+	GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3),
+	GEN_FW_RANGE(0x1d8000, 0x1dbfff, FORCEWAKE_MEDIA_VEBOX1)
+};
+
 static void
 ilk_dummy_write(struct drm_i915_private *dev_priv)
 {
@@ -1095,7 +1179,12 @@ func##_read##x(struct drm_i915_private *dev_priv, i915_reg_t reg, bool trace) {
 }
 #define __gen6_read(x) __gen_read(gen6, x)
 #define __fwtable_read(x) __gen_read(fwtable, x)
+#define __gen11_fwtable_read(x) __gen_read(gen11_fwtable, x)
 
+__gen11_fwtable_read(8)
+__gen11_fwtable_read(16)
+__gen11_fwtable_read(32)
+__gen11_fwtable_read(64)
 __fwtable_read(8)
 __fwtable_read(16)
 __fwtable_read(32)
@@ -1105,6 +1194,7 @@ __gen6_read(16)
 __gen6_read(32)
 __gen6_read(64)
 
+#undef __gen11_fwtable_read
 #undef __fwtable_read
 #undef __gen6_read
 #undef GEN6_READ_FOOTER
@@ -1181,7 +1271,11 @@ func##_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, boo
 }
 #define __gen8_write(x) __gen_write(gen8, x)
 #define __fwtable_write(x) __gen_write(fwtable, x)
+#define __gen11_fwtable_write(x) __gen_write(gen11_fwtable, x)
 
+__gen11_fwtable_write(8)
+__gen11_fwtable_write(16)
+__gen11_fwtable_write(32)
 __fwtable_write(8)
 __fwtable_write(16)
 __fwtable_write(32)
@@ -1192,6 +1286,7 @@ __gen6_write(8)
 __gen6_write(16)
 __gen6_write(32)
 
+#undef __gen11_fwtable_write
 #undef __fwtable_write
 #undef __gen8_write
 #undef __gen6_write
@@ -1240,6 +1335,13 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
 	BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER));
 	BUILD_BUG_ON(FORCEWAKE_BLITTER != (1 << FW_DOMAIN_ID_BLITTER));
 	BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA));
+	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));
+	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));
+	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2));
+	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3));
+	BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0));
+	BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1));
+
 
 	d->mask = BIT(domain_id);
 
@@ -1267,7 +1369,34 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
 		dev_priv->uncore.fw_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
 	}
 
-	if (INTEL_GEN(dev_priv) >= 9) {
+	if (INTEL_GEN(dev_priv) >= 11) {
+		int i;
+
+		dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
+		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
+		fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
+			       FORCEWAKE_RENDER_GEN9,
+			       FORCEWAKE_ACK_RENDER_GEN9);
+		fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
+			       FORCEWAKE_BLITTER_GEN9,
+			       FORCEWAKE_ACK_BLITTER_GEN9);
+		for (i = 0; i < I915_MAX_VCS; i++) {
+			if (!HAS_ENGINE(dev_priv, _VCS(i)))
+				continue;
+
+			fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA_VDBOX0 + i,
+				       FORCEWAKE_MEDIA_VDBOX_GEN11(i),
+				       FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i));
+		}
+		for (i = 0; i < I915_MAX_VECS; i++) {
+			if (!HAS_ENGINE(dev_priv, _VECS(i)))
+				continue;
+
+			fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA_VEBOX0 + i,
+				       FORCEWAKE_MEDIA_VEBOX_GEN11(i),
+				       FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
+		}
+	} else if (IS_GEN9(dev_priv) || IS_GEN10(dev_priv)) {
 		dev_priv->uncore.funcs.force_wake_get =
 			fw_domains_get_with_fallback;
 		dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
@@ -1422,10 +1551,14 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
 			ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen8);
 			ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6);
 		}
-	} else {
+	} else if (IS_GEN(dev_priv, 9, 10)) {
 		ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
 		ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable);
 		ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable);
+	} else {
+		ASSIGN_FW_DOMAINS_TABLE(__gen11_fw_ranges);
+		ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen11_fwtable);
+		ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen11_fwtable);
 	}
 
 	iosf_mbi_register_pmic_bus_access_notifier(
@@ -1994,7 +2127,9 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv,
 	u32 offset = i915_mmio_reg_offset(reg);
 	enum forcewake_domains fw_domains;
 
-	if (HAS_FWTABLE(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
+		fw_domains = __gen11_fwtable_reg_read_fw_domains(offset);
+	} else if (HAS_FWTABLE(dev_priv)) {
 		fw_domains = __fwtable_reg_read_fw_domains(offset);
 	} else if (INTEL_GEN(dev_priv) >= 6) {
 		fw_domains = __gen6_reg_read_fw_domains(offset);
@@ -2015,7 +2150,9 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv,
 	u32 offset = i915_mmio_reg_offset(reg);
 	enum forcewake_domains fw_domains;
 
-	if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) {
+	if (INTEL_GEN(dev_priv) >= 11) {
+		fw_domains = __gen11_fwtable_reg_write_fw_domains(offset);
+	} else if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) {
 		fw_domains = __fwtable_reg_write_fw_domains(offset);
 	} else if (IS_GEN8(dev_priv)) {
 		fw_domains = __gen8_reg_write_fw_domains(offset);
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index bed019ef000f..703da58d7dcd 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -37,17 +37,28 @@ enum forcewake_domain_id {
 	FW_DOMAIN_ID_RENDER = 0,
 	FW_DOMAIN_ID_BLITTER,
 	FW_DOMAIN_ID_MEDIA,
+	FW_DOMAIN_ID_MEDIA_VDBOX0,
+	FW_DOMAIN_ID_MEDIA_VDBOX1,
+	FW_DOMAIN_ID_MEDIA_VDBOX2,
+	FW_DOMAIN_ID_MEDIA_VDBOX3,
+	FW_DOMAIN_ID_MEDIA_VEBOX0,
+	FW_DOMAIN_ID_MEDIA_VEBOX1,
 
 	FW_DOMAIN_ID_COUNT
 };
 
 enum forcewake_domains {
-	FORCEWAKE_RENDER = BIT(FW_DOMAIN_ID_RENDER),
-	FORCEWAKE_BLITTER = BIT(FW_DOMAIN_ID_BLITTER),
-	FORCEWAKE_MEDIA	= BIT(FW_DOMAIN_ID_MEDIA),
-	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
-			 FORCEWAKE_BLITTER |
-			 FORCEWAKE_MEDIA)
+	FORCEWAKE_RENDER	= BIT(FW_DOMAIN_ID_RENDER),
+	FORCEWAKE_BLITTER	= BIT(FW_DOMAIN_ID_BLITTER),
+	FORCEWAKE_MEDIA		= BIT(FW_DOMAIN_ID_MEDIA),
+	FORCEWAKE_MEDIA_VDBOX0	= BIT(FW_DOMAIN_ID_MEDIA_VDBOX0),
+	FORCEWAKE_MEDIA_VDBOX1	= BIT(FW_DOMAIN_ID_MEDIA_VDBOX1),
+	FORCEWAKE_MEDIA_VDBOX2	= BIT(FW_DOMAIN_ID_MEDIA_VDBOX2),
+	FORCEWAKE_MEDIA_VDBOX3	= BIT(FW_DOMAIN_ID_MEDIA_VDBOX3),
+	FORCEWAKE_MEDIA_VEBOX0	= BIT(FW_DOMAIN_ID_MEDIA_VEBOX0),
+	FORCEWAKE_MEDIA_VEBOX1	= BIT(FW_DOMAIN_ID_MEDIA_VEBOX1),
+
+	FORCEWAKE_ALL = BIT(FW_DOMAIN_ID_COUNT) - 1
 };
 
 struct intel_uncore_funcs {
diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c
index 2f6367643171..f76f2597df5c 100644
--- a/drivers/gpu/drm/i915/selftests/intel_uncore.c
+++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c
@@ -61,20 +61,30 @@ static int intel_fw_table_check(const struct intel_forcewake_range *ranges,
 
 static int intel_shadow_table_check(void)
 {
-	const i915_reg_t *reg = gen8_shadowed_regs;
-	unsigned int i;
+	struct {
+		const i915_reg_t *regs;
+		unsigned int size;
+	} reg_lists[] = {
+		{ gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
+		{ gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
+	};
+	const i915_reg_t *reg;
+	unsigned int i, j;
 	s32 prev;
 
-	for (i = 0, prev = -1; i < ARRAY_SIZE(gen8_shadowed_regs); i++, reg++) {
-		u32 offset = i915_mmio_reg_offset(*reg);
+	for (j = 0; j < ARRAY_SIZE(reg_lists); ++j) {
+		reg = reg_lists[j].regs;
+		for (i = 0, prev = -1; i < reg_lists[j].size; i++, reg++) {
+			u32 offset = i915_mmio_reg_offset(*reg);
 
-		if (prev >= (s32)offset) {
-			pr_err("%s: entry[%d]:(%x) is before previous (%x)\n",
-			       __func__, i, offset, prev);
-			return -EINVAL;
-		}
+			if (prev >= (s32)offset) {
+				pr_err("%s: entry[%d]:(%x) is before previous (%x)\n",
+				       __func__, i, offset, prev);
+				return -EINVAL;
+			}
 
-		prev = offset;
+			prev = offset;
+		}
 	}
 
 	return 0;
@@ -90,6 +100,7 @@ int intel_uncore_mock_selftests(void)
 		{ __vlv_fw_ranges, ARRAY_SIZE(__vlv_fw_ranges), false },
 		{ __chv_fw_ranges, ARRAY_SIZE(__chv_fw_ranges), false },
 		{ __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
+		{ __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
 	};
 	int err, i;
 
-- 
2.14.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 12/20] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Mika Kuoppala]

From: Oscar Mateo <oscar.mateo@intel.com>

In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the
Video Enhancement engines (aka VEBOX, aka VECS) could be fused off. Also,
each VDBOX and VEBOX has its own power well, which only exist if the related
engine exists in the HW.

Unfortunately, we have a Catch-22 situation going on: we need to read an
MMIO register with the fuse info, but we cannot fully enable MMIO until
we read it (since we need the real engines to initialize the forcewake
domains). We workaround this problem by reading the fuse after the MMIO
is partially ready, but before we initialize forcewake.

Bspec: 20680

v2: We were shifting incorrectly for vebox disable (Vinay)

v3: Assert mmio is ready and warn if we have attempted to initialize
    forcewake for fused-off engines (Paulo)

v4:
  - Use INTEL_GEN in new code (Tvrtko)
  - Shorter local variable (Tvrtko, Michal)
  - Keep "if (!...) continue" style (Tvrtko)
  - No unnecessary BUG_ON (Tvrtko)
  - WARN_ON and cleanup if wrong mask (Tvrtko, Michal)
  - Use I915_READ_FW (Michal)
  - Use I915_MAX_VCS/VECS macros (Michal)

v5: Rebased by Rodrigo fixing conflicts on top of:
    commit 33def1ff7b0 ("drm/i915: Simplify intel_engines_init")

v6: Fix v5. Remove info->num_rings. (by Oscar)

v7: Rebase (Rodrigo).

v8:
  - s/intel_device_info_fused_off_engines/intel_device_info_init_mmio (Chris)
  - Make vdbox_disable & vebox_disable local variables (Chris)

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c          |  2 ++
 drivers/gpu/drm/i915/i915_drv.h          |  1 +
 drivers/gpu/drm/i915/i915_reg.h          |  5 +++
 drivers/gpu/drm/i915/intel_device_info.c | 54 ++++++++++++++++++++++++++++++++
 4 files changed, 62 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9380c9f69b0f..43b2f620bca7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1033,6 +1033,8 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 	if (ret < 0)
 		goto err_bridge;
 
+	intel_device_info_init_mmio(dev_priv);
+
 	intel_uncore_init(dev_priv);
 
 	intel_uc_init_mmio(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 65e674668b2e..ba16c2025364 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3438,6 +3438,7 @@ void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
 
+void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);
 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
 				       struct sg_table *pages);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b6cd725ff0b7..2b8d3a13dd27 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2860,6 +2860,11 @@ enum i915_power_well_id {
 #define GEN10_EU_DISABLE3		_MMIO(0x9140)
 #define   GEN10_EU_DIS_SS_MASK		0xff
 
+#define GEN11_GT_VEBOX_VDBOX_DISABLE	_MMIO(0x9140)
+#define GEN11_GT_VDBOX_DISABLE_MASK	0xff
+#define GEN11_GT_VEBOX_DISABLE_SHIFT	16
+#define GEN11_GT_VEBOX_DISABLE_MASK	(0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 9352f34e75c4..7c8779faf162 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -595,3 +595,57 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps,
 {
 	drm_printf(p, "scheduler: %x\n", caps->scheduler);
 }
+
+/*
+ * Determine which engines are fused off in our particular hardware.
+ *
+ * This function needs to be called after the MMIO has been setup (as we need
+ * to read registers) but before uncore init (because the powerwell for the
+ * fused off engines doesn't exist, so we cannot initialize forcewake for them)
+ */
+void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
+{
+	struct intel_device_info *info = mkwrite_device_info(dev_priv);
+	u8 vdbox_disable, vebox_disable;
+	u32 media_fuse;
+	int i;
+
+	if (INTEL_GEN(dev_priv) < 11)
+		return;
+
+	GEM_BUG_ON(!dev_priv->regs);
+
+	media_fuse = I915_READ_FW(GEN11_GT_VEBOX_VDBOX_DISABLE);
+
+	vdbox_disable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
+	vebox_disable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
+			GEN11_GT_VEBOX_DISABLE_SHIFT;
+
+	DRM_DEBUG_DRIVER("vdbox disable: %04x\n", vdbox_disable);
+	for (i = 0; i < I915_MAX_VCS; i++) {
+		if (!HAS_ENGINE(dev_priv, _VCS(i)))
+			continue;
+
+		if (!(BIT(i) & vdbox_disable))
+			continue;
+
+		info->ring_mask &= ~ENGINE_MASK(_VCS(i));
+		WARN_ON(dev_priv->uncore.fw_domains &
+			BIT(FW_DOMAIN_ID_MEDIA_VDBOX0 + i));
+		DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
+	}
+
+	DRM_DEBUG_DRIVER("vebox disable: %04x\n", vebox_disable);
+	for (i = 0; i < I915_MAX_VECS; i++) {
+		if (!HAS_ENGINE(dev_priv, _VECS(i)))
+			continue;
+
+		if (!(BIT(i) & vebox_disable))
+			continue;
+
+		info->ring_mask &= ~ENGINE_MASK(_VECS(i));
+		WARN_ON(dev_priv->uncore.fw_domains &
+			BIT(FW_DOMAIN_ID_MEDIA_VEBOX0 + i));
+		DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
+	}
+}
-- 
2.14.1

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[PATCH 13/20] drm/i915/icl: Enable the extra video decode and enhancement boxes for Icelake 11

[Mika Kuoppala]

From: Oscar Mateo <oscar.mateo@intel.com>

Icelake 11 has one vebox and two vdboxes (0 and 2).

Bspec: 21140

v2: Split out in two (Daniele)

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8c72a2bd315e..508f17e956e4 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -591,6 +591,7 @@ static const struct intel_device_info intel_icelake_11_info = {
 	.platform = INTEL_ICELAKE,
 	.is_alpha_support = 1,
 	.has_resource_streamer = 0,
+	.ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
 };
 
 /*
-- 
2.14.1

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[PATCH 14/20] drm/i915/icl: Update subslice define for ICL 11

[Mika Kuoppala]

From: Kelvin Gardiner <kelvin.gardiner@intel.com>

ICL 11 has a greater number of maximum subslices. This patch
reflects this.

v2: GEN11 updates to MCR_SELECTOR (Oscar)
v3: Copypasta error in the new defines (Lionel)

Bspec: 21139
BSpec: 21108

Signed-off-by: Kelvin Gardiner <kelvin.gardiner@intel.com>
Reviewed-by: Oscar Mateo <oscar.mateo@intel.com> (v1)
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> (v1)
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         |  4 ++++
 drivers/gpu/drm/i915/intel_engine_cs.c  | 22 ++++++++++++++++++----
 drivers/gpu/drm/i915/intel_ringbuffer.h |  2 +-
 3 files changed, 23 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2b8d3a13dd27..915f11469bc1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2473,6 +2473,10 @@ enum i915_power_well_id {
 #define   GEN8_MCR_SLICE_MASK		GEN8_MCR_SLICE(3)
 #define   GEN8_MCR_SUBSLICE(subslice)	(((subslice) & 3) << 24)
 #define   GEN8_MCR_SUBSLICE_MASK	GEN8_MCR_SUBSLICE(3)
+#define   GEN11_MCR_SLICE(slice)	(((slice) & 0xf) << 27)
+#define   GEN11_MCR_SLICE_MASK		GEN11_MCR_SLICE(0xf)
+#define   GEN11_MCR_SUBSLICE(subslice)	(((subslice) & 0x7) << 24)
+#define   GEN11_MCR_SUBSLICE_MASK	GEN11_MCR_SUBSLICE(0x7)
 #define RING_IPEIR(base)	_MMIO((base)+0x64)
 #define RING_IPEHR(base)	_MMIO((base)+0x68)
 /*
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index e8a95628fc69..56d3befa1567 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -778,10 +778,24 @@ static inline uint32_t
 read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 		  int subslice, i915_reg_t reg)
 {
+	uint32_t mcr_slice_subslice_mask;
+	uint32_t mcr_slice_subslice_select;
 	uint32_t mcr;
 	uint32_t ret;
 	enum forcewake_domains fw_domains;
 
+	if (INTEL_GEN(dev_priv) >= 11) {
+		mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK |
+					  GEN11_MCR_SUBSLICE_MASK;
+		mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) |
+					    GEN11_MCR_SUBSLICE(subslice);
+	} else {
+		mcr_slice_subslice_mask = GEN8_MCR_SLICE_MASK |
+					  GEN8_MCR_SUBSLICE_MASK;
+		mcr_slice_subslice_select = GEN8_MCR_SLICE(slice) |
+					    GEN8_MCR_SUBSLICE(subslice);
+	}
+
 	fw_domains = intel_uncore_forcewake_for_reg(dev_priv, reg,
 						    FW_REG_READ);
 	fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
@@ -796,14 +810,14 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice,
 	 * The HW expects the slice and sublice selectors to be reset to 0
 	 * after reading out the registers.
 	 */
-	WARN_ON_ONCE(mcr & (GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK));
-	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
-	mcr |= GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
+	WARN_ON_ONCE(mcr & mcr_slice_subslice_mask);
+	mcr &= ~mcr_slice_subslice_mask;
+	mcr |= mcr_slice_subslice_select;
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	ret = I915_READ_FW(reg);
 
-	mcr &= ~(GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK);
+	mcr &= ~mcr_slice_subslice_mask;
 	I915_WRITE_FW(GEN8_MCR_SELECTOR, mcr);
 
 	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index e56e0f95a723..9b32c69d9c17 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -82,7 +82,7 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a)
 }
 
 #define I915_MAX_SLICES	3
-#define I915_MAX_SUBSLICES 3
+#define I915_MAX_SUBSLICES 8
 
 #define instdone_slice_mask(dev_priv__) \
 	(INTEL_GEN(dev_priv__) == 7 ? \
-- 
2.14.1

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[PATCH 15/20] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection

[Mika Kuoppala]

From: Kelvin Gardiner <kelvin.gardiner@intel.com>

This patch adds support to detect ICL, slice, subslice and EU fuse
settings.

Add addresses for ICL 11 slice, subslice and EU fuses registers.
These register addresses are the same as previous platforms but the
format and / or the meaning of the information is different. Therefore
Gen11 defines for these registers are added.

Bspec: 9731
Bspec: 20643
Bspec: 20673

Signed-off-by: Kelvin Gardiner <kelvin.gardiner@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          |  9 +++++++++
 drivers/gpu/drm/i915/intel_device_info.c | 25 ++++++++++++++++++++++++-
 2 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 915f11469bc1..96417c1b3751 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2869,6 +2869,15 @@ enum i915_power_well_id {
 #define GEN11_GT_VEBOX_DISABLE_SHIFT	16
 #define GEN11_GT_VEBOX_DISABLE_MASK	(0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
 
+#define GEN11_EU_DISABLE _MMIO(0x9134)
+#define GEN11_EU_DIS_MASK 0xFF
+
+#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
+#define GEN11_GT_S_ENA_MASK 0xFF
+
+#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
+#define GEN11_GT_SS_DIS_MASK 0xFF
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 7c8779faf162..80af8a24c48e 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -120,6 +120,27 @@ void intel_device_info_dump(const struct intel_device_info *info,
 	intel_device_info_dump_flags(info, p);
 }
 
+static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
+{
+	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
+	int eu_max = 8;
+	u32 eu_disable;
+
+	sseu->slice_mask = I915_READ(GEN11_GT_SLICE_ENABLE) &
+				GEN11_GT_S_ENA_MASK;
+	sseu->subslice_mask = ~(I915_READ(GEN11_GT_SUBSLICE_DISABLE) &
+				GEN11_GT_SS_DIS_MASK);
+	eu_disable = I915_READ(GEN11_EU_DISABLE) & GEN11_GT_S_ENA_MASK;
+
+	sseu->eu_per_subslice = eu_max - hweight32(eu_disable);
+	sseu->eu_total = sseu->eu_per_subslice * hweight32(sseu->subslice_mask);
+
+	/* ICL has no power gating restrictions. */
+	sseu->has_slice_pg = 1;
+	sseu->has_subslice_pg = 1;
+	sseu->has_eu_pg = 1;
+}
+
 static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
 {
 	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
@@ -583,8 +604,10 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
 		broadwell_sseu_info_init(dev_priv);
 	else if (INTEL_GEN(dev_priv) == 9)
 		gen9_sseu_info_init(dev_priv);
-	else if (INTEL_GEN(dev_priv) >= 10)
+	else if (INTEL_GEN(dev_priv) == 10)
 		gen10_sseu_info_init(dev_priv);
+	else if (INTEL_INFO(dev_priv)->gen >= 11)
+		gen11_sseu_info_init(dev_priv);
 
 	/* Initialize command stream timestamp frequency */
 	info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
-- 
2.14.1

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[PATCH 16/20] drm/i915/icl: Add reset control register changes

[Mika Kuoppala]

From: Michel Thierry <michel.thierry@intel.com>

The bits used to reset the different engines/domains have changed in
GEN11, this patch maps the reset engine mask bits with the new bits
in the reset control register.

v2: Use shift-left instead of BIT macro to match the file style (Paulo).
v3: Reuse gen8_reset_engines (Daniele).
v4: Do not call intel_uncore_forcewake_reset after reset, we may be
using the forcewake to read protected registers elsewhere and those
results may be clobbered by the concurrent dropping of forcewake.

bspec: 19212
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Acked-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h     | 11 ++++++++
 drivers/gpu/drm/i915/intel_uncore.c | 53 +++++++++++++++++++++++++++++++++++--
 2 files changed, 62 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 96417c1b3751..38824a6e5d05 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -304,6 +304,17 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define  GEN6_GRDOM_VECS		(1 << 4)
 #define  GEN9_GRDOM_GUC			(1 << 5)
 #define  GEN8_GRDOM_MEDIA2		(1 << 7)
+/* GEN11 changed all bit defs except for FULL & RENDER */
+#define  GEN11_GRDOM_FULL		GEN6_GRDOM_FULL
+#define  GEN11_GRDOM_RENDER		GEN6_GRDOM_RENDER
+#define  GEN11_GRDOM_BLT		(1 << 2)
+#define  GEN11_GRDOM_GUC		(1 << 3)
+#define  GEN11_GRDOM_MEDIA		(1 << 5)
+#define  GEN11_GRDOM_MEDIA2		(1 << 6)
+#define  GEN11_GRDOM_MEDIA3		(1 << 7)
+#define  GEN11_GRDOM_MEDIA4		(1 << 8)
+#define  GEN11_GRDOM_VECS		(1 << 13)
+#define  GEN11_GRDOM_VECS2		(1 << 14)
 
 #define RING_PP_DIR_BASE(engine)	_MMIO((engine)->mmio_base+0x228)
 #define RING_PP_DIR_BASE_READ(engine)	_MMIO((engine)->mmio_base+0x518)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 4df7c2ef8576..6d206159f6f5 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1853,6 +1853,50 @@ static int gen6_reset_engines(struct drm_i915_private *dev_priv,
 	return gen6_hw_domain_reset(dev_priv, hw_mask);
 }
 
+/**
+ * gen11_reset_engines - reset individual engines
+ * @dev_priv: i915 device
+ * @engine_mask: mask of intel_ring_flag() engines or ALL_ENGINES for full reset
+ *
+ * This function will reset the individual engines that are set in engine_mask.
+ * If you provide ALL_ENGINES as mask, full global domain reset will be issued.
+ *
+ * Note: It is responsibility of the caller to handle the difference between
+ * asking full domain reset versus reset for all available individual engines.
+ *
+ * Returns 0 on success, nonzero on error.
+ */
+static int gen11_reset_engines(struct drm_i915_private *dev_priv,
+			       unsigned engine_mask)
+{
+	struct intel_engine_cs *engine;
+	const u32 hw_engine_mask[I915_NUM_ENGINES] = {
+		[RCS] = GEN11_GRDOM_RENDER,
+		[BCS] = GEN11_GRDOM_BLT,
+		[VCS] = GEN11_GRDOM_MEDIA,
+		[VCS2] = GEN11_GRDOM_MEDIA2,
+		[VCS3] = GEN11_GRDOM_MEDIA3,
+		[VCS4] = GEN11_GRDOM_MEDIA4,
+		[VECS] = GEN11_GRDOM_VECS,
+		[VECS2] = GEN11_GRDOM_VECS2,
+	};
+	u32 hw_mask;
+
+	BUILD_BUG_ON(VECS2 + 1 != I915_NUM_ENGINES);
+
+	if (engine_mask == ALL_ENGINES) {
+		hw_mask = GEN11_GRDOM_FULL;
+	} else {
+		unsigned int tmp;
+
+		hw_mask = 0;
+		for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
+			hw_mask |= hw_engine_mask[engine->id];
+	}
+
+	return gen6_hw_domain_reset(dev_priv, hw_mask);
+}
+
 /**
  * __intel_wait_for_register_fw - wait until register matches expected state
  * @dev_priv: the i915 device
@@ -2000,7 +2044,10 @@ static int gen8_reset_engines(struct drm_i915_private *dev_priv,
 		if (gen8_reset_engine_start(engine))
 			goto not_ready;
 
-	return gen6_reset_engines(dev_priv, engine_mask);
+	if (INTEL_GEN(dev_priv) >= 11)
+		return gen11_reset_engines(dev_priv, engine_mask);
+	else
+		return gen6_reset_engines(dev_priv, engine_mask);
 
 not_ready:
 	for_each_engine_masked(engine, dev_priv, engine_mask, tmp)
@@ -2085,12 +2132,14 @@ bool intel_has_reset_engine(struct drm_i915_private *dev_priv)
 
 int intel_reset_guc(struct drm_i915_private *dev_priv)
 {
+	u32 guc_domain = INTEL_GEN(dev_priv) >= 11 ? GEN11_GRDOM_GUC :
+						     GEN9_GRDOM_GUC;
 	int ret;
 
 	GEM_BUG_ON(!HAS_GUC(dev_priv));
 
 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
-	ret = gen6_hw_domain_reset(dev_priv, GEN9_GRDOM_GUC);
+	ret = gen6_hw_domain_reset(dev_priv, guc_domain);
 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 
 	return ret;
-- 
2.14.1

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[PATCH 17/20] drm/i915/icl: Add configuring MOCS in new Icelake engines

[Mika Kuoppala]

From: Tomasz Lis <tomasz.lis@intel.com>

In Icelake, there are more engines on which Memory Object Control States need
to be configured. Besides adding Icelake under Skylake config, the patch makes
sure MOCS register addresses for the new engines are properly defined.

Additional patch might be need later, in case the specification will
propose different MOCS config values for Icelake than in previous gens.

v2: Restricted comments to gen11, updated description, renamed defines.

v3: Used proper engine indexes for gen11.

v4: Removed engines which are not part of gen11.0

v5: Style fixes (proposed by mwajdeczko)

BSpec: 19405
BSpec: 21140
Cc: Oscar Mateo Lozano <oscar.mateo@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 2 ++
 drivers/gpu/drm/i915/intel_mocs.c | 5 ++++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 38824a6e5d05..ffe48e530b8d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9785,6 +9785,8 @@ enum skl_power_gate {
 #define GEN9_MFX1_MOCS(i)	_MMIO(0xca00 + (i) * 4)	/* Media 1 MOCS registers */
 #define GEN9_VEBOX_MOCS(i)	_MMIO(0xcb00 + (i) * 4)	/* Video MOCS registers */
 #define GEN9_BLT_MOCS(i)	_MMIO(0xcc00 + (i) * 4)	/* Blitter MOCS registers */
+/* Media decoder 2 MOCS registers */
+#define GEN11_MFX2_MOCS(i)	_MMIO(0x10000 + (i) * 4)
 
 /* gamt regs */
 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index abb7a8c1e340..2d75666537b3 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -178,7 +178,8 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
 {
 	bool result = false;
 
-	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
+	    IS_ICELAKE(dev_priv)) {
 		table->size  = ARRAY_SIZE(skylake_mocs_table);
 		table->table = skylake_mocs_table;
 		result = true;
@@ -217,6 +218,8 @@ static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index)
 		return GEN9_VEBOX_MOCS(index);
 	case VCS2:
 		return GEN9_MFX1_MOCS(index);
+	case VCS3:
+		return GEN11_MFX2_MOCS(index);
 	default:
 		MISSING_CASE(engine_id);
 		return INVALID_MMIO_REG;
-- 
2.14.1

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[PATCH 18/20] drm/i915/icl: Split out the servicing of the Selector and Shared IIR registers

[Mika Kuoppala]

From: Oscar Mateo <oscar.mateo@intel.com>

Both for clarity and so that we can reuse it later on.

v2:
  - local_clock returns a u64 (Tvrtko)
  - Use the funky BIT(bit) version (Tvrtko)
  - wait_start not required (Tvrtko)
  - Use time_after64 (Oscar)

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 58 +++++++++++++++++++++++++----------------
 1 file changed, 35 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3a1de4e2a941..0318c560c74b 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -243,6 +243,37 @@ void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
+static u16 gen11_service_shared_iir(struct drm_i915_private *dev_priv,
+				    unsigned int bank,
+				    unsigned int bit)
+{
+	u64 wait_end;
+	u16 irq;
+	u32 ident;
+
+	I915_WRITE_FW(GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
+	/*
+	 * NB: Specs do not specify how long to spin wait.
+	 * Taking 100us as an educated guess
+	 */
+	wait_end = (local_clock() >> 10) + 100;
+	do {
+		ident = I915_READ_FW(GEN11_INTR_IDENTITY_REG(bank));
+	} while (!(ident & GEN11_INTR_DATA_VALID) &&
+		 !time_after64(local_clock() >> 10, wait_end));
+
+	if (!(ident & GEN11_INTR_DATA_VALID))
+		DRM_ERROR("INTR_IDENTITY_REG%u:%u timed out!\n", bank, bit);
+
+	irq = ident & GEN11_INTR_ENGINE_MASK;
+	if (!irq)
+		DRM_ERROR("INTR_IDENTITY_REG%u:%u blank!\n", bank, bit);
+
+	I915_WRITE_FW(GEN11_INTR_IDENTITY_REG(bank), ident);
+
+	return irq;
+}
+
 /**
  * ilk_update_display_irq - update DEIMR
  * @dev_priv: driver private
@@ -2763,10 +2794,9 @@ gen11_gt_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 {
 	irqreturn_t ret = IRQ_NONE;
 	u16 irq[2][32];
-	u32 dw, ident;
+	u32 dw;
 	unsigned long tmp;
 	unsigned int bank, bit, engine;
-	unsigned long wait_start, wait_end;
 
 	memset(irq, 0, sizeof(irq));
 
@@ -2776,27 +2806,9 @@ gen11_gt_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 			if (!dw)
 				DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
 			tmp = dw;
-			for_each_set_bit(bit, &tmp, 32) {
-				I915_WRITE_FW(GEN11_IIR_REG_SELECTOR(bank), 1 << bit);
-				wait_start = local_clock() >> 10;
-				/* NB: Specs do not specify how long to spin wait.
-				 * Taking 100us as an educated guess */
-				wait_end = wait_start + 100;
-				do {
-					ident = I915_READ_FW(GEN11_INTR_IDENTITY_REG(bank));
-				} while (!(ident & GEN11_INTR_DATA_VALID) &&
-					 !time_after((unsigned long)local_clock() >> 10, wait_end));
-
-				if (!(ident & GEN11_INTR_DATA_VALID))
-					DRM_ERROR("INTR_IDENTITY_REG%u:%u timed out!\n",
-						  bank, bit);
-
-				irq[bank][bit] = ident & GEN11_INTR_ENGINE_MASK;
-				if (!irq[bank][bit])
-					DRM_ERROR("INTR_IDENTITY_REG%u:%u blank!\n",
-						  bank, bit);
-				I915_WRITE_FW(GEN11_INTR_IDENTITY_REG(bank), ident);
-			}
+			for_each_set_bit(bit, &tmp, 32)
+				irq[bank][bit] =
+					gen11_service_shared_iir(dev_priv, bank, bit);
 			I915_WRITE_FW(GEN11_GT_INTR_DW(bank), dw);
 		}
 	}
-- 
2.14.1

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[PATCH 19/20] drm/i915/icl: Handle RPS interrupts correctly for Gen11

[Mika Kuoppala]

From: Oscar Mateo <oscar.mateo@intel.com>

Using the new hierarchical interrupt infrastructure.

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c  | 68 +++++++++++++++++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  |  6 ++--
 3 files changed, 60 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0318c560c74b..cd7b0bf5bd78 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -339,17 +339,29 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 
 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 {
+	WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11);
+
 	return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 }
 
 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 {
-	return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
+	if (INTEL_GEN(dev_priv) >= 11)
+		return GEN11_GPM_WGBOXPERF_INTR_MASK;
+	else if (INTEL_GEN(dev_priv) >= 8)
+		return GEN8_GT_IMR(2);
+	else
+		return GEN6_PMIMR;
 }
 
 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 {
-	return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
+	if (INTEL_GEN(dev_priv) >= 11)
+		return GEN11_GPM_WGBOXPERF_INTR_ENABLE;
+	else if (INTEL_GEN(dev_priv) >= 8)
+		return GEN8_GT_IER(2);
+	else
+		return GEN6_PMIER;
 }
 
 /**
@@ -431,6 +443,28 @@ static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_m
 	/* though a barrier is missing here, but don't really need a one */
 }
 
+void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv)
+{
+	u32 dw;
+
+	spin_lock_irq(&dev_priv->irq_lock);
+
+	/*
+	 * According to the BSpec, DW_IIR bits cannot be cleared without
+	 * first servicing the Selector & Shared IIR registers.
+	 */
+	dw = I915_READ_FW(GEN11_GT_INTR_DW0);
+	while (dw & BIT(GEN11_GTPM)) {
+		gen11_service_shared_iir(dev_priv, 0, GEN11_GTPM);
+		I915_WRITE_FW(GEN11_GT_INTR_DW0, BIT(GEN11_GTPM));
+		dw = I915_READ_FW(GEN11_GT_INTR_DW0);
+	}
+
+	dev_priv->gt_pm.rps.pm_iir = 0;
+
+	spin_unlock_irq(&dev_priv->irq_lock);
+}
+
 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 {
 	spin_lock_irq(&dev_priv->irq_lock);
@@ -446,12 +480,12 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 	if (READ_ONCE(rps->interrupts_enabled))
 		return;
 
-	if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
-		return;
-
 	spin_lock_irq(&dev_priv->irq_lock);
 	WARN_ON_ONCE(rps->pm_iir);
-	WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
+	if (INTEL_GEN(dev_priv) >= 11)
+		WARN_ON_ONCE(I915_READ_FW(GEN11_GT_INTR_DW0) & BIT(GEN11_GTPM));
+	else
+		WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 	rps->interrupts_enabled = true;
 	gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 
@@ -465,9 +499,6 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 	if (!READ_ONCE(rps->interrupts_enabled))
 		return;
 
-	if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
-		return;
-
 	spin_lock_irq(&dev_priv->irq_lock);
 	rps->interrupts_enabled = false;
 
@@ -484,7 +515,10 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 	 * state of the worker can be discarded.
 	 */
 	cancel_work_sync(&rps->work);
-	gen6_reset_rps_interrupts(dev_priv);
+	if (INTEL_GEN(dev_priv) >= 11)
+		gen11_reset_rps_interrupts(dev_priv);
+	else
+		gen6_reset_rps_interrupts(dev_priv);
 }
 
 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
@@ -2842,8 +2876,8 @@ gen11_gt_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 	}
 
 	if (irq[0][GEN11_GTPM] & dev_priv->pm_rps_events) {
+		gen6_rps_irq_handler(dev_priv, (u32)irq[0][GEN11_GTPM]);
 		ret = IRQ_HANDLED;
-		gen6_rps_irq_handler(dev_priv, tmp);
 	}
 
 	return ret;
@@ -3314,6 +3348,9 @@ static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,	~0);
 	I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,	~0);
 	I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,	~0);
+
+	I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
+	I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK,  ~0);
 }
 
 static void gen11_irq_reset(struct drm_device *dev)
@@ -3852,7 +3889,14 @@ static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,	~(irqs | irqs << 16));
 	I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,	~(irqs | irqs << 16));
 
-	dev_priv->pm_imr = 0xffffffff; /* TODO */
+	/*
+	 * RPS interrupts will get enabled/disabled on demand when RPS itself
+	 * is enabled/disabled.
+	 */
+	dev_priv->pm_ier = 0x0;
+	dev_priv->pm_imr = ~dev_priv->pm_ier;
+	I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
+	I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK,  ~0);
 }
 
 static int gen11_irq_postinstall(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 898064e8bea7..cafed39ca986 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1318,6 +1318,7 @@ void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
+void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 087f981461e7..9218aeb783fb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8027,10 +8027,10 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 	dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
 	intel_disable_gt_powersave(dev_priv);
 
-	if (INTEL_GEN(dev_priv) < 11)
-		gen6_reset_rps_interrupts(dev_priv);
+	if (INTEL_GEN(dev_priv) >= 11)
+		gen11_reset_rps_interrupts(dev_priv);
 	else
-		WARN_ON_ONCE(1);
+		gen6_reset_rps_interrupts(dev_priv);
 }
 
 static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
-- 
2.14.1

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[PATCH 20/20] drm/i915/icl: Enable RC6 and RPS in Gen11

[Mika Kuoppala]

From: Oscar Mateo <oscar.mateo@intel.com>

AFAICT, once the new interrupt is in place, the rest should behave the
same as Gen10.

v2: Update ring frequencies (Sagar)

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 10 +++++-----
 drivers/gpu/drm/i915/intel_pm.c     | 10 ++++------
 2 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 49d5bed87798..8931d1df1f81 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1244,20 +1244,20 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
 		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
 			    rp_state_cap >> 16) & 0xff;
 		max_freq *= (IS_GEN9_BC(dev_priv) ||
-			     IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
+			     INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
 			   intel_gpu_freq(dev_priv, max_freq));
 
 		max_freq = (rp_state_cap & 0xff00) >> 8;
 		max_freq *= (IS_GEN9_BC(dev_priv) ||
-			     IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
+			     INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
 			   intel_gpu_freq(dev_priv, max_freq));
 
 		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
 			    rp_state_cap >> 0) & 0xff;
 		max_freq *= (IS_GEN9_BC(dev_priv) ||
-			     IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
+			     INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
 		seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
 			   intel_gpu_freq(dev_priv, max_freq));
 		seq_printf(m, "Max overclocked frequency: %dMHz\n",
@@ -1838,7 +1838,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
 	if (ret)
 		goto out;
 
-	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+	if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
 		/* Convert GT frequency to 50 HZ units */
 		min_gpu_freq = rps->min_freq_softlimit / GEN9_FREQ_SCALER;
 		max_gpu_freq = rps->max_freq_softlimit / GEN9_FREQ_SCALER;
@@ -1857,7 +1857,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
 		seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
 			   intel_gpu_freq(dev_priv, (gpu_freq *
 						     (IS_GEN9_BC(dev_priv) ||
-						      IS_CANNONLAKE(dev_priv) ?
+						      INTEL_GEN(dev_priv) >= 10 ?
 						      GEN9_FREQ_SCALER : 1))),
 			   ((ia_freq >> 0) & 0xff) * 100,
 			   ((ia_freq >> 8) & 0xff) * 100);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9218aeb783fb..34a88f0ab89f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6573,7 +6573,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
 
 	rps->efficient_freq = rps->rp1_freq;
 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
-	    IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+	    IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
 		u32 ddcc_status = 0;
 
 		if (sandybridge_pcode_read(dev_priv,
@@ -6586,7 +6586,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
 					rps->max_freq);
 	}
 
-	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+	if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
 		/* Store the frequency values in 16.66 MHZ units, which is
 		 * the natural hardware unit for SKL
 		 */
@@ -6919,7 +6919,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
 	/* convert DDR frequency from units of 266.6MHz to bandwidth */
 	min_ring_freq = mult_frac(min_ring_freq, 8, 3);
 
-	if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+	if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
 		/* Convert GT frequency to 50 HZ units */
 		min_gpu_freq = rps->min_freq / GEN9_FREQ_SCALER;
 		max_gpu_freq = rps->max_freq / GEN9_FREQ_SCALER;
@@ -6937,7 +6937,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
 		int diff = max_gpu_freq - gpu_freq;
 		unsigned int ia_freq = 0, ring_freq = 0;
 
-		if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+		if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
 			/*
 			 * ring_freq = 2 * GT. ring_freq is in 100MHz units
 			 * No floor required for ring frequency on SKL.
@@ -8143,8 +8143,6 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
 		cherryview_enable_rps(dev_priv);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
 		valleyview_enable_rps(dev_priv);
-	} else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) {
-		/* TODO */
 	} else if (INTEL_GEN(dev_priv) >= 9) {
 		gen9_enable_rps(dev_priv);
 	} else if (IS_BROADWELL(dev_priv)) {
-- 
2.14.1

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Re: [PATCH 05/20] drm/i915/icl: Interrupt handling

[Chris Wilson]

Quoting Mika Kuoppala (2018-02-13 16:37:23)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> v2: Rebase.
> 
> v3:
>   * Remove DPF, it has been removed from SKL+.
>   * Fix -internal rebase wrt. execlists interrupt handling.
> 
> v4: Rebase.
> 
> v5:
>   * Updated for POR changes. (Daniele Ceraolo Spurio)
>   * Merged with irq handling fixes by Daniele Ceraolo Spurio:
>       * Simplify the code by using gen8_cs_irq_handler.
>       * Fix interrupt handling for the upstream kernel.
> 
> v6:
>   * Remove early bringup debug messages (Tvrtko)
>   * Add NB about arbitrary spin wait timeout (Tvrtko)
> 
> v7 (from Paulo):
>   * Don't try to write RO bits to registers.
>   * Don't check for PCH types that don't exist. PCH interrupts are not
>     here yet.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 210 ++++++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_pm.c |   7 +-
>  2 files changed, 216 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b886bd459acc..3a1de4e2a941 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -415,6 +415,9 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
>         if (READ_ONCE(rps->interrupts_enabled))
>                 return;
>  
> +       if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
> +               return;
> +
>         spin_lock_irq(&dev_priv->irq_lock);
>         WARN_ON_ONCE(rps->pm_iir);
>         WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
> @@ -431,6 +434,9 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
>         if (!READ_ONCE(rps->interrupts_enabled))
>                 return;
>  
> +       if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
> +               return;
> +
>         spin_lock_irq(&dev_priv->irq_lock);
>         rps->interrupts_enabled = false;
>  
> @@ -2746,6 +2752,131 @@ static void __fini_wedge(struct wedge_me *w)
>              (W)->i915;                                                 \
>              __fini_wedge((W)))
>  
> +static __always_inline void
> +gen11_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
> +{
> +       gen8_cs_irq_handler(engine, iir, 0);
> +}
> +
> +static irqreturn_t
> +gen11_gt_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> +{
> +       irqreturn_t ret = IRQ_NONE;
> +       u16 irq[2][32];
> +       u32 dw, ident;
> +       unsigned long tmp;
> +       unsigned int bank, bit, engine;
> +       unsigned long wait_start, wait_end;
> +
> +       memset(irq, 0, sizeof(irq));
> +
> +       for (bank = 0; bank < 2; bank++) {
> +               if (master_ctl & GEN11_GT_DW_IRQ(bank)) {
> +                       dw = I915_READ_FW(GEN11_GT_INTR_DW(bank));
> +                       if (!dw)
> +                               DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
> +                       tmp = dw;
> +                       for_each_set_bit(bit, &tmp, 32) {
> +                               I915_WRITE_FW(GEN11_IIR_REG_SELECTOR(bank), 1 << bit);
> +                               wait_start = local_clock() >> 10;
> +                               /* NB: Specs do not specify how long to spin wait.
> +                                * Taking 100us as an educated guess */
> +                               wait_end = wait_start + 100;
> +                               do {
> +                                       ident = I915_READ_FW(GEN11_INTR_IDENTITY_REG(bank));
> +                               } while (!(ident & GEN11_INTR_DATA_VALID) &&
> +                                        !time_after((unsigned long)local_clock() >> 10, wait_end));
> +
> +                               if (!(ident & GEN11_INTR_DATA_VALID))
> +                                       DRM_ERROR("INTR_IDENTITY_REG%u:%u timed out!\n",
> +                                                 bank, bit);
> +
> +                               irq[bank][bit] = ident & GEN11_INTR_ENGINE_MASK;
> +                               if (!irq[bank][bit])
> +                                       DRM_ERROR("INTR_IDENTITY_REG%u:%u blank!\n",
> +                                                 bank, bit);
> +                               I915_WRITE_FW(GEN11_INTR_IDENTITY_REG(bank), ident);
> +                       }
> +                       I915_WRITE_FW(GEN11_GT_INTR_DW(bank), dw);
> +               }
> +       }
> +
> +       if (irq[0][GEN11_RCS0]) {
> +               gen11_cs_irq_handler(dev_priv->engine[RCS],
> +                                    irq[0][GEN11_RCS0]);
> +               ret = IRQ_HANDLED;

If you implement the same reset policy as we have for earlier gen, you
need to set IRQ_HANDLED based solely on the master. In short, just make
this function return void.
-Chris
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Re: [PATCH 12/20] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Michal Wajdeczko]

On Tue, 13 Feb 2018 17:37:30 +0100, Mika Kuoppala  
<mika.kuoppala@linux.intel.com> wrote:

> From: Oscar Mateo <oscar.mateo@intel.com>
>
> In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the
> Video Enhancement engines (aka VEBOX, aka VECS) could be fused off. Also,
> each VDBOX and VEBOX has its own power well, which only exist if the  
> related
> engine exists in the HW.
>
> Unfortunately, we have a Catch-22 situation going on: we need to read an
> MMIO register with the fuse info, but we cannot fully enable MMIO until
> we read it (since we need the real engines to initialize the forcewake
> domains). We workaround this problem by reading the fuse after the MMIO
> is partially ready, but before we initialize forcewake.
>
> Bspec: 20680
>
> v2: We were shifting incorrectly for vebox disable (Vinay)
>
> v3: Assert mmio is ready and warn if we have attempted to initialize
>     forcewake for fused-off engines (Paulo)
>
> v4:
>   - Use INTEL_GEN in new code (Tvrtko)
>   - Shorter local variable (Tvrtko, Michal)
>   - Keep "if (!...) continue" style (Tvrtko)
>   - No unnecessary BUG_ON (Tvrtko)
>   - WARN_ON and cleanup if wrong mask (Tvrtko, Michal)
>   - Use I915_READ_FW (Michal)
>   - Use I915_MAX_VCS/VECS macros (Michal)
>
> v5: Rebased by Rodrigo fixing conflicts on top of:
>     commit 33def1ff7b0 ("drm/i915: Simplify intel_engines_init")
>
> v6: Fix v5. Remove info->num_rings. (by Oscar)
>
> v7: Rebase (Rodrigo).
>
> v8:
>   - s/intel_device_info_fused_off_engines/intel_device_info_init_mmio  
> (Chris)
>   - Make vdbox_disable & vebox_disable local variables (Chris)
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c          |  2 ++
>  drivers/gpu/drm/i915/i915_drv.h          |  1 +
>  drivers/gpu/drm/i915/i915_reg.h          |  5 +++
>  drivers/gpu/drm/i915/intel_device_info.c | 54  
> ++++++++++++++++++++++++++++++++
>  4 files changed, 62 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c  
> b/drivers/gpu/drm/i915/i915_drv.c
> index 9380c9f69b0f..43b2f620bca7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1033,6 +1033,8 @@ static int i915_driver_init_mmio(struct  
> drm_i915_private *dev_priv)
>  	if (ret < 0)
>  		goto err_bridge;
> +	intel_device_info_init_mmio(dev_priv);
> +
>  	intel_uncore_init(dev_priv);
> 	intel_uc_init_mmio(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h  
> b/drivers/gpu/drm/i915/i915_drv.h
> index 65e674668b2e..ba16c2025364 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3438,6 +3438,7 @@ void i915_unreserve_fence(struct  
> drm_i915_fence_reg *fence);
>  void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
>  void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
> +void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);

This function should be declared in "intel_device_info.h"

>  void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
>  void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
>  				       struct sg_table *pages);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h  
> b/drivers/gpu/drm/i915/i915_reg.h
> index b6cd725ff0b7..2b8d3a13dd27 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2860,6 +2860,11 @@ enum i915_power_well_id {
>  #define GEN10_EU_DISABLE3		_MMIO(0x9140)
>  #define   GEN10_EU_DIS_SS_MASK		0xff
> +#define GEN11_GT_VEBOX_VDBOX_DISABLE	_MMIO(0x9140)
> +#define GEN11_GT_VDBOX_DISABLE_MASK	0xff
> +#define GEN11_GT_VEBOX_DISABLE_SHIFT	16
> +#define GEN11_GT_VEBOX_DISABLE_MASK	(0xff <<  
> GEN11_GT_VEBOX_DISABLE_SHIFT)
> +

Missing indent (2 spaces) for above bit fields definitions.

>  #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
>  #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
>  #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c  
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 9352f34e75c4..7c8779faf162 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -595,3 +595,57 @@ void intel_driver_caps_print(const struct  
> intel_driver_caps *caps,
>  {
>  	drm_printf(p, "scheduler: %x\n", caps->scheduler);
>  }
> +
> +/*
> + * Determine which engines are fused off in our particular hardware.
> + *
> + * This function needs to be called after the MMIO has been setup (as  
> we need
> + * to read registers) but before uncore init (because the powerwell for  
> the
> + * fused off engines doesn't exist, so we cannot initialize forcewake  
> for them)
> + */
> +void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_device_info *info = mkwrite_device_info(dev_priv);
> +	u8 vdbox_disable, vebox_disable;
> +	u32 media_fuse;
> +	int i;
> +
> +	if (INTEL_GEN(dev_priv) < 11)
> +		return;
> +
> +	GEM_BUG_ON(!dev_priv->regs);
> +
> +	media_fuse = I915_READ_FW(GEN11_GT_VEBOX_VDBOX_DISABLE);
> +
> +	vdbox_disable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> +	vebox_disable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> +			GEN11_GT_VEBOX_DISABLE_SHIFT;
> +
> +	DRM_DEBUG_DRIVER("vdbox disable: %04x\n", vdbox_disable);
> +	for (i = 0; i < I915_MAX_VCS; i++) {
> +		if (!HAS_ENGINE(dev_priv, _VCS(i)))
> +			continue;
> +
> +		if (!(BIT(i) & vdbox_disable))
> +			continue;
> +
> +		info->ring_mask &= ~ENGINE_MASK(_VCS(i));
> +		WARN_ON(dev_priv->uncore.fw_domains &
> +			BIT(FW_DOMAIN_ID_MEDIA_VDBOX0 + i));
> +		DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
> +	}
> +
> +	DRM_DEBUG_DRIVER("vebox disable: %04x\n", vebox_disable);
> +	for (i = 0; i < I915_MAX_VECS; i++) {
> +		if (!HAS_ENGINE(dev_priv, _VECS(i)))
> +			continue;
> +
> +		if (!(BIT(i) & vebox_disable))
> +			continue;
> +
> +		info->ring_mask &= ~ENGINE_MASK(_VECS(i));
> +		WARN_ON(dev_priv->uncore.fw_domains &
> +			BIT(FW_DOMAIN_ID_MEDIA_VEBOX0 + i));
> +		DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
> +	}
> +}
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✓ Fi.CI.BAT: success for ICL GEM enabling (v2)

[Patchwork]

== Series Details ==

Series: ICL GEM enabling (v2)
URL   : https://patchwork.freedesktop.org/series/38174/
State : success

== Summary ==

Series 38174v1 ICL GEM enabling (v2)
https://patchwork.freedesktop.org/api/1.0/series/38174/revisions/1/mbox/

Test debugfs_test:
        Subgroup read_all_entries:
                incomplete -> PASS       (fi-snb-2520m) fdo#103713
Test gem_cs_tlb:
        Subgroup basic-default:
                incomplete -> PASS       (fi-cnl-y3)
Test prime_vgem:
        Subgroup basic-fence-flip:
                fail       -> PASS       (fi-ilk-650) fdo#104008

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u     total:288  pass:265  dwarn:0   dfail:0   fail:2   skip:21  time:440s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:424s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:374s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:496s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:287s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:479s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:483s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:469s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:455s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:569s
fi-cnl-y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:572s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:416s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:283s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:508s
fi-hsw-4770      total:288  pass:259  dwarn:0   dfail:0   fail:2   skip:27  time:413s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:414s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:465s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:413s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:457s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:495s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:502s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:592s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:428s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:510s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:527s
fi-skl-6700k2    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:491s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:484s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:413s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:431s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:533s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:395s
Blacklisted hosts:
fi-glk-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:466s
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:455s

ec41124d62839a682718af73244b1d2a225530ca drm-tip: 2018y-02m-13d-16h-31m-22s UTC integration manifest
ade2e1602553 drm/i915/icl: Enable RC6 and RPS in Gen11
8d91f5b271fe drm/i915/icl: Handle RPS interrupts correctly for Gen11
c451e117050f drm/i915/icl: Split out the servicing of the Selector and Shared IIR registers
1796f4dc0a0e drm/i915/icl: Add configuring MOCS in new Icelake engines
46cd1354f876 drm/i915/icl: Add reset control register changes
38c95f6f8c64 drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
e442cd636573 drm/i915/icl: Update subslice define for ICL 11
911fe1798851 drm/i915/icl: Enable the extra video decode and enhancement boxes for Icelake 11
89d0774005a5 drm/i915/icl: Check for fused-off VDBOX and VEBOX instances
928dabf7c7ac drm/i915/icl: Gen11 forcewake support
c6e51f3e7b8d drm/i915/icl: Add Indirect Context Offset for Gen11
81e37af9a5c9 drm/i915/icl: Enhanced execution list support
32b3d5b001ba drm/i915/icl: new context descriptor support
dd5b12c6b8f0 drm/i915/icl: Correctly initialize the Gen11 engines
f73e424fe712 drm/i915/icl: Ringbuffer interrupt handling
301b90e8f64f drm/i915/icl: Interrupt handling
18d346c974f4 drm/i915/icl: Prepare for more rings
be1f4107290d drm/i915/icl: Show interrupt registers in debugfs
4c9df36c42fa drm/i915/icl: add icelake_init_clock_gating()
6a7d94c6a085 drm/i915/icl: Add the ICL PCI IDs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7997/issues.html
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Re: [PATCH 01/20] drm/i915/icl: Add the ICL PCI IDs

[Michel Thierry]

On 13/02/18 08:37, Mika Kuoppala wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> This is the current PCI ID list in our documentation.
> 
> Let's leave the _gt#_ part out for now since our current documentation
> is not 100% clear and we don't need this info now anyway.
> 
> v2: Use the new ICL_11 naming (Kelvin Gardiner).
> v3: Latest IDs as per BSpec (Oscar).
> v4: Make it compile (Paulo).
> v5: Remove comments (Lucas).
> v6: Multile rebases (Paulo).
> v7: Rebase (Mika)
> 
> Reviewed-by: Anuj Phogat <anuj.phogat@intel.com> (v1)
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_pci.c |  1 +
>   include/drm/i915_pciids.h       | 12 ++++++++++++
>   2 files changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 4e7a10c89782..c94a76bef763 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -650,6 +650,7 @@ static const struct pci_device_id pciidlist[] = {
>          INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
>          INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
>          INTEL_CNL_IDS(&intel_cannonlake_info),
> +       INTEL_ICL_11_IDS(&intel_icelake_11_info),
>          {0, 0, 0}
>   };
>   MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 9e1fe6634424..4afcdb4492f1 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -430,4 +430,16 @@
>          INTEL_VGA_DEVICE(0x5A5C, info), \
>          INTEL_VGA_DEVICE(0x5A44, info)
> 
> +/* ICL */
> +#define INTEL_ICL_11_IDS(info) \
> +       INTEL_VGA_DEVICE(0x8A50, info), \
> +       INTEL_VGA_DEVICE(0x8A51, info), \
> +       INTEL_VGA_DEVICE(0x8A5C, info), \
> +       INTEL_VGA_DEVICE(0x8A5D, info), \
> +       INTEL_VGA_DEVICE(0x8A52, info), \
> +       INTEL_VGA_DEVICE(0x8A5A, info), \
> +       INTEL_VGA_DEVICE(0x8A5B, info), \
> +       INTEL_VGA_DEVICE(0x8A71, info), \
> +       INTEL_VGA_DEVICE(0x8A70, info)
> +
>   #endif /* _I915_PCIIDS_H */

List is still correct and up-to-date.

Reviewed-by: Michel Thierry <michel.thierry@intel.com>

> --
> 2.14.1
> 
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Re: [PATCH 13/20] drm/i915/icl: Enable the extra video decode and enhancement boxes for Icelake 11

[Michel Thierry]

On 13/02/18 08:37, Mika Kuoppala wrote:
> From: Oscar Mateo <oscar.mateo@intel.com>
> 
> Icelake 11 has one vebox and two vdboxes (0 and 2).
> 
> Bspec: 21140
> 
> v2: Split out in two (Daniele)
> 
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_pci.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 8c72a2bd315e..508f17e956e4 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -591,6 +591,7 @@ static const struct intel_device_info intel_icelake_11_info = {
>          .platform = INTEL_ICELAKE,
>          .is_alpha_support = 1,
>          .has_resource_streamer = 0,
> +       .ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
>   };
> 
>   /*
> --
> 2.14.1
> 

Reviewed-by: Michel Thierry <michel.thierry@intel.com>
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Re: [PATCH 17/20] drm/i915/icl: Add configuring MOCS in new Icelake engines

[Michel Thierry]

On 13/02/18 08:37, Mika Kuoppala wrote:
> From: Tomasz Lis <tomasz.lis@intel.com>
> 
> In Icelake, there are more engines on which Memory Object Control States need
> to be configured. Besides adding Icelake under Skylake config, the patch makes
> sure MOCS register addresses for the new engines are properly defined.
> 
> Additional patch might be need later, in case the specification will
> propose different MOCS config values for Icelake than in previous gens.
> 
> v2: Restricted comments to gen11, updated description, renamed defines.
> 
> v3: Used proper engine indexes for gen11.
> 
> v4: Removed engines which are not part of gen11.0
> 
> v5: Style fixes (proposed by mwajdeczko)
> 
> BSpec: 19405
> BSpec: 21140
> Cc: Oscar Mateo Lozano <oscar.mateo@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h   | 2 ++
>   drivers/gpu/drm/i915/intel_mocs.c | 5 ++++-
>   2 files changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 38824a6e5d05..ffe48e530b8d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9785,6 +9785,8 @@ enum skl_power_gate {
>   #define GEN9_MFX1_MOCS(i)      _MMIO(0xca00 + (i) * 4) /* Media 1 MOCS registers */
>   #define GEN9_VEBOX_MOCS(i)     _MMIO(0xcb00 + (i) * 4) /* Video MOCS registers */
>   #define GEN9_BLT_MOCS(i)       _MMIO(0xcc00 + (i) * 4) /* Blitter MOCS registers */
> +/* Media decoder 2 MOCS registers */
> +#define GEN11_MFX2_MOCS(i)     _MMIO(0x10000 + (i) * 4)
> 
>   /* gamt regs */
>   #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index abb7a8c1e340..2d75666537b3 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -178,7 +178,8 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv,
>   {
>          bool result = false;
> 
> -       if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> +       if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) ||
> +           IS_ICELAKE(dev_priv)) {
>                  table->size  = ARRAY_SIZE(skylake_mocs_table);
>                  table->table = skylake_mocs_table;
>                  result = true;
> @@ -217,6 +218,8 @@ static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index)
>                  return GEN9_VEBOX_MOCS(index);
>          case VCS2:
>                  return GEN9_MFX1_MOCS(index);
> +       case VCS3:
> +               return GEN11_MFX2_MOCS(index);
>          default:
>                  MISSING_CASE(engine_id);
>                  return INVALID_MMIO_REG;
> --
> 2.14.1
> 

Reviewed-by: Michel Thierry <michel.thierry@intel.com>
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Re: [PATCH 15/20] drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection

[Lionel Landwerlin]

Checked the documentation. It looks good to me :

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

On 13/02/18 16:37, Mika Kuoppala wrote:
> From: Kelvin Gardiner <kelvin.gardiner@intel.com>
>
> This patch adds support to detect ICL, slice, subslice and EU fuse
> settings.
>
> Add addresses for ICL 11 slice, subslice and EU fuses registers.
> These register addresses are the same as previous platforms but the
> format and / or the meaning of the information is different. Therefore
> Gen11 defines for these registers are added.
>
> Bspec: 9731
> Bspec: 20643
> Bspec: 20673
>
> Signed-off-by: Kelvin Gardiner <kelvin.gardiner@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h          |  9 +++++++++
>   drivers/gpu/drm/i915/intel_device_info.c | 25 ++++++++++++++++++++++++-
>   2 files changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 915f11469bc1..96417c1b3751 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2869,6 +2869,15 @@ enum i915_power_well_id {
>   #define GEN11_GT_VEBOX_DISABLE_SHIFT	16
>   #define GEN11_GT_VEBOX_DISABLE_MASK	(0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
>   
> +#define GEN11_EU_DISABLE _MMIO(0x9134)
> +#define GEN11_EU_DIS_MASK 0xFF
> +
> +#define GEN11_GT_SLICE_ENABLE _MMIO(0x9138)
> +#define GEN11_GT_S_ENA_MASK 0xFF
> +
> +#define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913C)
> +#define GEN11_GT_SS_DIS_MASK 0xFF
> +
>   #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
>   #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
>   #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 7c8779faf162..80af8a24c48e 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -120,6 +120,27 @@ void intel_device_info_dump(const struct intel_device_info *info,
>   	intel_device_info_dump_flags(info, p);
>   }
>   
> +static void gen11_sseu_info_init(struct drm_i915_private *dev_priv)
> +{
> +	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> +	int eu_max = 8;
> +	u32 eu_disable;
> +
> +	sseu->slice_mask = I915_READ(GEN11_GT_SLICE_ENABLE) &
> +				GEN11_GT_S_ENA_MASK;
> +	sseu->subslice_mask = ~(I915_READ(GEN11_GT_SUBSLICE_DISABLE) &
> +				GEN11_GT_SS_DIS_MASK);
> +	eu_disable = I915_READ(GEN11_EU_DISABLE) & GEN11_GT_S_ENA_MASK;
> +
> +	sseu->eu_per_subslice = eu_max - hweight32(eu_disable);
> +	sseu->eu_total = sseu->eu_per_subslice * hweight32(sseu->subslice_mask);
> +
> +	/* ICL has no power gating restrictions. */
> +	sseu->has_slice_pg = 1;
> +	sseu->has_subslice_pg = 1;
> +	sseu->has_eu_pg = 1;
> +}
> +
>   static void gen10_sseu_info_init(struct drm_i915_private *dev_priv)
>   {
>   	struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
> @@ -583,8 +604,10 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
>   		broadwell_sseu_info_init(dev_priv);
>   	else if (INTEL_GEN(dev_priv) == 9)
>   		gen9_sseu_info_init(dev_priv);
> -	else if (INTEL_GEN(dev_priv) >= 10)
> +	else if (INTEL_GEN(dev_priv) == 10)
>   		gen10_sseu_info_init(dev_priv);
> +	else if (INTEL_INFO(dev_priv)->gen >= 11)
> +		gen11_sseu_info_init(dev_priv);
>   
>   	/* Initialize command stream timestamp frequency */
>   	info->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);


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Re: [PATCH 06/20] drm/i915/icl: Ringbuffer interrupt handling

[Daniele Ceraolo Spurio]

On 13/02/18 08:37, Mika Kuoppala wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> Since it is not possible to mask individual engine instances
> and they are all permanently unmasked we do not need to do
> anything for engine interrupt management.
> 
> v2: Rebase.
> v3: Remove gen 11 extra check in logical_render_ring_init.
> v4: Rebase fixes.
> v5: Rebase/refactor.
> v6: Rebase.
> v7: Rebase.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_breadcrumbs.c | 20 ++++++++++++--------
>   drivers/gpu/drm/i915/intel_lrc.c         | 11 +++++++++--
>   drivers/gpu/drm/i915/intel_ringbuffer.h  |  5 +++++
>   3 files changed, 26 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> index b955f7d7bd0f..69c727f97eb5 100644
> --- a/drivers/gpu/drm/i915/intel_breadcrumbs.c
> +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c
> @@ -167,18 +167,22 @@ static void irq_enable(struct intel_engine_cs *engine)
>   	 */
>   	set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
>   
> -	/* Caller disables interrupts */
> -	spin_lock(&engine->i915->irq_lock);
> -	engine->irq_enable(engine);
> -	spin_unlock(&engine->i915->irq_lock);
> +	if (engine->irq_enable) {
> +		/* Caller disables interrupts */
> +		spin_lock(&engine->i915->irq_lock);
> +		engine->irq_enable(engine);
> +		spin_unlock(&engine->i915->irq_lock);
> +	}
>   }
>   
>   static void irq_disable(struct intel_engine_cs *engine)
>   {
> -	/* Caller disables interrupts */
> -	spin_lock(&engine->i915->irq_lock);
> -	engine->irq_disable(engine);
> -	spin_unlock(&engine->i915->irq_lock);
> +	if (engine->irq_disable) {
> +		/* Caller disables interrupts */
> +		spin_lock(&engine->i915->irq_lock);
> +		engine->irq_disable(engine);
> +		spin_unlock(&engine->i915->irq_lock);
> +	}
>   }
>   
>   void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index c2c8380a0121..da396c46b345 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1989,8 +1989,15 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
>   
>   	engine->set_default_submission = execlists_set_default_submission;
>   
> -	engine->irq_enable = gen8_logical_ring_enable_irq;
> -	engine->irq_disable = gen8_logical_ring_disable_irq;
> +	if (INTEL_GEN(engine->i915) < 11) {
> +		engine->irq_enable = gen8_logical_ring_enable_irq;
> +		engine->irq_disable = gen8_logical_ring_disable_irq;
> +	} else {
> +		/*
> +		 * On Gen11 interrupts are permanently unmasked and there
> +		 * are no per-engine instance mask bits.
> +		 */

As mentioned on the previous review, the masks exist but we can't use 
them easily, because according to the docs we need to clear them to 
allow C6 entry. My guess is that it is actually the possible pending 
interrupts behind the mask that can keep the device awake more than the 
masks value themselves, but the docs just say to clear the registers. 
Maybe a possible solution would be to track idleness per-engine and 
unmask the interrupts once all requests have completed on the specific 
engine? Anyway, while we're still in early enabling I'd just update this 
comment and the commit message to reflect that we don't use the mask to 
allow C6 entry and we can eventually come back to refine this at a later 
point if we see that we're generating too many interrupts.

With the updated comment and commit message:

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Daniele

> +	}
>   	engine->emit_bb_start = gen8_emit_bb_start;
>   }
>   
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index f743351c441f..caed64bb02da 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -393,6 +393,11 @@ struct intel_engine_cs {
>   
>   	u32             irq_keep_mask; /* always keep these interrupts */
>   	u32		irq_enable_mask; /* bitmask to enable ring interrupt */
> +
> +	/*
> +	 * irq_enable and irq_disable do not have to be provided for
> +	 * an engine. In other words they can be NULL.
> +	 */
>   	void		(*irq_enable)(struct intel_engine_cs *engine);
>   	void		(*irq_disable)(struct intel_engine_cs *engine);
>   
> 
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Re: [PATCH 01/20] drm/i915/icl: Add the ICL PCI IDs

[Anuj Phogat]

[-- Attachment #1.1: Type: text/plain, Size: 2656 bytes --]

On Tue, Feb 13, 2018 at 8:37 AM, Mika Kuoppala <
mika.kuoppala@linux.intel.com> wrote:

> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> This is the current PCI ID list in our documentation.
>
> Let's leave the _gt#_ part out for now since our current documentation
> is not 100% clear and we don't need this info now anyway.
>
> v2: Use the new ICL_11 naming (Kelvin Gardiner).
> v3: Latest IDs as per BSpec (Oscar).
> v4: Make it compile (Paulo).
> v5: Remove comments (Lucas).
> v6: Multile rebases (Paulo).
> v7: Rebase (Mika)
>
> Reviewed-by: Anuj Phogat <anuj.phogat@intel.com> (v1)
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_pci.c |  1 +
>  include/drm/i915_pciids.h       | 12 ++++++++++++
>  2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c
> b/drivers/gpu/drm/i915/i915_pci.c
> index 4e7a10c89782..c94a76bef763 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -650,6 +650,7 @@ static const struct pci_device_id pciidlist[] = {
>         INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
>         INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
>         INTEL_CNL_IDS(&intel_cannonlake_info),
> +       INTEL_ICL_11_IDS(&intel_icelake_11_info),
>         {0, 0, 0}
>  };
>  MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 9e1fe6634424..4afcdb4492f1 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -430,4 +430,16 @@
>         INTEL_VGA_DEVICE(0x5A5C, info), \
>         INTEL_VGA_DEVICE(0x5A44, info)
>
> +/* ICL */
> +#define INTEL_ICL_11_IDS(info) \
> +       INTEL_VGA_DEVICE(0x8A50, info), \
> +       INTEL_VGA_DEVICE(0x8A51, info), \
> +       INTEL_VGA_DEVICE(0x8A5C, info), \
> +       INTEL_VGA_DEVICE(0x8A5D, info), \
> +       INTEL_VGA_DEVICE(0x8A52, info), \
> +       INTEL_VGA_DEVICE(0x8A5A, info), \
> +       INTEL_VGA_DEVICE(0x8A5B, info), \
> +       INTEL_VGA_DEVICE(0x8A71, info), \
> +       INTEL_VGA_DEVICE(0x8A70, info)
>
​Why do we need a GT0 pci id in there?​


> +
>  #endif /* _I915_PCIIDS_H */
> --
> 2.14.1
>
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> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 05/20] drm/i915/icl: Interrupt handling

[Daniele Ceraolo Spurio]

On 13/02/18 08:37, Mika Kuoppala wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> v2: Rebase.
> 
> v3:
>    * Remove DPF, it has been removed from SKL+.
>    * Fix -internal rebase wrt. execlists interrupt handling.
> 
> v4: Rebase.
> 
> v5:
>    * Updated for POR changes. (Daniele Ceraolo Spurio)
>    * Merged with irq handling fixes by Daniele Ceraolo Spurio:
>        * Simplify the code by using gen8_cs_irq_handler.
>        * Fix interrupt handling for the upstream kernel.
> 
> v6:
>    * Remove early bringup debug messages (Tvrtko)
>    * Add NB about arbitrary spin wait timeout (Tvrtko)
> 
> v7 (from Paulo):
>    * Don't try to write RO bits to registers.
>    * Don't check for PCH types that don't exist. PCH interrupts are not
>      here yet.
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_irq.c | 210 ++++++++++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_pm.c |   7 +-
>   2 files changed, 216 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b886bd459acc..3a1de4e2a941 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -415,6 +415,9 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
>   	if (READ_ONCE(rps->interrupts_enabled))
>   		return;
>   
> +	if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
> +		return;
> +
>   	spin_lock_irq(&dev_priv->irq_lock);
>   	WARN_ON_ONCE(rps->pm_iir);
>   	WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
> @@ -431,6 +434,9 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
>   	if (!READ_ONCE(rps->interrupts_enabled))
>   		return;
>   
> +	if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
> +		return;
> +
>   	spin_lock_irq(&dev_priv->irq_lock);
>   	rps->interrupts_enabled = false;
>   
> @@ -2746,6 +2752,131 @@ static void __fini_wedge(struct wedge_me *w)
>   	     (W)->i915;							\
>   	     __fini_wedge((W)))
>   
> +static __always_inline void
> +gen11_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
> +{
> +	gen8_cs_irq_handler(engine, iir, 0);
> +}
> +
> +static irqreturn_t
> +gen11_gt_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> +{
> +	irqreturn_t ret = IRQ_NONE;
> +	u16 irq[2][32];
> +	u32 dw, ident;
> +	unsigned long tmp;
> +	unsigned int bank, bit, engine;
> +	unsigned long wait_start, wait_end;
> +
> +	memset(irq, 0, sizeof(irq));
> +
> +	for (bank = 0; bank < 2; bank++) {
> +		if (master_ctl & GEN11_GT_DW_IRQ(bank)) {
> +			dw = I915_READ_FW(GEN11_GT_INTR_DW(bank));
> +			if (!dw)
> +				DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
> +			tmp = dw;
> +			for_each_set_bit(bit, &tmp, 32) {
> +				I915_WRITE_FW(GEN11_IIR_REG_SELECTOR(bank), 1 << bit);
> +				wait_start = local_clock() >> 10;
> +				/* NB: Specs do not specify how long to spin wait.
> +				 * Taking 100us as an educated guess */
> +				wait_end = wait_start + 100;
> +				do {
> +					ident = I915_READ_FW(GEN11_INTR_IDENTITY_REG(bank));
> +				} while (!(ident & GEN11_INTR_DATA_VALID) &&
> +					 !time_after((unsigned long)local_clock() >> 10, wait_end));

Patch 18/20 changes this to time_after64 and wait_end to u64, which 
looks like the correct way to handle this. Since splitting part of this 
loop out also helps making things cleaner, would it make sense to squash 
patch 18/20 into this one?

> +
> +				if (!(ident & GEN11_INTR_DATA_VALID))
> +					DRM_ERROR("INTR_IDENTITY_REG%u:%u timed out!\n",
> +						  bank, bit);

If the data is not valid we should probably skip writing it to the 
irq[bank][bit] field as we might be writing an incorrect value.

> +
> +				irq[bank][bit] = ident & GEN11_INTR_ENGINE_MASK;
> +				if (!irq[bank][bit])
> +					DRM_ERROR("INTR_IDENTITY_REG%u:%u blank!\n",
> +						  bank, bit);

As mentioned on the previous review, I believe it is actually possible 
to get a blank identity register due to double buffering of interrupts 
if a second interrupt arrives between reading GT_INTR_DW and reading 
GEN11_INTR_IDENTITY, as both interrupts will be serviced on the first 
iteration but GT_INTR_DW will still report the second interrupt after 
being cleared once. We can just drop the error here as nothing bas 
should happen afterwards

> +				I915_WRITE_FW(GEN11_INTR_IDENTITY_REG(bank), ident);
> +			}
> +			I915_WRITE_FW(GEN11_GT_INTR_DW(bank), dw);
> +		}
> +	}
> +
> +	if (irq[0][GEN11_RCS0]) {
> +		gen11_cs_irq_handler(dev_priv->engine[RCS],
> +				     irq[0][GEN11_RCS0]);
> +		ret = IRQ_HANDLED;
> +	}
> +
> +	if (irq[0][GEN11_BCS]) {
> +		gen11_cs_irq_handler(dev_priv->engine[BCS],
> +				     irq[0][GEN11_BCS]);
> +		ret = IRQ_HANDLED;
> +	}
> +
> +	for (engine = 0; engine < 4; engine++) {

Can we use I915_MAX_VCS here?

> +		if (irq[1][GEN11_VCS(engine)]) {
> +			gen11_cs_irq_handler(dev_priv->engine[_VCS(engine)],
> +					     irq[1][GEN11_VCS(engine)]);
> +			ret = IRQ_HANDLED;
> +		}
> +	}
> +
> +	for (engine = 0; engine < 2; engine++) {

same as above but with I915_MAX_VECS

Thanks,
Daniele

> +		if (irq[1][GEN11_VECS(engine)]) {
> +			gen11_cs_irq_handler(dev_priv->engine[_VECS(engine)],
> +					     irq[1][GEN11_VECS(engine)]);
> +			ret = IRQ_HANDLED;
> +		}
> +	}
> +
> +	if (irq[0][GEN11_GTPM] & dev_priv->pm_rps_events) {
> +		ret = IRQ_HANDLED;
> +		gen6_rps_irq_handler(dev_priv, tmp);
> +	}
> +
> +	return ret;
> +}
> +
> +static irqreturn_t gen11_irq_handler(int irq, void *arg)
> +{
> +	struct drm_device *dev = arg;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 master_ctl;
> +	u32 disp_ctl;
> +	irqreturn_t ret;
> +
> +	if (!intel_irqs_enabled(dev_priv))
> +		return IRQ_NONE;
> +
> +	master_ctl = I915_READ_FW(GEN11_GFX_MSTR_IRQ);
> +
> +	master_ctl &= ~GEN11_MASTER_IRQ;
> +	if (!master_ctl)
> +		return IRQ_NONE;
> +
> +	/* Disable interrupts. */
> +	I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, 0);
> +
> +	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
> +	disable_rpm_wakeref_asserts(dev_priv);
> +
> +	/* Find, clear, then process each source of interrupt. */
> +	ret = gen11_gt_irq_handler(dev_priv, master_ctl);
> +
> +	if (master_ctl & GEN11_DISPLAY_IRQ) {
> +		disp_ctl = I915_READ_FW(GEN11_DISPLAY_INT_CTL);
> +		ret |= gen8_de_irq_handler(dev_priv, disp_ctl);
> +	}
> +
> +	/* Acknowledge and enable interrupts. */
> +	I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
> +	POSTING_READ_FW(GEN11_GFX_MSTR_IRQ);
> +
> +	enable_rpm_wakeref_asserts(dev_priv);
> +
> +	return ret;
> +}
> +
>   /**
>    * i915_reset_device - do process context error handling work
>    * @dev_priv: i915 device private
> @@ -3159,6 +3290,42 @@ static void gen8_irq_reset(struct drm_device *dev)
>   		ibx_irq_reset(dev_priv);
>   }
>   
> +static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
> +{
> +	/* Disable RCS, BCS, VCS and VECS class engines. */
> +	I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0);
> +	I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE,	  0);
> +
> +	/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
> +	I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK,	~0);
> +	I915_WRITE(GEN11_BCS_RSVD_INTR_MASK,	~0);
> +	I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,	~0);
> +	I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,	~0);
> +	I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,	~0);
> +}
> +
> +static void gen11_irq_reset(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int pipe;
> +
> +	I915_WRITE(GEN11_GFX_MSTR_IRQ, 0);
> +	POSTING_READ(GEN11_GFX_MSTR_IRQ);
> +
> +	gen11_gt_irq_reset(dev_priv);
> +
> +	I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
> +
> +	for_each_pipe(dev_priv, pipe)
> +		if (intel_display_power_is_enabled(dev_priv,
> +						   POWER_DOMAIN_PIPE(pipe)))
> +			GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
> +
> +	GEN3_IRQ_RESET(GEN8_DE_PORT_);
> +	GEN3_IRQ_RESET(GEN8_DE_MISC_);
> +	GEN3_IRQ_RESET(GEN8_PCU_);
> +}
> +
>   void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>   				     u8 pipe_mask)
>   {
> @@ -3656,6 +3823,41 @@ static int gen8_irq_postinstall(struct drm_device *dev)
>   	return 0;
>   }
>   
> +static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> +	const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
> +
> +	BUILD_BUG_ON(irqs & 0xffff0000);
> +
> +	/* Enable RCS, BCS, VCS and VECS class interrupts. */
> +	I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs);
> +	I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE,	  irqs << 16 | irqs);
> +
> +	/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
> +	I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK,	~(irqs << 16));
> +	I915_WRITE(GEN11_BCS_RSVD_INTR_MASK,	~(irqs << 16));
> +	I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,	~(irqs | irqs << 16));
> +	I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,	~(irqs | irqs << 16));
> +	I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,	~(irqs | irqs << 16));
> +
> +	dev_priv->pm_imr = 0xffffffff; /* TODO */
> +}
> +
> +static int gen11_irq_postinstall(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	gen11_gt_irq_postinstall(dev_priv);
> +	gen8_de_irq_postinstall(dev_priv);
> +
> +	I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
> +
> +	I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
> +	POSTING_READ(GEN11_GFX_MSTR_IRQ);
> +
> +	return 0;
> +}
> +
>   static int cherryview_irq_postinstall(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -4104,6 +4306,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>   		dev->driver->enable_vblank = i965_enable_vblank;
>   		dev->driver->disable_vblank = i965_disable_vblank;
>   		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> +	} else if (INTEL_GEN(dev_priv) >= 11) {
> +		dev->driver->irq_handler = gen11_irq_handler;
> +		dev->driver->irq_preinstall = gen11_irq_reset;
> +		dev->driver->irq_postinstall = gen11_irq_postinstall;
> +		dev->driver->irq_uninstall = gen11_irq_reset;
> +		dev->driver->enable_vblank = gen8_enable_vblank;
> +		dev->driver->disable_vblank = gen8_disable_vblank;
> +		dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
>   	} else if (INTEL_GEN(dev_priv) >= 8) {
>   		dev->driver->irq_handler = gen8_irq_handler;
>   		dev->driver->irq_preinstall = gen8_irq_reset;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d88f107b0d50..087f981461e7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8027,7 +8027,10 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
>   	dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
>   	intel_disable_gt_powersave(dev_priv);
>   
> -	gen6_reset_rps_interrupts(dev_priv);
> +	if (INTEL_GEN(dev_priv) < 11)
> +		gen6_reset_rps_interrupts(dev_priv);
> +	else
> +		WARN_ON_ONCE(1);
>   }
>   
>   static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
> @@ -8140,6 +8143,8 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
>   		cherryview_enable_rps(dev_priv);
>   	} else if (IS_VALLEYVIEW(dev_priv)) {
>   		valleyview_enable_rps(dev_priv);
> +	} else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) {
> +		/* TODO */
>   	} else if (INTEL_GEN(dev_priv) >= 9) {
>   		gen9_enable_rps(dev_priv);
>   	} else if (IS_BROADWELL(dev_priv)) {
> 
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Re: [PATCH 03/20] drm/i915/icl: Show interrupt registers in debugfs

[Daniele Ceraolo Spurio]

On 13/02/18 08:37, Mika Kuoppala wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> v2: Update for POR changes. (Daniele Ceraolo Spurio)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_debugfs.c | 82 ++++++++++++++++++++++++++++++++++++-
>   1 file changed, 81 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 960302668649..49d5bed87798 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -703,6 +703,64 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
>   				   i, I915_READ(GEN8_GT_IER(i)));
>   		}
>   
> +		seq_printf(m, "PCU interrupt mask:\t%08x\n",
> +			   I915_READ(GEN8_PCU_IMR));
> +		seq_printf(m, "PCU interrupt identity:\t%08x\n",
> +			   I915_READ(GEN8_PCU_IIR));
> +		seq_printf(m, "PCU interrupt enable:\t%08x\n",
> +			   I915_READ(GEN8_PCU_IER));
> +	} else if (INTEL_GEN(dev_priv) >= 11) {
> +		seq_printf(m, "Master Interrupt Control:  %08x\n",
> +			   I915_READ(GEN11_GFX_MSTR_IRQ));
> +
> +		seq_printf(m, "Render/Copy Intr Enable:   %08x\n",
> +			   I915_READ(GEN11_RENDER_COPY_INTR_ENABLE));
> +		seq_printf(m, "VCS/VECS Intr Enable:      %08x\n",
> +			   I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
> +		seq_printf(m, "GUC/SG Intr Enable:\t   %08x\n",
> +			   I915_READ(GEN11_GUC_SG_INTR_ENABLE));
> +		seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
> +			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE));
> +		seq_printf(m, "Crypto Intr Enable:\t   %08x\n",
> +			   I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE));
> +		seq_printf(m, "GUnit/CSME Intr Enable:\t   %08x\n",
> +			   I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE));
> +
> +		seq_printf(m, "Display Interrupt Control:\t%08x\n",
> +			   I915_READ(GEN11_DISPLAY_INT_CTL));

 From here onwards the code in this statement is almost identical to the 
one in the GEN8 case, apart from a small difference which I believe can 
be removed (see comment below), so it'd probably be cleaner to move it 
to a common function.

> +
> +		for_each_pipe(dev_priv, pipe) {
> +			if (!intel_display_power_is_enabled(dev_priv,
> +						POWER_DOMAIN_PIPE(pipe))) {

The Gen8 code uses intel_display_power_get_if_enabled(), any reason not 
to do the same here?

Daniele

> +				seq_printf(m, "Pipe %c power disabled\n",
> +					   pipe_name(pipe));
> +				continue;
> +			}
> +			seq_printf(m, "Pipe %c IMR:\t%08x\n",
> +				   pipe_name(pipe),
> +				   I915_READ(GEN8_DE_PIPE_IMR(pipe)));
> +			seq_printf(m, "Pipe %c IIR:\t%08x\n",
> +				   pipe_name(pipe),
> +				   I915_READ(GEN8_DE_PIPE_IIR(pipe)));
> +			seq_printf(m, "Pipe %c IER:\t%08x\n",
> +				   pipe_name(pipe),
> +				   I915_READ(GEN8_DE_PIPE_IER(pipe)));
> +		}
> +
> +		seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
> +			   I915_READ(GEN8_DE_PORT_IMR));
> +		seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
> +			   I915_READ(GEN8_DE_PORT_IIR));
> +		seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
> +			   I915_READ(GEN8_DE_PORT_IER));
> +
> +		seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
> +			   I915_READ(GEN8_DE_MISC_IMR));
> +		seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
> +			   I915_READ(GEN8_DE_MISC_IIR));
> +		seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
> +			   I915_READ(GEN8_DE_MISC_IER));
> +
>   		seq_printf(m, "PCU interrupt mask:\t%08x\n",
>   			   I915_READ(GEN8_PCU_IMR));
>   		seq_printf(m, "PCU interrupt identity:\t%08x\n",
> @@ -846,13 +904,35 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
>   		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
>   			   I915_READ(GTIMR));
>   	}
> -	if (INTEL_GEN(dev_priv) >= 6) {
> +
> +	if (INTEL_GEN(dev_priv) >= 11) {
> +		seq_printf(m, "RCS Intr Mask:\t %08x\n",
> +			   I915_READ(GEN11_RCS0_RSVD_INTR_MASK));
> +		seq_printf(m, "BCS Intr Mask:\t %08x\n",
> +			   I915_READ(GEN11_BCS_RSVD_INTR_MASK));
> +		seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
> +			   I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
> +		seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
> +			   I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
> +		seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
> +			   I915_READ(GEN11_VECS0_VECS1_INTR_MASK));
> +		seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
> +			   I915_READ(GEN11_GUC_SG_INTR_MASK));
> +		seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
> +			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK));
> +		seq_printf(m, "Crypto Intr Mask:\t %08x\n",
> +			   I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK));
> +		seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
> +			   I915_READ(GEN11_GUNIT_CSME_INTR_MASK));
> +
> +	} else if (INTEL_GEN(dev_priv) >= 6) {
>   		for_each_engine(engine, dev_priv, id) {
>   			seq_printf(m,
>   				   "Graphics Interrupt mask (%s):	%08x\n",
>   				   engine->name, I915_READ_IMR(engine));
>   		}
>   	}
> +
>   	intel_runtime_pm_put(dev_priv);
>   
>   	return 0;
> 
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✗ Fi.CI.IGT: failure for ICL GEM enabling (v2)

[Patchwork]

== Series Details ==

Series: ICL GEM enabling (v2)
URL   : https://patchwork.freedesktop.org/series/38174/
State : failure

== Summary ==

Test drv_module_reload:
        Subgroup basic-reload:
                pass       -> DMESG-FAIL (shard-snb)
Test kms_sysfs_edid_timing:
                pass       -> WARN       (shard-apl) fdo#100047
Test kms_flip:
        Subgroup 2x-flip-vs-expired-vblank-interruptible:
                fail       -> PASS       (shard-hsw) fdo#102887 +1
Test kms_cursor_crc:
        Subgroup cursor-64x64-suspend:
                skip       -> PASS       (shard-snb) fdo#102365

fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365

shard-apl        total:3344 pass:1730 dwarn:1   dfail:0   fail:20  skip:1591 time:13824s
shard-hsw        total:3427 pass:1720 dwarn:1   dfail:0   fail:51  skip:1654 time:14731s
shard-snb        total:3330 pass:1312 dwarn:1   dfail:1   fail:9   skip:2007 time:7352s
Blacklisted hosts:
shard-kbl        total:3370 pass:1877 dwarn:1   dfail:0   fail:21  skip:1470 time:10942s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7997/shards.html
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Re: [PATCH 05/20] drm/i915/icl: Interrupt handling

[Oscar Mateo]

On 02/13/2018 11:18 AM, Daniele Ceraolo Spurio wrote:
>
>
> On 13/02/18 08:37, Mika Kuoppala wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> v2: Rebase.
>>
>> v3:
>>    * Remove DPF, it has been removed from SKL+.
>>    * Fix -internal rebase wrt. execlists interrupt handling.
>>
>> v4: Rebase.
>>
>> v5:
>>    * Updated for POR changes. (Daniele Ceraolo Spurio)
>>    * Merged with irq handling fixes by Daniele Ceraolo Spurio:
>>        * Simplify the code by using gen8_cs_irq_handler.
>>        * Fix interrupt handling for the upstream kernel.
>>
>> v6:
>>    * Remove early bringup debug messages (Tvrtko)
>>    * Add NB about arbitrary spin wait timeout (Tvrtko)
>>
>> v7 (from Paulo):
>>    * Don't try to write RO bits to registers.
>>    * Don't check for PCH types that don't exist. PCH interrupts are not
>>      here yet.
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_irq.c | 210 
>> ++++++++++++++++++++++++++++++++++++++++
>>   drivers/gpu/drm/i915/intel_pm.c |   7 +-
>>   2 files changed, 216 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c 
>> b/drivers/gpu/drm/i915/i915_irq.c
>> index b886bd459acc..3a1de4e2a941 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -415,6 +415,9 @@ void gen6_enable_rps_interrupts(struct 
>> drm_i915_private *dev_priv)
>>       if (READ_ONCE(rps->interrupts_enabled))
>>           return;
>>   +    if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
>> +        return;
>> +
>>       spin_lock_irq(&dev_priv->irq_lock);
>>       WARN_ON_ONCE(rps->pm_iir);
>>       WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & 
>> dev_priv->pm_rps_events);
>> @@ -431,6 +434,9 @@ void gen6_disable_rps_interrupts(struct 
>> drm_i915_private *dev_priv)
>>       if (!READ_ONCE(rps->interrupts_enabled))
>>           return;
>>   +    if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
>> +        return;
>> +
>>       spin_lock_irq(&dev_priv->irq_lock);
>>       rps->interrupts_enabled = false;
>>   @@ -2746,6 +2752,131 @@ static void __fini_wedge(struct wedge_me *w)
>>            (W)->i915;                            \
>>            __fini_wedge((W)))
>>   +static __always_inline void
>> +gen11_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
>> +{
>> +    gen8_cs_irq_handler(engine, iir, 0);
>> +}
>> +
>> +static irqreturn_t
>> +gen11_gt_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>> +{
>> +    irqreturn_t ret = IRQ_NONE;
>> +    u16 irq[2][32];
>> +    u32 dw, ident;
>> +    unsigned long tmp;
>> +    unsigned int bank, bit, engine;
>> +    unsigned long wait_start, wait_end;
>> +
>> +    memset(irq, 0, sizeof(irq));
>> +
>> +    for (bank = 0; bank < 2; bank++) {
>> +        if (master_ctl & GEN11_GT_DW_IRQ(bank)) {
>> +            dw = I915_READ_FW(GEN11_GT_INTR_DW(bank));
>> +            if (!dw)
>> +                DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
>> +            tmp = dw;
>> +            for_each_set_bit(bit, &tmp, 32) {
>> +                I915_WRITE_FW(GEN11_IIR_REG_SELECTOR(bank), 1 << bit);
>> +                wait_start = local_clock() >> 10;
>> +                /* NB: Specs do not specify how long to spin wait.
>> +                 * Taking 100us as an educated guess */
>> +                wait_end = wait_start + 100;
>> +                do {
>> +                    ident = 
>> I915_READ_FW(GEN11_INTR_IDENTITY_REG(bank));
>> +                } while (!(ident & GEN11_INTR_DATA_VALID) &&
>> +                     !time_after((unsigned long)local_clock() >> 10, 
>> wait_end));
>
> Patch 18/20 changes this to time_after64 and wait_end to u64, which 
> looks like the correct way to handle this. Since splitting part of 
> this loop out also helps making things cleaner, would it make sense to 
> squash patch 18/20 into this one?
>

Makes sense to me. Tvrtko, what do you think?

>> +
>> +                if (!(ident & GEN11_INTR_DATA_VALID))
>> +                    DRM_ERROR("INTR_IDENTITY_REG%u:%u timed out!\n",
>> +                          bank, bit);
>
> If the data is not valid we should probably skip writing it to the 
> irq[bank][bit] field as we might be writing an incorrect value.
>
>> +
>> +                irq[bank][bit] = ident & GEN11_INTR_ENGINE_MASK;
>> +                if (!irq[bank][bit])
>> +                    DRM_ERROR("INTR_IDENTITY_REG%u:%u blank!\n",
>> +                          bank, bit);
>
> As mentioned on the previous review, I believe it is actually possible 
> to get a blank identity register due to double buffering of interrupts 
> if a second interrupt arrives between reading GT_INTR_DW and reading 
> GEN11_INTR_IDENTITY, as both interrupts will be serviced on the first 
> iteration but GT_INTR_DW will still report the second interrupt after 
> being cleared once. We can just drop the error here as nothing bas 
> should happen afterwards
>
>> + I915_WRITE_FW(GEN11_INTR_IDENTITY_REG(bank), ident);
>> +            }
>> +            I915_WRITE_FW(GEN11_GT_INTR_DW(bank), dw);
>> +        }
>> +    }
>> +
>> +    if (irq[0][GEN11_RCS0]) {
>> +        gen11_cs_irq_handler(dev_priv->engine[RCS],
>> +                     irq[0][GEN11_RCS0]);
>> +        ret = IRQ_HANDLED;
>> +    }
>> +
>> +    if (irq[0][GEN11_BCS]) {
>> +        gen11_cs_irq_handler(dev_priv->engine[BCS],
>> +                     irq[0][GEN11_BCS]);
>> +        ret = IRQ_HANDLED;
>> +    }
>> +
>> +    for (engine = 0; engine < 4; engine++) {
>
> Can we use I915_MAX_VCS here?
>
>> +        if (irq[1][GEN11_VCS(engine)]) {
>> + gen11_cs_irq_handler(dev_priv->engine[_VCS(engine)],
>> +                         irq[1][GEN11_VCS(engine)]);
>> +            ret = IRQ_HANDLED;
>> +        }
>> +    }
>> +
>> +    for (engine = 0; engine < 2; engine++) {
>
> same as above but with I915_MAX_VECS
>
> Thanks,
> Daniele
>
>> +        if (irq[1][GEN11_VECS(engine)]) {
>> + gen11_cs_irq_handler(dev_priv->engine[_VECS(engine)],
>> +                         irq[1][GEN11_VECS(engine)]);
>> +            ret = IRQ_HANDLED;
>> +        }
>> +    }
>> +
>> +    if (irq[0][GEN11_GTPM] & dev_priv->pm_rps_events) {
>> +        ret = IRQ_HANDLED;
>> +        gen6_rps_irq_handler(dev_priv, tmp);
>> +    }
>> +
>> +    return ret;
>> +}
>> +
>> +static irqreturn_t gen11_irq_handler(int irq, void *arg)
>> +{
>> +    struct drm_device *dev = arg;
>> +    struct drm_i915_private *dev_priv = dev->dev_private;
>> +    u32 master_ctl;
>> +    u32 disp_ctl;
>> +    irqreturn_t ret;
>> +
>> +    if (!intel_irqs_enabled(dev_priv))
>> +        return IRQ_NONE;
>> +
>> +    master_ctl = I915_READ_FW(GEN11_GFX_MSTR_IRQ);
>> +
>> +    master_ctl &= ~GEN11_MASTER_IRQ;
>> +    if (!master_ctl)
>> +        return IRQ_NONE;
>> +
>> +    /* Disable interrupts. */
>> +    I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, 0);
>> +
>> +    /* IRQs are synced during runtime_suspend, we don't require a 
>> wakeref */
>> +    disable_rpm_wakeref_asserts(dev_priv);
>> +
>> +    /* Find, clear, then process each source of interrupt. */
>> +    ret = gen11_gt_irq_handler(dev_priv, master_ctl);
>> +
>> +    if (master_ctl & GEN11_DISPLAY_IRQ) {
>> +        disp_ctl = I915_READ_FW(GEN11_DISPLAY_INT_CTL);
>> +        ret |= gen8_de_irq_handler(dev_priv, disp_ctl);
>> +    }
>> +
>> +    /* Acknowledge and enable interrupts. */
>> +    I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
>> +    POSTING_READ_FW(GEN11_GFX_MSTR_IRQ);
>> +
>> +    enable_rpm_wakeref_asserts(dev_priv);
>> +
>> +    return ret;
>> +}
>> +
>>   /**
>>    * i915_reset_device - do process context error handling work
>>    * @dev_priv: i915 device private
>> @@ -3159,6 +3290,42 @@ static void gen8_irq_reset(struct drm_device 
>> *dev)
>>           ibx_irq_reset(dev_priv);
>>   }
>>   +static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
>> +{
>> +    /* Disable RCS, BCS, VCS and VECS class engines. */
>> +    I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0);
>> +    I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE,      0);
>> +
>> +    /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
>> +    I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK,    ~0);
>> +    I915_WRITE(GEN11_BCS_RSVD_INTR_MASK,    ~0);
>> +    I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,    ~0);
>> +    I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,    ~0);
>> +    I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,    ~0);
>> +}
>> +
>> +static void gen11_irq_reset(struct drm_device *dev)
>> +{
>> +    struct drm_i915_private *dev_priv = dev->dev_private;
>> +    int pipe;
>> +
>> +    I915_WRITE(GEN11_GFX_MSTR_IRQ, 0);
>> +    POSTING_READ(GEN11_GFX_MSTR_IRQ);
>> +
>> +    gen11_gt_irq_reset(dev_priv);
>> +
>> +    I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
>> +
>> +    for_each_pipe(dev_priv, pipe)
>> +        if (intel_display_power_is_enabled(dev_priv,
>> +                           POWER_DOMAIN_PIPE(pipe)))
>> +            GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
>> +
>> +    GEN3_IRQ_RESET(GEN8_DE_PORT_);
>> +    GEN3_IRQ_RESET(GEN8_DE_MISC_);
>> +    GEN3_IRQ_RESET(GEN8_PCU_);
>> +}
>> +
>>   void gen8_irq_power_well_post_enable(struct drm_i915_private 
>> *dev_priv,
>>                        u8 pipe_mask)
>>   {
>> @@ -3656,6 +3823,41 @@ static int gen8_irq_postinstall(struct 
>> drm_device *dev)
>>       return 0;
>>   }
>>   +static void gen11_gt_irq_postinstall(struct drm_i915_private 
>> *dev_priv)
>> +{
>> +    const u32 irqs = GT_RENDER_USER_INTERRUPT | 
>> GT_CONTEXT_SWITCH_INTERRUPT;
>> +
>> +    BUILD_BUG_ON(irqs & 0xffff0000);
>> +
>> +    /* Enable RCS, BCS, VCS and VECS class interrupts. */
>> +    I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs);
>> +    I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE,      irqs << 16 | irqs);
>> +
>> +    /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
>> +    I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK,    ~(irqs << 16));
>> +    I915_WRITE(GEN11_BCS_RSVD_INTR_MASK,    ~(irqs << 16));
>> +    I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,    ~(irqs | irqs << 16));
>> +    I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,    ~(irqs | irqs << 16));
>> +    I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,    ~(irqs | irqs << 16));
>> +
>> +    dev_priv->pm_imr = 0xffffffff; /* TODO */
>> +}
>> +
>> +static int gen11_irq_postinstall(struct drm_device *dev)
>> +{
>> +    struct drm_i915_private *dev_priv = dev->dev_private;
>> +
>> +    gen11_gt_irq_postinstall(dev_priv);
>> +    gen8_de_irq_postinstall(dev_priv);
>> +
>> +    I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
>> +
>> +    I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
>> +    POSTING_READ(GEN11_GFX_MSTR_IRQ);
>> +
>> +    return 0;
>> +}
>> +
>>   static int cherryview_irq_postinstall(struct drm_device *dev)
>>   {
>>       struct drm_i915_private *dev_priv = to_i915(dev);
>> @@ -4104,6 +4306,14 @@ void intel_irq_init(struct drm_i915_private 
>> *dev_priv)
>>           dev->driver->enable_vblank = i965_enable_vblank;
>>           dev->driver->disable_vblank = i965_disable_vblank;
>>           dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
>> +    } else if (INTEL_GEN(dev_priv) >= 11) {
>> +        dev->driver->irq_handler = gen11_irq_handler;
>> +        dev->driver->irq_preinstall = gen11_irq_reset;
>> +        dev->driver->irq_postinstall = gen11_irq_postinstall;
>> +        dev->driver->irq_uninstall = gen11_irq_reset;
>> +        dev->driver->enable_vblank = gen8_enable_vblank;
>> +        dev->driver->disable_vblank = gen8_disable_vblank;
>> +        dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
>>       } else if (INTEL_GEN(dev_priv) >= 8) {
>>           dev->driver->irq_handler = gen8_irq_handler;
>>           dev->driver->irq_preinstall = gen8_irq_reset;
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c 
>> b/drivers/gpu/drm/i915/intel_pm.c
>> index d88f107b0d50..087f981461e7 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -8027,7 +8027,10 @@ void intel_sanitize_gt_powersave(struct 
>> drm_i915_private *dev_priv)
>>       dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
>>       intel_disable_gt_powersave(dev_priv);
>>   -    gen6_reset_rps_interrupts(dev_priv);
>> +    if (INTEL_GEN(dev_priv) < 11)
>> +        gen6_reset_rps_interrupts(dev_priv);
>> +    else
>> +        WARN_ON_ONCE(1);
>>   }
>>     static inline void intel_disable_llc_pstate(struct 
>> drm_i915_private *i915)
>> @@ -8140,6 +8143,8 @@ static void intel_enable_rps(struct 
>> drm_i915_private *dev_priv)
>>           cherryview_enable_rps(dev_priv);
>>       } else if (IS_VALLEYVIEW(dev_priv)) {
>>           valleyview_enable_rps(dev_priv);
>> +    } else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) {
>> +        /* TODO */
>>       } else if (INTEL_GEN(dev_priv) >= 9) {
>>           gen9_enable_rps(dev_priv);
>>       } else if (IS_BROADWELL(dev_priv)) {
>>

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Re: [PATCH 05/20] drm/i915/icl: Interrupt handling

[Chris Wilson]

Quoting Oscar Mateo (2018-02-13 21:56:32)
> 
> 
> On 02/13/2018 11:18 AM, Daniele Ceraolo Spurio wrote:
> >
> >
> > On 13/02/18 08:37, Mika Kuoppala wrote:
> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >> +static irqreturn_t
> >> +gen11_gt_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> >> +{
> >> +    irqreturn_t ret = IRQ_NONE;
> >> +    u16 irq[2][32];
> >> +    u32 dw, ident;
> >> +    unsigned long tmp;
> >> +    unsigned int bank, bit, engine;
> >> +    unsigned long wait_start, wait_end;
> >> +
> >> +    memset(irq, 0, sizeof(irq));
> >> +
> >> +    for (bank = 0; bank < 2; bank++) {
> >> +        if (master_ctl & GEN11_GT_DW_IRQ(bank)) {
> >> +            dw = I915_READ_FW(GEN11_GT_INTR_DW(bank));
> >> +            if (!dw)
> >> +                DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
> >> +            tmp = dw;
> >> +            for_each_set_bit(bit, &tmp, 32) {
> >> +                I915_WRITE_FW(GEN11_IIR_REG_SELECTOR(bank), 1 << bit);
> >> +                wait_start = local_clock() >> 10;
> >> +                /* NB: Specs do not specify how long to spin wait.
> >> +                 * Taking 100us as an educated guess */
> >> +                wait_end = wait_start + 100;
> >> +                do {
> >> +                    ident = 
> >> I915_READ_FW(GEN11_INTR_IDENTITY_REG(bank));
> >> +                } while (!(ident & GEN11_INTR_DATA_VALID) &&
> >> +                     !time_after((unsigned long)local_clock() >> 10, 
> >> wait_end));
> >
> > Patch 18/20 changes this to time_after64 and wait_end to u64, which 
> > looks like the correct way to handle this. Since splitting part of 
> > this loop out also helps making things cleaner, would it make sense to 
> > squash patch 18/20 into this one?
> >
> 
> Makes sense to me. Tvrtko, what do you think?

The squash should be made, but time_after64 is no more correct since the
native 32b/64b wrapped arithmetic is accurate. So what can be done here
is remove the casts and use time_after32() if we truly cared.
-Chris
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Re: [PATCH 03/20] drm/i915/icl: Show interrupt registers in debugfs

[Mika Kuoppala]

Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> writes:

> On 13/02/18 08:37, Mika Kuoppala wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> 
>> v2: Update for POR changes. (Daniele Ceraolo Spurio)
>> 
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Cc: Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_debugfs.c | 82 ++++++++++++++++++++++++++++++++++++-
>>   1 file changed, 81 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index 960302668649..49d5bed87798 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -703,6 +703,64 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
>>   				   i, I915_READ(GEN8_GT_IER(i)));
>>   		}
>>   
>> +		seq_printf(m, "PCU interrupt mask:\t%08x\n",
>> +			   I915_READ(GEN8_PCU_IMR));
>> +		seq_printf(m, "PCU interrupt identity:\t%08x\n",
>> +			   I915_READ(GEN8_PCU_IIR));
>> +		seq_printf(m, "PCU interrupt enable:\t%08x\n",
>> +			   I915_READ(GEN8_PCU_IER));
>> +	} else if (INTEL_GEN(dev_priv) >= 11) {
>> +		seq_printf(m, "Master Interrupt Control:  %08x\n",
>> +			   I915_READ(GEN11_GFX_MSTR_IRQ));
>> +
>> +		seq_printf(m, "Render/Copy Intr Enable:   %08x\n",
>> +			   I915_READ(GEN11_RENDER_COPY_INTR_ENABLE));
>> +		seq_printf(m, "VCS/VECS Intr Enable:      %08x\n",
>> +			   I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
>> +		seq_printf(m, "GUC/SG Intr Enable:\t   %08x\n",
>> +			   I915_READ(GEN11_GUC_SG_INTR_ENABLE));
>> +		seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
>> +			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE));
>> +		seq_printf(m, "Crypto Intr Enable:\t   %08x\n",
>> +			   I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE));
>> +		seq_printf(m, "GUnit/CSME Intr Enable:\t   %08x\n",
>> +			   I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE));
>> +
>> +		seq_printf(m, "Display Interrupt Control:\t%08x\n",
>> +			   I915_READ(GEN11_DISPLAY_INT_CTL));
>
>  From here onwards the code in this statement is almost identical to the 
> one in the GEN8 case, apart from a small difference which I believe can 
> be removed (see comment below), so it'd probably be cleaner to move it 
> to a common function.
>
>> +
>> +		for_each_pipe(dev_priv, pipe) {
>> +			if (!intel_display_power_is_enabled(dev_priv,
>> +						POWER_DOMAIN_PIPE(pipe))) {
>
> The Gen8 code uses intel_display_power_get_if_enabled(), any reason not 
> to do the same here?

We need the ref while we poke the registers, so the get_if_enabled
variant should be used. I will make a common function out of these
as you suggested.

With Tvrtko's permission, I have adopted this and the interrupt
patches. So I will post update patch soon.

-Mika

>
> Daniele
>
>> +				seq_printf(m, "Pipe %c power disabled\n",
>> +					   pipe_name(pipe));
>> +				continue;
>> +			}
>> +			seq_printf(m, "Pipe %c IMR:\t%08x\n",
>> +				   pipe_name(pipe),
>> +				   I915_READ(GEN8_DE_PIPE_IMR(pipe)));
>> +			seq_printf(m, "Pipe %c IIR:\t%08x\n",
>> +				   pipe_name(pipe),
>> +				   I915_READ(GEN8_DE_PIPE_IIR(pipe)));
>> +			seq_printf(m, "Pipe %c IER:\t%08x\n",
>> +				   pipe_name(pipe),
>> +				   I915_READ(GEN8_DE_PIPE_IER(pipe)));
>> +		}
>> +
>> +		seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
>> +			   I915_READ(GEN8_DE_PORT_IMR));
>> +		seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
>> +			   I915_READ(GEN8_DE_PORT_IIR));
>> +		seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
>> +			   I915_READ(GEN8_DE_PORT_IER));
>> +
>> +		seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
>> +			   I915_READ(GEN8_DE_MISC_IMR));
>> +		seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
>> +			   I915_READ(GEN8_DE_MISC_IIR));
>> +		seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
>> +			   I915_READ(GEN8_DE_MISC_IER));
>> +
>>   		seq_printf(m, "PCU interrupt mask:\t%08x\n",
>>   			   I915_READ(GEN8_PCU_IMR));
>>   		seq_printf(m, "PCU interrupt identity:\t%08x\n",
>> @@ -846,13 +904,35 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
>>   		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
>>   			   I915_READ(GTIMR));
>>   	}
>> -	if (INTEL_GEN(dev_priv) >= 6) {
>> +
>> +	if (INTEL_GEN(dev_priv) >= 11) {
>> +		seq_printf(m, "RCS Intr Mask:\t %08x\n",
>> +			   I915_READ(GEN11_RCS0_RSVD_INTR_MASK));
>> +		seq_printf(m, "BCS Intr Mask:\t %08x\n",
>> +			   I915_READ(GEN11_BCS_RSVD_INTR_MASK));
>> +		seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
>> +			   I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
>> +		seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
>> +			   I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
>> +		seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
>> +			   I915_READ(GEN11_VECS0_VECS1_INTR_MASK));
>> +		seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
>> +			   I915_READ(GEN11_GUC_SG_INTR_MASK));
>> +		seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
>> +			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK));
>> +		seq_printf(m, "Crypto Intr Mask:\t %08x\n",
>> +			   I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK));
>> +		seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
>> +			   I915_READ(GEN11_GUNIT_CSME_INTR_MASK));
>> +
>> +	} else if (INTEL_GEN(dev_priv) >= 6) {
>>   		for_each_engine(engine, dev_priv, id) {
>>   			seq_printf(m,
>>   				   "Graphics Interrupt mask (%s):	%08x\n",
>>   				   engine->name, I915_READ_IMR(engine));
>>   		}
>>   	}
>> +
>>   	intel_runtime_pm_put(dev_priv);
>>   
>>   	return 0;
>> 
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[PATCH 03/20] drm/i915/icl: Show interrupt registers in debugfs

[Mika Kuoppala]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Show GEN11 specific interrupt registers in debugfs

v2: Update for POR changes. (Daniele Ceraolo Spurio)
v3: get runtime pm ref. unify common parts with gen8 (Daniele)

Cc: Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 139 ++++++++++++++++++++++++------------
 1 file changed, 95 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 960302668649..7e1d08b64fab 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -646,6 +646,56 @@ static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 	return 0;
 }
 
+static void gen8_display_interrupt_info(struct seq_file *m)
+{
+	struct drm_i915_private *dev_priv = node_to_i915(m->private);
+	int pipe;
+
+	for_each_pipe(dev_priv, pipe) {
+		enum intel_display_power_domain power_domain;
+
+		power_domain = POWER_DOMAIN_PIPE(pipe);
+		if (!intel_display_power_get_if_enabled(dev_priv,
+							power_domain)) {
+			seq_printf(m, "Pipe %c power disabled\n",
+				   pipe_name(pipe));
+			continue;
+		}
+		seq_printf(m, "Pipe %c IMR:\t%08x\n",
+			   pipe_name(pipe),
+			   I915_READ(GEN8_DE_PIPE_IMR(pipe)));
+		seq_printf(m, "Pipe %c IIR:\t%08x\n",
+			   pipe_name(pipe),
+			   I915_READ(GEN8_DE_PIPE_IIR(pipe)));
+		seq_printf(m, "Pipe %c IER:\t%08x\n",
+			   pipe_name(pipe),
+			   I915_READ(GEN8_DE_PIPE_IER(pipe)));
+
+		intel_display_power_put(dev_priv, power_domain);
+	}
+
+	seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
+		   I915_READ(GEN8_DE_PORT_IMR));
+	seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
+		   I915_READ(GEN8_DE_PORT_IIR));
+	seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
+		   I915_READ(GEN8_DE_PORT_IER));
+
+	seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
+		   I915_READ(GEN8_DE_MISC_IMR));
+	seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
+		   I915_READ(GEN8_DE_MISC_IIR));
+	seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
+		   I915_READ(GEN8_DE_MISC_IER));
+
+	seq_printf(m, "PCU interrupt mask:\t%08x\n",
+		   I915_READ(GEN8_PCU_IMR));
+	seq_printf(m, "PCU interrupt identity:\t%08x\n",
+		   I915_READ(GEN8_PCU_IIR));
+	seq_printf(m, "PCU interrupt enable:\t%08x\n",
+		   I915_READ(GEN8_PCU_IER));
+}
+
 static int i915_interrupt_info(struct seq_file *m, void *data)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -709,6 +759,27 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 			   I915_READ(GEN8_PCU_IIR));
 		seq_printf(m, "PCU interrupt enable:\t%08x\n",
 			   I915_READ(GEN8_PCU_IER));
+	} else if (INTEL_GEN(dev_priv) >= 11) {
+		seq_printf(m, "Master Interrupt Control:  %08x\n",
+			   I915_READ(GEN11_GFX_MSTR_IRQ));
+
+		seq_printf(m, "Render/Copy Intr Enable:   %08x\n",
+			   I915_READ(GEN11_RENDER_COPY_INTR_ENABLE));
+		seq_printf(m, "VCS/VECS Intr Enable:      %08x\n",
+			   I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
+		seq_printf(m, "GUC/SG Intr Enable:\t   %08x\n",
+			   I915_READ(GEN11_GUC_SG_INTR_ENABLE));
+		seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
+			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE));
+		seq_printf(m, "Crypto Intr Enable:\t   %08x\n",
+			   I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE));
+		seq_printf(m, "GUnit/CSME Intr Enable:\t   %08x\n",
+			   I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE));
+
+		seq_printf(m, "Display Interrupt Control:\t%08x\n",
+			   I915_READ(GEN11_DISPLAY_INT_CTL));
+
+		gen8_display_interrupt_info(m);
 	} else if (INTEL_GEN(dev_priv) >= 8) {
 		seq_printf(m, "Master Interrupt Control:\t%08x\n",
 			   I915_READ(GEN8_MASTER_IRQ));
@@ -722,49 +793,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 				   i, I915_READ(GEN8_GT_IER(i)));
 		}
 
-		for_each_pipe(dev_priv, pipe) {
-			enum intel_display_power_domain power_domain;
-
-			power_domain = POWER_DOMAIN_PIPE(pipe);
-			if (!intel_display_power_get_if_enabled(dev_priv,
-								power_domain)) {
-				seq_printf(m, "Pipe %c power disabled\n",
-					   pipe_name(pipe));
-				continue;
-			}
-			seq_printf(m, "Pipe %c IMR:\t%08x\n",
-				   pipe_name(pipe),
-				   I915_READ(GEN8_DE_PIPE_IMR(pipe)));
-			seq_printf(m, "Pipe %c IIR:\t%08x\n",
-				   pipe_name(pipe),
-				   I915_READ(GEN8_DE_PIPE_IIR(pipe)));
-			seq_printf(m, "Pipe %c IER:\t%08x\n",
-				   pipe_name(pipe),
-				   I915_READ(GEN8_DE_PIPE_IER(pipe)));
-
-			intel_display_power_put(dev_priv, power_domain);
-		}
-
-		seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
-			   I915_READ(GEN8_DE_PORT_IMR));
-		seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
-			   I915_READ(GEN8_DE_PORT_IIR));
-		seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
-			   I915_READ(GEN8_DE_PORT_IER));
-
-		seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
-			   I915_READ(GEN8_DE_MISC_IMR));
-		seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
-			   I915_READ(GEN8_DE_MISC_IIR));
-		seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
-			   I915_READ(GEN8_DE_MISC_IER));
-
-		seq_printf(m, "PCU interrupt mask:\t%08x\n",
-			   I915_READ(GEN8_PCU_IMR));
-		seq_printf(m, "PCU interrupt identity:\t%08x\n",
-			   I915_READ(GEN8_PCU_IIR));
-		seq_printf(m, "PCU interrupt enable:\t%08x\n",
-			   I915_READ(GEN8_PCU_IER));
+		gen8_display_interrupt_info(m);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
 		seq_printf(m, "Display IER:\t%08x\n",
 			   I915_READ(VLV_IER));
@@ -846,13 +875,35 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
 			   I915_READ(GTIMR));
 	}
-	if (INTEL_GEN(dev_priv) >= 6) {
+
+	if (INTEL_GEN(dev_priv) >= 11) {
+		seq_printf(m, "RCS Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_RCS0_RSVD_INTR_MASK));
+		seq_printf(m, "BCS Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_BCS_RSVD_INTR_MASK));
+		seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
+		seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
+		seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_VECS0_VECS1_INTR_MASK));
+		seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_GUC_SG_INTR_MASK));
+		seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
+			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK));
+		seq_printf(m, "Crypto Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK));
+		seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
+			   I915_READ(GEN11_GUNIT_CSME_INTR_MASK));
+
+	} else if (INTEL_GEN(dev_priv) >= 6) {
 		for_each_engine(engine, dev_priv, id) {
 			seq_printf(m,
 				   "Graphics Interrupt mask (%s):	%08x\n",
 				   engine->name, I915_READ_IMR(engine));
 		}
 	}
+
 	intel_runtime_pm_put(dev_priv);
 
 	return 0;
-- 
2.14.1

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✗ Fi.CI.CHECKPATCH: warning for ICL GEM enabling (v2) (rev2)

[Patchwork]

== Series Details ==

Series: ICL GEM enabling (v2) (rev2)
URL   : https://patchwork.freedesktop.org/series/38174/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
e3d750591349 drm/i915/icl: Add the ICL PCI IDs
-:47: ERROR: Macros with complex values should be enclosed in parentheses
#47: FILE: include/drm/i915_pciids.h:434:
+#define INTEL_ICL_11_IDS(info) \
+	INTEL_VGA_DEVICE(0x8A50, info), \
+	INTEL_VGA_DEVICE(0x8A51, info), \
+	INTEL_VGA_DEVICE(0x8A5C, info), \
+	INTEL_VGA_DEVICE(0x8A5D, info), \
+	INTEL_VGA_DEVICE(0x8A52, info), \
+	INTEL_VGA_DEVICE(0x8A5A, info), \
+	INTEL_VGA_DEVICE(0x8A5B, info), \
+	INTEL_VGA_DEVICE(0x8A71, info), \
+	INTEL_VGA_DEVICE(0x8A70, info)

-:47: CHECK: Macro argument reuse 'info' - possible side-effects?
#47: FILE: include/drm/i915_pciids.h:434:
+#define INTEL_ICL_11_IDS(info) \
+	INTEL_VGA_DEVICE(0x8A50, info), \
+	INTEL_VGA_DEVICE(0x8A51, info), \
+	INTEL_VGA_DEVICE(0x8A5C, info), \
+	INTEL_VGA_DEVICE(0x8A5D, info), \
+	INTEL_VGA_DEVICE(0x8A52, info), \
+	INTEL_VGA_DEVICE(0x8A5A, info), \
+	INTEL_VGA_DEVICE(0x8A5B, info), \
+	INTEL_VGA_DEVICE(0x8A71, info), \
+	INTEL_VGA_DEVICE(0x8A70, info)

total: 1 errors, 0 warnings, 1 checks, 23 lines checked
d75493c4335d drm/i915/icl: add icelake_init_clock_gating()
-:22: CHECK: Blank lines aren't necessary after an open brace '{'
#22: FILE: drivers/gpu/drm/i915/intel_pm.c:8498:
+{
+

-:23: CHECK: Blank lines aren't necessary before a close brace '}'
#23: FILE: drivers/gpu/drm/i915/intel_pm.c:8499:
+
+}

total: 0 errors, 0 warnings, 2 checks, 21 lines checked
048837d73700 drm/i915/icl: Show interrupt registers in debugfs
145a0e361111 drm/i915/icl: Prepare for more rings
21129ec5a1e2 drm/i915/icl: Interrupt handling
-:88: WARNING: line over 80 characters
#88: FILE: drivers/gpu/drm/i915/i915_irq.c:2780:
+				I915_WRITE_FW(GEN11_IIR_REG_SELECTOR(bank), 1 << bit);

-:90: WARNING: line over 80 characters
#90: FILE: drivers/gpu/drm/i915/i915_irq.c:2782:
+				/* NB: Specs do not specify how long to spin wait.

-:91: WARNING: Block comments use a trailing */ on a separate line
#91: FILE: drivers/gpu/drm/i915/i915_irq.c:2783:
+				 * Taking 100us as an educated guess */

-:94: WARNING: line over 80 characters
#94: FILE: drivers/gpu/drm/i915/i915_irq.c:2786:
+					ident = I915_READ_FW(GEN11_INTR_IDENTITY_REG(bank));

-:96: WARNING: line over 80 characters
#96: FILE: drivers/gpu/drm/i915/i915_irq.c:2788:
+					 !time_after((unsigned long)local_clock() >> 10, wait_end));

-:99: WARNING: line over 80 characters
#99: FILE: drivers/gpu/drm/i915/i915_irq.c:2791:
+					DRM_ERROR("INTR_IDENTITY_REG%u:%u timed out!\n",

-:104: WARNING: line over 80 characters
#104: FILE: drivers/gpu/drm/i915/i915_irq.c:2796:
+					DRM_ERROR("INTR_IDENTITY_REG%u:%u blank!\n",

-:106: WARNING: line over 80 characters
#106: FILE: drivers/gpu/drm/i915/i915_irq.c:2798:
+				I915_WRITE_FW(GEN11_INTR_IDENTITY_REG(bank), ident);

total: 0 errors, 8 warnings, 0 checks, 265 lines checked
35e3bee64402 drm/i915/icl: Ringbuffer interrupt handling
f3825b9b7935 drm/i915/icl: Correctly initialize the Gen11 engines
e535dcb288c4 drm/i915/icl: new context descriptor support
-:37: CHECK: spaces preferred around that '<<' (ctx:VxV)
#37: FILE: drivers/gpu/drm/i915/i915_drv.h:2099:
+#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
                                   ^

-:37: CHECK: Prefer using the BIT macro
#37: FILE: drivers/gpu/drm/i915/i915_drv.h:2099:
+#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */

-:121: CHECK: spaces preferred around that '<<' (ctx:VxV)
#121: FILE: drivers/gpu/drm/i915/intel_lrc.c:211:
+	BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (1<<GEN11_SW_CTX_ID_WIDTH));
 	                                         ^

total: 0 errors, 0 warnings, 3 checks, 92 lines checked
ea7cec009f3b drm/i915/icl: Enhanced execution list support
-:81: WARNING: line over 80 characters
#81: FILE: drivers/gpu/drm/i915/intel_lrc.c:402:
+static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)

-:87: WARNING: line over 80 characters
#87: FILE: drivers/gpu/drm/i915/intel_lrc.c:406:
+		writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1);

-:199: WARNING: line over 80 characters
#199: FILE: drivers/gpu/drm/i915/intel_lrc.h:45:
+#define RING_EXECLIST_SQ_CONTENTS(engine)	_MMIO((engine)->mmio_base + 0x510)

-:200: WARNING: line over 80 characters
#200: FILE: drivers/gpu/drm/i915/intel_lrc.h:46:
+#define RING_EXECLIST_CONTROL(engine)		_MMIO((engine)->mmio_base + 0x550)

-:201: CHECK: Prefer using the BIT macro
#201: FILE: drivers/gpu/drm/i915/intel_lrc.h:47:
+#define	  EL_CTRL_LOAD				(1 << 0)

total: 0 errors, 4 warnings, 1 checks, 161 lines checked
c3f217cfec40 drm/i915/icl: Add Indirect Context Offset for Gen11
96cf65e43227 drm/i915/icl: Gen11 forcewake support
-:81: CHECK: Macro argument reuse 'reg' - possible side-effects?
#81: FILE: drivers/gpu/drm/i915/intel_uncore.c:783:
+#define GEN11_NEEDS_FORCE_WAKE(reg) \
+	((reg) < 0x40000 || ((reg) >= 0x1c0000 && (reg) < 0x1dc000))

-:106: CHECK: Macro argument reuse 'offset' - possible side-effects?
#106: FILE: drivers/gpu/drm/i915/intel_uncore.c:880:
+#define __gen11_fwtable_reg_read_fw_domains(offset) \
+({ \
+	enum forcewake_domains __fwd = 0; \
+	if (GEN11_NEEDS_FORCE_WAKE((offset))) \
+		__fwd = find_fw_domain(dev_priv, offset); \
+	__fwd; \
+})

-:166: CHECK: Macro argument reuse 'offset' - possible side-effects?
#166: FILE: drivers/gpu/drm/i915/intel_uncore.c:974:
+#define __gen11_fwtable_reg_write_fw_domains(offset) \
+({ \
+	enum forcewake_domains __fwd = 0; \
+	if (GEN11_NEEDS_FORCE_WAKE((offset)) && !is_gen11_shadowed(offset)) \
+		__fwd = find_fw_domain(dev_priv, offset); \
+	__fwd; \
+})

-:263: WARNING: line over 80 characters
#263: FILE: drivers/gpu/drm/i915/intel_uncore.c:1338:
+	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0));

-:264: WARNING: line over 80 characters
#264: FILE: drivers/gpu/drm/i915/intel_uncore.c:1339:
+	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1));

-:265: WARNING: line over 80 characters
#265: FILE: drivers/gpu/drm/i915/intel_uncore.c:1340:
+	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2));

-:266: WARNING: line over 80 characters
#266: FILE: drivers/gpu/drm/i915/intel_uncore.c:1341:
+	BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3));

-:267: WARNING: line over 80 characters
#267: FILE: drivers/gpu/drm/i915/intel_uncore.c:1342:
+	BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0));

-:268: WARNING: line over 80 characters
#268: FILE: drivers/gpu/drm/i915/intel_uncore.c:1343:
+	BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1));

total: 0 errors, 6 warnings, 3 checks, 360 lines checked
505af6b68524 drm/i915/icl: Check for fused-off VDBOX and VEBOX instances
-:8: WARNING: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#8: 
each VDBOX and VEBOX has its own power well, which only exist if the related

-:34: ERROR: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 33def1ff7b09 ("drm/i915: Simplify intel_engines_init")'
#34: 
    commit 33def1ff7b0 ("drm/i915: Simplify intel_engines_init")

total: 1 errors, 1 warnings, 0 checks, 83 lines checked
507d86de0ad8 drm/i915/icl: Enable the extra video decode and enhancement boxes for Icelake 11
a92d8fb69ff7 drm/i915/icl: Update subslice define for ICL 11
-:44: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#44: FILE: drivers/gpu/drm/i915/intel_engine_cs.c:781:
+	uint32_t mcr_slice_subslice_mask;

-:45: CHECK: Prefer kernel type 'u32' over 'uint32_t'
#45: FILE: drivers/gpu/drm/i915/intel_engine_cs.c:782:
+	uint32_t mcr_slice_subslice_select;

total: 0 errors, 0 warnings, 2 checks, 60 lines checked
5d1119aba0bb drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
d1a20b90b203 drm/i915/icl: Add reset control register changes
-:35: CHECK: Prefer using the BIT macro
#35: FILE: drivers/gpu/drm/i915/i915_reg.h:310:
+#define  GEN11_GRDOM_BLT		(1 << 2)

-:36: CHECK: Prefer using the BIT macro
#36: FILE: drivers/gpu/drm/i915/i915_reg.h:311:
+#define  GEN11_GRDOM_GUC		(1 << 3)

-:37: CHECK: Prefer using the BIT macro
#37: FILE: drivers/gpu/drm/i915/i915_reg.h:312:
+#define  GEN11_GRDOM_MEDIA		(1 << 5)

-:38: CHECK: Prefer using the BIT macro
#38: FILE: drivers/gpu/drm/i915/i915_reg.h:313:
+#define  GEN11_GRDOM_MEDIA2		(1 << 6)

-:39: CHECK: Prefer using the BIT macro
#39: FILE: drivers/gpu/drm/i915/i915_reg.h:314:
+#define  GEN11_GRDOM_MEDIA3		(1 << 7)

-:40: CHECK: Prefer using the BIT macro
#40: FILE: drivers/gpu/drm/i915/i915_reg.h:315:
+#define  GEN11_GRDOM_MEDIA4		(1 << 8)

-:41: CHECK: Prefer using the BIT macro
#41: FILE: drivers/gpu/drm/i915/i915_reg.h:316:
+#define  GEN11_GRDOM_VECS		(1 << 13)

-:42: CHECK: Prefer using the BIT macro
#42: FILE: drivers/gpu/drm/i915/i915_reg.h:317:
+#define  GEN11_GRDOM_VECS2		(1 << 14)

-:67: WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
#67: FILE: drivers/gpu/drm/i915/intel_uncore.c:1870:
+			       unsigned engine_mask)

total: 0 errors, 1 warnings, 8 checks, 93 lines checked
d69bf1391650 drm/i915/icl: Add configuring MOCS in new Icelake engines
-:6: WARNING: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#6: 
In Icelake, there are more engines on which Memory Object Control States need

total: 0 errors, 1 warnings, 0 checks, 25 lines checked
69f0d8dbe77e drm/i915/icl: Split out the servicing of the Selector and Shared IIR registers
-:100: WARNING: line over 80 characters
#100: FILE: drivers/gpu/drm/i915/i915_irq.c:2811:
+					gen11_service_shared_iir(dev_priv, bank, bit);

total: 0 errors, 1 warnings, 0 checks, 78 lines checked
feef482fb7f3 drm/i915/icl: Handle RPS interrupts correctly for Gen11
-:92: WARNING: line over 80 characters
#92: FILE: drivers/gpu/drm/i915/i915_irq.c:488:
+		WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);

total: 0 errors, 1 warnings, 0 checks, 148 lines checked
2a584d53b971 drm/i915/icl: Enable RC6 and RPS in Gen11
-:58: WARNING: line over 80 characters
#58: FILE: drivers/gpu/drm/i915/i915_debugfs.c:1831:
+						      INTEL_GEN(dev_priv) >= 10 ?

total: 0 errors, 1 warnings, 0 checks, 79 lines checked

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Re: [PATCH 05/20] drm/i915/icl: Interrupt handling

[Mika Kuoppala]

Mika Kuoppala <mika.kuoppala@linux.intel.com> writes:

> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> v2: Rebase.
>
> v3:
>   * Remove DPF, it has been removed from SKL+.
>   * Fix -internal rebase wrt. execlists interrupt handling.
>
> v4: Rebase.
>
> v5:
>   * Updated for POR changes. (Daniele Ceraolo Spurio)
>   * Merged with irq handling fixes by Daniele Ceraolo Spurio:
>       * Simplify the code by using gen8_cs_irq_handler.
>       * Fix interrupt handling for the upstream kernel.
>
> v6:
>   * Remove early bringup debug messages (Tvrtko)
>   * Add NB about arbitrary spin wait timeout (Tvrtko)
>
> v7 (from Paulo):
>   * Don't try to write RO bits to registers.
>   * Don't check for PCH types that don't exist. PCH interrupts are not
>     here yet.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 210 ++++++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_pm.c |   7 +-
>  2 files changed, 216 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b886bd459acc..3a1de4e2a941 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -415,6 +415,9 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
>  	if (READ_ONCE(rps->interrupts_enabled))
>  		return;
>  
> +	if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
> +		return;
> +
>  	spin_lock_irq(&dev_priv->irq_lock);
>  	WARN_ON_ONCE(rps->pm_iir);
>  	WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
> @@ -431,6 +434,9 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
>  	if (!READ_ONCE(rps->interrupts_enabled))
>  		return;
>  
> +	if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
> +		return;
> +
>  	spin_lock_irq(&dev_priv->irq_lock);
>  	rps->interrupts_enabled = false;
>  
> @@ -2746,6 +2752,131 @@ static void __fini_wedge(struct wedge_me *w)
>  	     (W)->i915;							\
>  	     __fini_wedge((W)))
>  
> +static __always_inline void
> +gen11_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
> +{
> +	gen8_cs_irq_handler(engine, iir, 0);
> +}
> +
> +static irqreturn_t
> +gen11_gt_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> +{
> +	irqreturn_t ret = IRQ_NONE;
> +	u16 irq[2][32];
> +	u32 dw, ident;
> +	unsigned long tmp;
> +	unsigned int bank, bit, engine;
> +	unsigned long wait_start, wait_end;
> +
> +	memset(irq, 0, sizeof(irq));
> +
> +	for (bank = 0; bank < 2; bank++) {
> +		if (master_ctl & GEN11_GT_DW_IRQ(bank)) {
> +			dw = I915_READ_FW(GEN11_GT_INTR_DW(bank));
> +			if (!dw)
> +				DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
> +			tmp = dw;
> +			for_each_set_bit(bit, &tmp, 32) {
> +				I915_WRITE_FW(GEN11_IIR_REG_SELECTOR(bank), 1 << bit);
> +				wait_start = local_clock() >> 10;
> +				/* NB: Specs do not specify how long to spin wait.
> +				 * Taking 100us as an educated guess */
> +				wait_end = wait_start + 100;
> +				do {
> +					ident = I915_READ_FW(GEN11_INTR_IDENTITY_REG(bank));
> +				} while (!(ident & GEN11_INTR_DATA_VALID) &&
> +					 !time_after((unsigned long)local_clock() >> 10, wait_end));
> +
> +				if (!(ident & GEN11_INTR_DATA_VALID))
> +					DRM_ERROR("INTR_IDENTITY_REG%u:%u timed out!\n",
> +						  bank, bit);
> +
> +				irq[bank][bit] = ident & GEN11_INTR_ENGINE_MASK;
> +				if (!irq[bank][bit])
> +					DRM_ERROR("INTR_IDENTITY_REG%u:%u blank!\n",
> +						  bank, bit);
> +				I915_WRITE_FW(GEN11_INTR_IDENTITY_REG(bank), ident);
> +			}
> +			I915_WRITE_FW(GEN11_GT_INTR_DW(bank), dw);
> +		}
> +	}
> +
> +	if (irq[0][GEN11_RCS0]) {
> +		gen11_cs_irq_handler(dev_priv->engine[RCS],
> +				     irq[0][GEN11_RCS0]);
> +		ret = IRQ_HANDLED;
> +	}
> +
> +	if (irq[0][GEN11_BCS]) {
> +		gen11_cs_irq_handler(dev_priv->engine[BCS],
> +				     irq[0][GEN11_BCS]);
> +		ret = IRQ_HANDLED;
> +	}
> +
> +	for (engine = 0; engine < 4; engine++) {
> +		if (irq[1][GEN11_VCS(engine)]) {
> +			gen11_cs_irq_handler(dev_priv->engine[_VCS(engine)],
> +					     irq[1][GEN11_VCS(engine)]);
> +			ret = IRQ_HANDLED;
> +		}
> +	}
> +
> +	for (engine = 0; engine < 2; engine++) {
> +		if (irq[1][GEN11_VECS(engine)]) {
> +			gen11_cs_irq_handler(dev_priv->engine[_VECS(engine)],
> +					     irq[1][GEN11_VECS(engine)]);
> +			ret = IRQ_HANDLED;
> +		}
> +	}
> +
> +	if (irq[0][GEN11_GTPM] & dev_priv->pm_rps_events) {
> +		ret = IRQ_HANDLED;
> +		gen6_rps_irq_handler(dev_priv, tmp);

This tmp in here looks like it can't be right.
-Mika

> +	}
> +
> +	return ret;
> +}
> +
> +static irqreturn_t gen11_irq_handler(int irq, void *arg)
> +{
> +	struct drm_device *dev = arg;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 master_ctl;
> +	u32 disp_ctl;
> +	irqreturn_t ret;
> +
> +	if (!intel_irqs_enabled(dev_priv))
> +		return IRQ_NONE;
> +
> +	master_ctl = I915_READ_FW(GEN11_GFX_MSTR_IRQ);
> +
> +	master_ctl &= ~GEN11_MASTER_IRQ;
> +	if (!master_ctl)
> +		return IRQ_NONE;
> +
> +	/* Disable interrupts. */
> +	I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, 0);
> +
> +	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
> +	disable_rpm_wakeref_asserts(dev_priv);
> +
> +	/* Find, clear, then process each source of interrupt. */
> +	ret = gen11_gt_irq_handler(dev_priv, master_ctl);
> +
> +	if (master_ctl & GEN11_DISPLAY_IRQ) {
> +		disp_ctl = I915_READ_FW(GEN11_DISPLAY_INT_CTL);
> +		ret |= gen8_de_irq_handler(dev_priv, disp_ctl);
> +	}
> +
> +	/* Acknowledge and enable interrupts. */
> +	I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
> +	POSTING_READ_FW(GEN11_GFX_MSTR_IRQ);
> +
> +	enable_rpm_wakeref_asserts(dev_priv);
> +
> +	return ret;
> +}
> +
>  /**
>   * i915_reset_device - do process context error handling work
>   * @dev_priv: i915 device private
> @@ -3159,6 +3290,42 @@ static void gen8_irq_reset(struct drm_device *dev)
>  		ibx_irq_reset(dev_priv);
>  }
>  
> +static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
> +{
> +	/* Disable RCS, BCS, VCS and VECS class engines. */
> +	I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0);
> +	I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE,	  0);
> +
> +	/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
> +	I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK,	~0);
> +	I915_WRITE(GEN11_BCS_RSVD_INTR_MASK,	~0);
> +	I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,	~0);
> +	I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,	~0);
> +	I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,	~0);
> +}
> +
> +static void gen11_irq_reset(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int pipe;
> +
> +	I915_WRITE(GEN11_GFX_MSTR_IRQ, 0);
> +	POSTING_READ(GEN11_GFX_MSTR_IRQ);
> +
> +	gen11_gt_irq_reset(dev_priv);
> +
> +	I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
> +
> +	for_each_pipe(dev_priv, pipe)
> +		if (intel_display_power_is_enabled(dev_priv,
> +						   POWER_DOMAIN_PIPE(pipe)))
> +			GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
> +
> +	GEN3_IRQ_RESET(GEN8_DE_PORT_);
> +	GEN3_IRQ_RESET(GEN8_DE_MISC_);
> +	GEN3_IRQ_RESET(GEN8_PCU_);
> +}
> +
>  void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>  				     u8 pipe_mask)
>  {
> @@ -3656,6 +3823,41 @@ static int gen8_irq_postinstall(struct drm_device *dev)
>  	return 0;
>  }
>  
> +static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> +	const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
> +
> +	BUILD_BUG_ON(irqs & 0xffff0000);
> +
> +	/* Enable RCS, BCS, VCS and VECS class interrupts. */
> +	I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs);
> +	I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE,	  irqs << 16 | irqs);
> +
> +	/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
> +	I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK,	~(irqs << 16));
> +	I915_WRITE(GEN11_BCS_RSVD_INTR_MASK,	~(irqs << 16));
> +	I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,	~(irqs | irqs << 16));
> +	I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,	~(irqs | irqs << 16));
> +	I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,	~(irqs | irqs << 16));
> +
> +	dev_priv->pm_imr = 0xffffffff; /* TODO */
> +}
> +
> +static int gen11_irq_postinstall(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	gen11_gt_irq_postinstall(dev_priv);
> +	gen8_de_irq_postinstall(dev_priv);
> +
> +	I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
> +
> +	I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
> +	POSTING_READ(GEN11_GFX_MSTR_IRQ);
> +
> +	return 0;
> +}
> +
>  static int cherryview_irq_postinstall(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -4104,6 +4306,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>  		dev->driver->enable_vblank = i965_enable_vblank;
>  		dev->driver->disable_vblank = i965_disable_vblank;
>  		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> +	} else if (INTEL_GEN(dev_priv) >= 11) {
> +		dev->driver->irq_handler = gen11_irq_handler;
> +		dev->driver->irq_preinstall = gen11_irq_reset;
> +		dev->driver->irq_postinstall = gen11_irq_postinstall;
> +		dev->driver->irq_uninstall = gen11_irq_reset;
> +		dev->driver->enable_vblank = gen8_enable_vblank;
> +		dev->driver->disable_vblank = gen8_disable_vblank;
> +		dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
>  	} else if (INTEL_GEN(dev_priv) >= 8) {
>  		dev->driver->irq_handler = gen8_irq_handler;
>  		dev->driver->irq_preinstall = gen8_irq_reset;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d88f107b0d50..087f981461e7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8027,7 +8027,10 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
>  	dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
>  	intel_disable_gt_powersave(dev_priv);
>  
> -	gen6_reset_rps_interrupts(dev_priv);
> +	if (INTEL_GEN(dev_priv) < 11)
> +		gen6_reset_rps_interrupts(dev_priv);
> +	else
> +		WARN_ON_ONCE(1);
>  }
>  
>  static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
> @@ -8140,6 +8143,8 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
>  		cherryview_enable_rps(dev_priv);
>  	} else if (IS_VALLEYVIEW(dev_priv)) {
>  		valleyview_enable_rps(dev_priv);
> +	} else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) {
> +		/* TODO */
>  	} else if (INTEL_GEN(dev_priv) >= 9) {
>  		gen9_enable_rps(dev_priv);
>  	} else if (IS_BROADWELL(dev_priv)) {
> -- 
> 2.14.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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✓ Fi.CI.BAT: success for ICL GEM enabling (v2) (rev2)

[Patchwork]

== Series Details ==

Series: ICL GEM enabling (v2) (rev2)
URL   : https://patchwork.freedesktop.org/series/38174/
State : success

== Summary ==

Series 38174v2 ICL GEM enabling (v2)
https://patchwork.freedesktop.org/api/1.0/series/38174/revisions/2/mbox/

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:418s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:422s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:376s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:488s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:288s
fi-bxt-dsi       total:288  pass:258  dwarn:0   dfail:0   fail:0   skip:30  time:477s
fi-bxt-j4205     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:484s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:468s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:457s
fi-cfl-s2        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:570s
fi-cnl-y3        total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:586s
fi-elk-e7500     total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:416s
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:283s
fi-glk-1         total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:509s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:397s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:411s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:458s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:414s
fi-kbl-7500u     total:288  pass:263  dwarn:1   dfail:0   fail:0   skip:24  time:455s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:498s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:503s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:585s
fi-skl-6260u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:426s
fi-skl-6600u     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:508s
fi-skl-6700hq    total:288  pass:262  dwarn:0   dfail:0   fail:0   skip:26  time:525s
fi-skl-6770hq    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:478s
fi-skl-guc       total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:415s
fi-skl-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:428s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:534s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:396s
Blacklisted hosts:
fi-kbl-7567u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:459s

e34af189963498c5168b4b5ba0a9be7aa96f69e1 drm-tip: 2018y-02m-14d-11h-50m-53s UTC integration manifest
2a584d53b971 drm/i915/icl: Enable RC6 and RPS in Gen11
feef482fb7f3 drm/i915/icl: Handle RPS interrupts correctly for Gen11
69f0d8dbe77e drm/i915/icl: Split out the servicing of the Selector and Shared IIR registers
d69bf1391650 drm/i915/icl: Add configuring MOCS in new Icelake engines
d1a20b90b203 drm/i915/icl: Add reset control register changes
5d1119aba0bb drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
a92d8fb69ff7 drm/i915/icl: Update subslice define for ICL 11
507d86de0ad8 drm/i915/icl: Enable the extra video decode and enhancement boxes for Icelake 11
505af6b68524 drm/i915/icl: Check for fused-off VDBOX and VEBOX instances
96cf65e43227 drm/i915/icl: Gen11 forcewake support
c3f217cfec40 drm/i915/icl: Add Indirect Context Offset for Gen11
ea7cec009f3b drm/i915/icl: Enhanced execution list support
e535dcb288c4 drm/i915/icl: new context descriptor support
f3825b9b7935 drm/i915/icl: Correctly initialize the Gen11 engines
35e3bee64402 drm/i915/icl: Ringbuffer interrupt handling
21129ec5a1e2 drm/i915/icl: Interrupt handling
145a0e361111 drm/i915/icl: Prepare for more rings
048837d73700 drm/i915/icl: Show interrupt registers in debugfs
d75493c4335d drm/i915/icl: add icelake_init_clock_gating()
e3d750591349 drm/i915/icl: Add the ICL PCI IDs

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8016/issues.html
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[PATCH 05/19] drm/i915/icl: Interrupt handling

[Mika Kuoppala]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

v2: Rebase.

v3:
  * Remove DPF, it has been removed from SKL+.
  * Fix -internal rebase wrt. execlists interrupt handling.

v4: Rebase.

v5:
  * Updated for POR changes. (Daniele Ceraolo Spurio)
  * Merged with irq handling fixes by Daniele Ceraolo Spurio:
      * Simplify the code by using gen8_cs_irq_handler.
      * Fix interrupt handling for the upstream kernel.

v6:
  * Remove early bringup debug messages (Tvrtko)
  * Add NB about arbitrary spin wait timeout (Tvrtko)

v7 (from Paulo):
  * Don't try to write RO bits to registers.
  * Don't check for PCH types that don't exist. PCH interrupts are not
    here yet.

v9:
  * squashed in selector and shared register handling (Daniele)
  * skip writing of irq if data is not valid (Daniele)
  * use time_after32 (Chris)
  * use I915_MAX_VCS and I915_MAX_VECS (Daniele)
  * remove fake pm interrupt handling for later patch (Mika)

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 212 ++++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_pm.c |   7 +-
 2 files changed, 218 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b886bd459acc..9a2d12c8c44c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -408,6 +408,37 @@ void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 	spin_unlock_irq(&dev_priv->irq_lock);
 }
 
+static int gen11_service_shared_iir(struct drm_i915_private *dev_priv,
+				    const unsigned int bank,
+				    const unsigned int bit)
+{
+	u64 wait_end;
+	u32 ident;
+	int irq;
+
+	I915_WRITE_FW(GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
+	/*
+	 * NB: Specs do not specify how long to spin wait.
+	 * Taking 100us as an educated guess
+	 */
+	wait_end = (local_clock() >> 10) + 100;
+	do {
+		ident = I915_READ_FW(GEN11_INTR_IDENTITY_REG(bank));
+	} while (!(ident & GEN11_INTR_DATA_VALID) &&
+		 !time_after32(local_clock() >> 10, wait_end));
+
+	if (!(ident & GEN11_INTR_DATA_VALID)) {
+		DRM_ERROR("INTR_IDENTITY_REG%u:%u timed out!\n", bank, bit);
+		return -ETIMEDOUT;
+	}
+
+	irq = ident & GEN11_INTR_ENGINE_MASK;
+
+	I915_WRITE_FW(GEN11_INTR_IDENTITY_REG(bank), ident);
+
+	return irq;
+}
+
 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 {
 	struct intel_rps *rps = &dev_priv->gt_pm.rps;
@@ -415,6 +446,9 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 	if (READ_ONCE(rps->interrupts_enabled))
 		return;
 
+	if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
+		return;
+
 	spin_lock_irq(&dev_priv->irq_lock);
 	WARN_ON_ONCE(rps->pm_iir);
 	WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
@@ -431,6 +465,9 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 	if (!READ_ONCE(rps->interrupts_enabled))
 		return;
 
+	if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
+		return;
+
 	spin_lock_irq(&dev_priv->irq_lock);
 	rps->interrupts_enabled = false;
 
@@ -2746,6 +2783,102 @@ static void __fini_wedge(struct wedge_me *w)
 	     (W)->i915;							\
 	     __fini_wedge((W)))
 
+static __always_inline void
+gen11_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
+{
+	gen8_cs_irq_handler(engine, iir, 0);
+}
+
+static void
+gen11_gt_irq_handler(struct drm_i915_private *dev_priv, const u32 master_ctl)
+{
+	u16 irq[2][32];
+	unsigned int bank, engine;
+
+	memset(irq, 0, sizeof(irq));
+
+	for (bank = 0; bank < 2; bank++) {
+		unsigned long tmp;
+		unsigned int bit;
+		u32 dw;
+		int ret;
+
+		if (!(master_ctl & GEN11_GT_DW_IRQ(bank)))
+			continue;
+
+		dw = I915_READ_FW(GEN11_GT_INTR_DW(bank));
+		if (!dw)
+			DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
+
+		tmp = dw;
+		for_each_set_bit(bit, &tmp, 32) {
+			ret = gen11_service_shared_iir(dev_priv, bank, bit);
+			if (unlikely(ret < 0))
+				continue;
+
+			irq[bank][bit] = ret;
+		}
+
+		I915_WRITE_FW(GEN11_GT_INTR_DW(bank), dw);
+	}
+
+	if (irq[0][GEN11_RCS0])
+		gen11_cs_irq_handler(dev_priv->engine[RCS],
+				     irq[0][GEN11_RCS0]);
+
+	if (irq[0][GEN11_BCS])
+		gen11_cs_irq_handler(dev_priv->engine[BCS],
+				     irq[0][GEN11_BCS]);
+
+	for (engine = 0; engine < I915_MAX_VCS; engine++)
+		if (irq[1][GEN11_VCS(engine)])
+			gen11_cs_irq_handler(dev_priv->engine[_VCS(engine)],
+					     irq[1][GEN11_VCS(engine)]);
+
+	for (engine = 0; engine < I915_MAX_VECS; engine++)
+		if (irq[1][GEN11_VECS(engine)])
+			gen11_cs_irq_handler(dev_priv->engine[_VECS(engine)],
+					     irq[1][GEN11_VECS(engine)]);
+}
+
+static irqreturn_t gen11_irq_handler(int irq, void *arg)
+{
+	struct drm_device *dev = arg;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 master_ctl;
+	u32 disp_ctl;
+
+	if (!intel_irqs_enabled(dev_priv))
+		return IRQ_NONE;
+
+	master_ctl = I915_READ_FW(GEN11_GFX_MSTR_IRQ);
+	master_ctl &= ~GEN11_MASTER_IRQ;
+	if (!master_ctl)
+		return IRQ_NONE;
+
+	/* Disable interrupts. */
+	I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, 0);
+
+	/* IRQs are synced during runtime_suspend, we don't require a wakeref */
+	disable_rpm_wakeref_asserts(dev_priv);
+
+	/* Find, clear, then process each source of interrupt. */
+	gen11_gt_irq_handler(dev_priv, master_ctl);
+
+	if (master_ctl & GEN11_DISPLAY_IRQ) {
+		disp_ctl = I915_READ_FW(GEN11_DISPLAY_INT_CTL);
+		gen8_de_irq_handler(dev_priv, disp_ctl);
+	}
+
+	/* Acknowledge and enable interrupts. */
+	I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
+	POSTING_READ_FW(GEN11_GFX_MSTR_IRQ);
+
+	enable_rpm_wakeref_asserts(dev_priv);
+
+	return IRQ_HANDLED;
+}
+
 /**
  * i915_reset_device - do process context error handling work
  * @dev_priv: i915 device private
@@ -3159,6 +3292,42 @@ static void gen8_irq_reset(struct drm_device *dev)
 		ibx_irq_reset(dev_priv);
 }
 
+static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
+{
+	/* Disable RCS, BCS, VCS and VECS class engines. */
+	I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0);
+	I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE,	  0);
+
+	/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
+	I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK,	~0);
+	I915_WRITE(GEN11_BCS_RSVD_INTR_MASK,	~0);
+	I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,	~0);
+	I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,	~0);
+	I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,	~0);
+}
+
+static void gen11_irq_reset(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int pipe;
+
+	I915_WRITE(GEN11_GFX_MSTR_IRQ, 0);
+	POSTING_READ(GEN11_GFX_MSTR_IRQ);
+
+	gen11_gt_irq_reset(dev_priv);
+
+	I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
+
+	for_each_pipe(dev_priv, pipe)
+		if (intel_display_power_is_enabled(dev_priv,
+						   POWER_DOMAIN_PIPE(pipe)))
+			GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
+
+	GEN3_IRQ_RESET(GEN8_DE_PORT_);
+	GEN3_IRQ_RESET(GEN8_DE_MISC_);
+	GEN3_IRQ_RESET(GEN8_PCU_);
+}
+
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 				     u8 pipe_mask)
 {
@@ -3656,6 +3825,41 @@ static int gen8_irq_postinstall(struct drm_device *dev)
 	return 0;
 }
 
+static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+	const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
+
+	BUILD_BUG_ON(irqs & 0xffff0000);
+
+	/* Enable RCS, BCS, VCS and VECS class interrupts. */
+	I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs);
+	I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE,	  irqs << 16 | irqs);
+
+	/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
+	I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK,	~(irqs << 16));
+	I915_WRITE(GEN11_BCS_RSVD_INTR_MASK,	~(irqs << 16));
+	I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,	~(irqs | irqs << 16));
+	I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,	~(irqs | irqs << 16));
+	I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,	~(irqs | irqs << 16));
+
+	dev_priv->pm_imr = 0xffffffff; /* TODO */
+}
+
+static int gen11_irq_postinstall(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	gen11_gt_irq_postinstall(dev_priv);
+	gen8_de_irq_postinstall(dev_priv);
+
+	I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
+
+	I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
+	POSTING_READ(GEN11_GFX_MSTR_IRQ);
+
+	return 0;
+}
+
 static int cherryview_irq_postinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -4104,6 +4308,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		dev->driver->enable_vblank = i965_enable_vblank;
 		dev->driver->disable_vblank = i965_disable_vblank;
 		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+	} else if (INTEL_GEN(dev_priv) >= 11) {
+		dev->driver->irq_handler = gen11_irq_handler;
+		dev->driver->irq_preinstall = gen11_irq_reset;
+		dev->driver->irq_postinstall = gen11_irq_postinstall;
+		dev->driver->irq_uninstall = gen11_irq_reset;
+		dev->driver->enable_vblank = gen8_enable_vblank;
+		dev->driver->disable_vblank = gen8_disable_vblank;
+		dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
 	} else if (INTEL_GEN(dev_priv) >= 8) {
 		dev->driver->irq_handler = gen8_irq_handler;
 		dev->driver->irq_preinstall = gen8_irq_reset;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 98d336a1d885..e207c3a2eea9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8027,7 +8027,10 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 	dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
 	intel_disable_gt_powersave(dev_priv);
 
-	gen6_reset_rps_interrupts(dev_priv);
+	if (INTEL_GEN(dev_priv) < 11)
+		gen6_reset_rps_interrupts(dev_priv);
+	else
+		WARN_ON_ONCE(1);
 }
 
 static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
@@ -8140,6 +8143,8 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
 		cherryview_enable_rps(dev_priv);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
 		valleyview_enable_rps(dev_priv);
+	} else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) {
+		/* TODO */
 	} else if (INTEL_GEN(dev_priv) >= 9) {
 		gen9_enable_rps(dev_priv);
 	} else if (IS_BROADWELL(dev_priv)) {
-- 
2.14.1

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Re: [PATCH 05/19] drm/i915/icl: Interrupt handling

[Chris Wilson]

Quoting Mika Kuoppala (2018-02-14 14:12:13)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> 
> v2: Rebase.
> 
> v3:
>   * Remove DPF, it has been removed from SKL+.
>   * Fix -internal rebase wrt. execlists interrupt handling.
> 
> v4: Rebase.
> 
> v5:
>   * Updated for POR changes. (Daniele Ceraolo Spurio)
>   * Merged with irq handling fixes by Daniele Ceraolo Spurio:
>       * Simplify the code by using gen8_cs_irq_handler.
>       * Fix interrupt handling for the upstream kernel.
> 
> v6:
>   * Remove early bringup debug messages (Tvrtko)
>   * Add NB about arbitrary spin wait timeout (Tvrtko)
> 
> v7 (from Paulo):
>   * Don't try to write RO bits to registers.
>   * Don't check for PCH types that don't exist. PCH interrupts are not
>     here yet.
> 
> v9:
>   * squashed in selector and shared register handling (Daniele)
>   * skip writing of irq if data is not valid (Daniele)
>   * use time_after32 (Chris)
>   * use I915_MAX_VCS and I915_MAX_VECS (Daniele)
>   * remove fake pm interrupt handling for later patch (Mika)
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_irq.c | 212 ++++++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_pm.c |   7 +-
>  2 files changed, 218 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b886bd459acc..9a2d12c8c44c 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -408,6 +408,37 @@ void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
>         spin_unlock_irq(&dev_priv->irq_lock);
>  }
>  
> +static int gen11_service_shared_iir(struct drm_i915_private *dev_priv,
> +                                   const unsigned int bank,
> +                                   const unsigned int bit)
> +{
> +       u64 wait_end;
> +       u32 ident;
> +       int irq;
> +
> +       I915_WRITE_FW(GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
> +       /*
> +        * NB: Specs do not specify how long to spin wait.
> +        * Taking 100us as an educated guess
> +        */
> +       wait_end = (local_clock() >> 10) + 100;
> +       do {
> +               ident = I915_READ_FW(GEN11_INTR_IDENTITY_REG(bank));
> +       } while (!(ident & GEN11_INTR_DATA_VALID) &&
> +                !time_after32(local_clock() >> 10, wait_end));

Now you are just mixing types willy nilly :)

No need for wait_end to be 64b when we are looking at a 100 interval.

> +
> +       if (!(ident & GEN11_INTR_DATA_VALID)) {
> +               DRM_ERROR("INTR_IDENTITY_REG%u:%u timed out!\n", bank, bit);
> +               return -ETIMEDOUT;
> +       }
> +
> +       irq = ident & GEN11_INTR_ENGINE_MASK;
> +
> +       I915_WRITE_FW(GEN11_INTR_IDENTITY_REG(bank), ident);
> +
> +       return irq;

return ident & GEN11_INTR_ENGINE_MASK;

no need for irq, and why int return type?

Why is this gen11 specific helper so far away from the irq_handler?

> +static __always_inline void
> +gen11_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
> +{
> +       gen8_cs_irq_handler(engine, iir, 0);
> +}
> +
> +static void
> +gen11_gt_irq_handler(struct drm_i915_private *dev_priv, const u32 master_ctl)
> +{
> +       u16 irq[2][32];
> +       unsigned int bank, engine;
> +
> +       memset(irq, 0, sizeof(irq));
> +
> +       for (bank = 0; bank < 2; bank++) {
> +               unsigned long tmp;
> +               unsigned int bit;
> +               u32 dw;
> +               int ret;
> +
> +               if (!(master_ctl & GEN11_GT_DW_IRQ(bank)))
> +                       continue;
> +
> +               dw = I915_READ_FW(GEN11_GT_INTR_DW(bank));
> +               if (!dw)
> +                       DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
> +
> +               tmp = dw;
> +               for_each_set_bit(bit, &tmp, 32) {

tmp is not required here.

> +                       ret = gen11_service_shared_iir(dev_priv, bank, bit);
> +                       if (unlikely(ret < 0))
> +                               continue;
> +
> +                       irq[bank][bit] = ret;
> +               }
> +
> +               I915_WRITE_FW(GEN11_GT_INTR_DW(bank), dw);

If we process the banks here, we won't need to memset 128 bytes and scan
untouched cachelines!

> +       }
> +
> +       if (irq[0][GEN11_RCS0])
> +               gen11_cs_irq_handler(dev_priv->engine[RCS],
> +                                    irq[0][GEN11_RCS0]);
> +
> +       if (irq[0][GEN11_BCS])
> +               gen11_cs_irq_handler(dev_priv->engine[BCS],
> +                                    irq[0][GEN11_BCS]);
> +
> +       for (engine = 0; engine < I915_MAX_VCS; engine++)
> +               if (irq[1][GEN11_VCS(engine)])
> +                       gen11_cs_irq_handler(dev_priv->engine[_VCS(engine)],
> +                                            irq[1][GEN11_VCS(engine)]);
> +
> +       for (engine = 0; engine < I915_MAX_VECS; engine++)
> +               if (irq[1][GEN11_VECS(engine)])
> +                       gen11_cs_irq_handler(dev_priv->engine[_VECS(engine)],
> +                                            irq[1][GEN11_VECS(engine)]);

Keep reminding yourself that this is the hottest function in the entire
i915.ko.

> +}
> +
> +static irqreturn_t gen11_irq_handler(int irq, void *arg)
> +{
> +       struct drm_device *dev = arg;
> +       struct drm_i915_private *dev_priv = dev->dev_private;

What?

> +       u32 master_ctl;
> +       u32 disp_ctl;

Why is this at top level scope?

> +       if (!intel_irqs_enabled(dev_priv))
> +               return IRQ_NONE;
> +
> +       master_ctl = I915_READ_FW(GEN11_GFX_MSTR_IRQ);
> +       master_ctl &= ~GEN11_MASTER_IRQ;
> +       if (!master_ctl)
> +               return IRQ_NONE;
> +
> +       /* Disable interrupts. */
> +       I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, 0);
> +
> +       /* IRQs are synced during runtime_suspend, we don't require a wakeref */
> +       disable_rpm_wakeref_asserts(dev_priv);
> +
> +       /* Find, clear, then process each source of interrupt. */
> +       gen11_gt_irq_handler(dev_priv, master_ctl);
> +
> +       if (master_ctl & GEN11_DISPLAY_IRQ) {
> +               disp_ctl = I915_READ_FW(GEN11_DISPLAY_INT_CTL);
> +               gen8_de_irq_handler(dev_priv, disp_ctl);
> +       }
> +
> +       /* Acknowledge and enable interrupts. */
> +       I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
> +       POSTING_READ_FW(GEN11_GFX_MSTR_IRQ);
> +
> +       enable_rpm_wakeref_asserts(dev_priv);

What happened to the onion? gen8 is broken as well, sure I sent patches
to fix that. The posting read is ott, and you don't need to disable the
asserts around the GT irq handler.
-Chris
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[PATCH v5] drm/i915/icl: new context descriptor support

[Daniele Ceraolo Spurio]

Starting from Gen11 the context descriptor format has been updated in
the HW. The hw_id field has been considerably reduced in size and engine
class and instance fields have been added.

There is a slight name clashing issue because the field that we call
hw_id is actually called SW Context ID in the specs for Gen11+.

With the current size of the hw_id field we can have a maximum of 2k
contexts at any time, but we could use the sw_counter field (which is sw
defined) to increase that because the HW requirement is that
engine_id + sw id + sw_counter is a unique number.
GuC uses a similar method to support more contexts but does its tracking
at lrc level. To avoid doing an implementation that will need to be
reworked once GuC support lands, defer it for now and mark it as TODO.

v2: rebased, add documentation, fix GEN11_ENGINE_INSTANCE_SHIFT
v3: rebased, bring back lost code from i915_gem_context.c
v4: make TODO comment more generic
v5: be consistent with bit ordering, add extra checks (Chris)

Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |  1 +
 drivers/gpu/drm/i915/i915_gem_context.c | 11 ++++++++--
 drivers/gpu/drm/i915/i915_reg.h         |  6 ++++++
 drivers/gpu/drm/i915/intel_engine_cs.c  |  3 +++
 drivers/gpu/drm/i915/intel_lrc.c        | 36 +++++++++++++++++++++++++++++++--
 5 files changed, 53 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7db3557b945c..acaa63f8237d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2093,6 +2093,7 @@ struct drm_i915_private {
 		 */
 		struct ida hw_ida;
 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
+#define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
 	} contexts;
 
 	u32 fdi_rx_config;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 3d75f484f6e5..45b0b78aca3f 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -211,9 +211,15 @@ static void context_close(struct i915_gem_context *ctx)
 static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
 {
 	int ret;
+	unsigned int max;
+
+	if (INTEL_GEN(dev_priv) >= 11)
+		max = GEN11_MAX_CONTEXT_HW_ID;
+	else
+		max = MAX_CONTEXT_HW_ID;
 
 	ret = ida_simple_get(&dev_priv->contexts.hw_ida,
-			     0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
+			     0, max, GFP_KERNEL);
 	if (ret < 0) {
 		/* Contexts are only released when no longer active.
 		 * Flush any pending retires to hopefully release some
@@ -221,7 +227,7 @@ static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
 		 */
 		i915_gem_retire_requests(dev_priv);
 		ret = ida_simple_get(&dev_priv->contexts.hw_ida,
-				     0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
+				     0, max, GFP_KERNEL);
 		if (ret < 0)
 			return ret;
 	}
@@ -463,6 +469,7 @@ int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
 
 	/* Using the simple ida interface, the max is limited by sizeof(int) */
 	BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
+	BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > INT_MAX);
 	ida_init(&dev_priv->contexts.hw_ida);
 
 	/* lowest priority; idle task */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9c79b560823..789ec1e16058 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3869,6 +3869,12 @@ enum {
 
 #define GEN8_CTX_ID_SHIFT 32
 #define GEN8_CTX_ID_WIDTH 21
+#define GEN11_SW_CTX_ID_SHIFT 37
+#define GEN11_SW_CTX_ID_WIDTH 11
+#define GEN11_ENGINE_CLASS_SHIFT 61
+#define GEN11_ENGINE_CLASS_WIDTH 3
+#define GEN11_ENGINE_INSTANCE_SHIFT 48
+#define GEN11_ENGINE_INSTANCE_WIDTH 6
 
 #define CHV_CLK_CTL1			_MMIO(0x101100)
 #define VLV_CLK_CTL2			_MMIO(0x101104)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 0ad9184eba97..c21903bf0fd8 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -210,6 +210,9 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
 	GEM_BUG_ON(info->class >= ARRAY_SIZE(intel_engine_classes));
 	class_info = &intel_engine_classes[info->class];
 
+	BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
+	BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
+
 	if (GEM_WARN_ON(info->class > MAX_ENGINE_CLASS))
 		return -EINVAL;
 
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index c2c8380a0121..3d96592b4c6b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -187,6 +187,18 @@ static void execlists_init_reg_state(u32 *reg_state,
  *      bits 32-52:    ctx ID, a globally unique tag
  *      bits 53-54:    mbz, reserved for use by hardware
  *      bits 55-63:    group ID, currently unused and set to 0
+ *
+ * Starting from Gen11, the upper dword of the descriptor has a new format:
+ *
+ *      bits 32-36:    reserved
+ *      bits 37-47:    SW context ID
+ *      bits 48:53:    engine instance
+ *      bit 54:        mbz, reserved for use by hardware
+ *      bits 55-60:    SW counter
+ *      bits 61-63:    engine class
+ *
+ * engine info, SW context ID and SW counter need to form a unique number
+ * (Context ID) per lrc.
  */
 static void
 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
@@ -195,12 +207,32 @@ intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
 	struct intel_context *ce = &ctx->engine[engine->id];
 	u64 desc;
 
-	BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
+	BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH)));
+	BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH)));
 
 	desc = ctx->desc_template;				/* bits  0-11 */
+	GEM_BUG_ON(desc & GENMASK_ULL(63, 12));
+
 	desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
 								/* bits 12-31 */
-	desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT;		/* bits 32-52 */
+	GEM_BUG_ON(desc & GENMASK_ULL(63, 32));
+
+	if (INTEL_GEN(ctx->i915) >= 11) {
+		GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
+		desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
+								/* bits 37-47 */
+
+		desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
+								/* bits 48-53 */
+
+		/* TODO: decide what to do with SW counter (bits 55-60) */
+
+		desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
+								/* bits 61-63 */
+	} else {
+		GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH));
+		desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT;	/* bits 32-52 */
+	}
 
 	ce->lrc_desc = desc;
 }
-- 
2.16.1

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✗ Fi.CI.BAT: failure for ICL GEM enabling (v2) (rev4)

[Patchwork]

== Series Details ==

Series: ICL GEM enabling (v2) (rev4)
URL   : https://patchwork.freedesktop.org/series/38174/
State : failure

== Summary ==

Applying: drm/i915/icl: Add the ICL PCI IDs
Applying: drm/i915/icl: add icelake_init_clock_gating()
Applying: drm/i915/icl: Show interrupt registers in debugfs
Applying: drm/i915/icl: Prepare for more rings
Applying: drm/i915/icl: Interrupt handling
Applying: drm/i915/icl: Ringbuffer interrupt handling
Applying: drm/i915/icl: Correctly initialize the Gen11 engines
Applying: drm/i915/icl: new context descriptor support
Applying: drm/i915/icl: Enhanced execution list support
Applying: drm/i915/icl: Add Indirect Context Offset for Gen11
Applying: drm/i915/icl: Gen11 forcewake support
Applying: drm/i915/icl: Check for fused-off VDBOX and VEBOX instances
Applying: drm/i915/icl: Enable the extra video decode and enhancement boxes for Icelake 11
Applying: drm/i915/icl: Update subslice define for ICL 11
Applying: drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
Applying: drm/i915/icl: Add reset control register changes
Applying: drm/i915/icl: Add configuring MOCS in new Icelake engines
Applying: drm/i915/icl: Split out the servicing of the Selector and Shared IIR registers
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/i915_irq.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_irq.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_irq.c
Patch failed at 0018 drm/i915/icl: Split out the servicing of the Selector and Shared IIR registers
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [PATCH 05/19] drm/i915/icl: Interrupt handling

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Quoting Mika Kuoppala (2018-02-14 14:12:13)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> 
>> v2: Rebase.
>> 
>> v3:
>>   * Remove DPF, it has been removed from SKL+.
>>   * Fix -internal rebase wrt. execlists interrupt handling.
>> 
>> v4: Rebase.
>> 
>> v5:
>>   * Updated for POR changes. (Daniele Ceraolo Spurio)
>>   * Merged with irq handling fixes by Daniele Ceraolo Spurio:
>>       * Simplify the code by using gen8_cs_irq_handler.
>>       * Fix interrupt handling for the upstream kernel.
>> 
>> v6:
>>   * Remove early bringup debug messages (Tvrtko)
>>   * Add NB about arbitrary spin wait timeout (Tvrtko)
>> 
>> v7 (from Paulo):
>>   * Don't try to write RO bits to registers.
>>   * Don't check for PCH types that don't exist. PCH interrupts are not
>>     here yet.
>> 
>> v9:
>>   * squashed in selector and shared register handling (Daniele)
>>   * skip writing of irq if data is not valid (Daniele)
>>   * use time_after32 (Chris)
>>   * use I915_MAX_VCS and I915_MAX_VECS (Daniele)
>>   * remove fake pm interrupt handling for later patch (Mika)
>> 
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_irq.c | 212 ++++++++++++++++++++++++++++++++++++++++
>>  drivers/gpu/drm/i915/intel_pm.c |   7 +-
>>  2 files changed, 218 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index b886bd459acc..9a2d12c8c44c 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -408,6 +408,37 @@ void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
>>         spin_unlock_irq(&dev_priv->irq_lock);
>>  }
>>  
>> +static int gen11_service_shared_iir(struct drm_i915_private *dev_priv,
>> +                                   const unsigned int bank,
>> +                                   const unsigned int bit)
>> +{
>> +       u64 wait_end;
>> +       u32 ident;
>> +       int irq;
>> +
>> +       I915_WRITE_FW(GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
>> +       /*
>> +        * NB: Specs do not specify how long to spin wait.
>> +        * Taking 100us as an educated guess
>> +        */
>> +       wait_end = (local_clock() >> 10) + 100;
>> +       do {
>> +               ident = I915_READ_FW(GEN11_INTR_IDENTITY_REG(bank));
>> +       } while (!(ident & GEN11_INTR_DATA_VALID) &&
>> +                !time_after32(local_clock() >> 10, wait_end));
>
> Now you are just mixing types willy nilly :)
>
> No need for wait_end to be 64b when we are looking at a 100 interval.

I threw the poll away. We can add it later if someone objects
and/or evidence indicates that it is needed. But polling for 100us just
in case in irq handler should not be the first step.

>
>> +
>> +       if (!(ident & GEN11_INTR_DATA_VALID)) {
>> +               DRM_ERROR("INTR_IDENTITY_REG%u:%u timed out!\n", bank, bit);
>> +               return -ETIMEDOUT;
>> +       }
>> +
>> +       irq = ident & GEN11_INTR_ENGINE_MASK;
>> +
>> + I915_WRITE_FW(GEN11_INTR_IDENTITY_REG(bank), ident);

Bspec tells that valid bit write should be enough here.

>> +
>> +       return irq;
>
> return ident & GEN11_INTR_ENGINE_MASK;
>
> no need for irq, and why int return type?

I made it return zero on unvalid.

>
> Why is this gen11 specific helper so far away from the irq_handler?

Due to later patch in this series needing it, rc6 enabling
due to rps reset.

I moved those closer in both patches.

>
>> +static __always_inline void
>> +gen11_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
>> +{
>> +       gen8_cs_irq_handler(engine, iir, 0);
>> +}
>> +
>> +static void
>> +gen11_gt_irq_handler(struct drm_i915_private *dev_priv, const u32 master_ctl)
>> +{
>> +       u16 irq[2][32];
>> +       unsigned int bank, engine;
>> +
>> +       memset(irq, 0, sizeof(irq));
>> +
>> +       for (bank = 0; bank < 2; bank++) {
>> +               unsigned long tmp;
>> +               unsigned int bit;
>> +               u32 dw;
>> +               int ret;
>> +
>> +               if (!(master_ctl & GEN11_GT_DW_IRQ(bank)))
>> +                       continue;
>> +
>> +               dw = I915_READ_FW(GEN11_GT_INTR_DW(bank));
>> +               if (!dw)
>> +                       DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
>> +
>> +               tmp = dw;
>> +               for_each_set_bit(bit, &tmp, 32) {
>
> tmp is not required here.

reading directly now to unsigned long dw_intr.

>
>> +                       ret = gen11_service_shared_iir(dev_priv, bank, bit);
>> +                       if (unlikely(ret < 0))
>> +                               continue;
>> +
>> +                       irq[bank][bit] = ret;
>> +               }
>> +
>> +               I915_WRITE_FW(GEN11_GT_INTR_DW(bank), dw);
>
> If we process the banks here, we won't need to memset 128 bytes and scan
> untouched cachelines!

Made it so. Bspec says that we need to serve the engine shared irq
before clearing the corresponding bank bit. I avoided trickery
and kept it so that we minimize writes by clearing them all.

>
>> +       }
>> +
>> +       if (irq[0][GEN11_RCS0])
>> +               gen11_cs_irq_handler(dev_priv->engine[RCS],
>> +                                    irq[0][GEN11_RCS0]);
>> +
>> +       if (irq[0][GEN11_BCS])
>> +               gen11_cs_irq_handler(dev_priv->engine[BCS],
>> +                                    irq[0][GEN11_BCS]);
>> +
>> +       for (engine = 0; engine < I915_MAX_VCS; engine++)
>> +               if (irq[1][GEN11_VCS(engine)])
>> +                       gen11_cs_irq_handler(dev_priv->engine[_VCS(engine)],
>> +                                            irq[1][GEN11_VCS(engine)]);
>> +
>> +       for (engine = 0; engine < I915_MAX_VECS; engine++)
>> +               if (irq[1][GEN11_VECS(engine)])
>> +                       gen11_cs_irq_handler(dev_priv->engine[_VECS(engine)],
>> +                                            irq[1][GEN11_VECS(engine)]);
>
> Keep reminding yourself that this is the hottest function in the entire
> i915.ko.

The serving of engine specific irq is now done using outer
and inner switches. Atleast it looks leaner :O

>
>> +}
>> +
>> +static irqreturn_t gen11_irq_handler(int irq, void *arg)
>> +{
>> +       struct drm_device *dev = arg;
>> +       struct drm_i915_private *dev_priv = dev->dev_private;
>
> What?

	struct drm_i915_private * const dev_priv =
		to_i915((struct drm_device *)arg);
>
>> +       u32 master_ctl;
>> +       u32 disp_ctl;
>
> Why is this at top level scope?

It is no more at all.

>
>> +       if (!intel_irqs_enabled(dev_priv))
>> +               return IRQ_NONE;
>> +
>> +       master_ctl = I915_READ_FW(GEN11_GFX_MSTR_IRQ);
>> +       master_ctl &= ~GEN11_MASTER_IRQ;
>> +       if (!master_ctl)
>> +               return IRQ_NONE;
>> +
>> +       /* Disable interrupts. */
>> +       I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, 0);
>> +
>> +       /* IRQs are synced during runtime_suspend, we don't require a wakeref */
>> +       disable_rpm_wakeref_asserts(dev_priv);
>> +
>> +       /* Find, clear, then process each source of interrupt. */
>> +       gen11_gt_irq_handler(dev_priv, master_ctl);
>> +
>> +       if (master_ctl & GEN11_DISPLAY_IRQ) {
>> +               disp_ctl = I915_READ_FW(GEN11_DISPLAY_INT_CTL);
>> +               gen8_de_irq_handler(dev_priv, disp_ctl);
>> +       }
>> +
>> +       /* Acknowledge and enable interrupts. */
>> +       I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
>> +       POSTING_READ_FW(GEN11_GFX_MSTR_IRQ);
>> +
>> +       enable_rpm_wakeref_asserts(dev_priv);
>
> What happened to the onion? gen8 is broken as well, sure I sent patches
> to fix that. The posting read is ott, and you don't need to disable the
> asserts around the GT irq handler.

I moved the asserts inside display scope, like in gen8 version.

Thanks for comments,
-Mika

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[PATCH 05/19] drm/i915/icl: Interrupt handling

[Mika Kuoppala]

From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

v2: Rebase.

v3:
  * Remove DPF, it has been removed from SKL+.
  * Fix -internal rebase wrt. execlists interrupt handling.

v4: Rebase.

v5:
  * Updated for POR changes. (Daniele Ceraolo Spurio)
  * Merged with irq handling fixes by Daniele Ceraolo Spurio:
      * Simplify the code by using gen8_cs_irq_handler.
      * Fix interrupt handling for the upstream kernel.

v6:
  * Remove early bringup debug messages (Tvrtko)
  * Add NB about arbitrary spin wait timeout (Tvrtko)

v7 (from Paulo):
  * Don't try to write RO bits to registers.
  * Don't check for PCH types that don't exist. PCH interrupts are not
    here yet.

v9:
  * squashed in selector and shared register handling (Daniele)
  * skip writing of irq if data is not valid (Daniele)
  * use time_after32 (Chris)
  * use I915_MAX_VCS and I915_MAX_VECS (Daniele)
  * remove fake pm interrupt handling for later patch (Mika)

v10:
  * Direct processing of banks. clear banks early (Chris)
  * remove poll on valid bit, only clear valid bit (Mika)
  * use raw accessors, better naming (Chris)

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 222 ++++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_pm.c |   7 +-
 2 files changed, 228 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b886bd459acc..e3914d1e204e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -415,6 +415,9 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 	if (READ_ONCE(rps->interrupts_enabled))
 		return;
 
+	if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
+		return;
+
 	spin_lock_irq(&dev_priv->irq_lock);
 	WARN_ON_ONCE(rps->pm_iir);
 	WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
@@ -431,6 +434,9 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 	if (!READ_ONCE(rps->interrupts_enabled))
 		return;
 
+	if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
+		return;
+
 	spin_lock_irq(&dev_priv->irq_lock);
 	rps->interrupts_enabled = false;
 
@@ -2746,6 +2752,143 @@ static void __fini_wedge(struct wedge_me *w)
 	     (W)->i915;							\
 	     __fini_wedge((W)))
 
+static __always_inline void
+gen11_cs_irq_handler(struct intel_engine_cs * const engine, const u32 iir)
+{
+	gen8_cs_irq_handler(engine, iir, 0);
+}
+
+static void
+gen11_gt_engine_irq_handler(struct drm_i915_private * const i915,
+			    const unsigned int bank,
+			    const unsigned int engine_n,
+			    const u16 iir)
+{
+	struct intel_engine_cs ** const engine = i915->engine;
+
+	switch (bank) {
+	case 0:
+		switch (engine_n) {
+
+		case GEN11_RCS0:
+			return gen11_cs_irq_handler(engine[RCS], iir);
+
+		case GEN11_BCS:
+			return gen11_cs_irq_handler(engine[BCS], iir);
+		}
+	case 1:
+		switch (engine_n) {
+
+		case GEN11_VCS(0):
+			return gen11_cs_irq_handler(engine[_VCS(0)], iir);
+		case GEN11_VCS(1):
+			return gen11_cs_irq_handler(engine[_VCS(1)], iir);
+		case GEN11_VCS(2):
+			return gen11_cs_irq_handler(engine[_VCS(2)], iir);
+		case GEN11_VCS(3):
+			return gen11_cs_irq_handler(engine[_VCS(3)], iir);
+
+		case GEN11_VECS(0):
+			return gen11_cs_irq_handler(engine[_VECS(0)], iir);
+		case GEN11_VECS(1):
+			return gen11_cs_irq_handler(engine[_VECS(1)], iir);
+		}
+	}
+}
+
+static u32
+gen11_gt_engine_intr(struct drm_i915_private * const i915,
+		     const unsigned int bank, const unsigned int bit)
+{
+	void __iomem * const regs = i915->regs;
+	u32 ident;
+
+	writel(BIT(bit),
+	       regs + i915_mmio_reg_offset(GEN11_IIR_REG_SELECTOR(bank)));
+
+	ident = readl(regs +
+		      i915_mmio_reg_offset(GEN11_INTR_IDENTITY_REG(bank)));
+
+	if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
+		DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",
+			  bank, bit, ident);
+		return 0;
+	}
+
+	writel(GEN11_INTR_DATA_VALID,
+	       regs + i915_mmio_reg_offset(GEN11_INTR_IDENTITY_REG(bank)));
+
+	return ident & GEN11_INTR_ENGINE_MASK;
+}
+
+static void
+gen11_gt_irq_handler(struct drm_i915_private * const i915,
+		     const u32 master_ctl)
+{
+	void __iomem * const regs = i915->regs;
+	unsigned int bank;
+
+	for (bank = 0; bank < 2; bank++) {
+		unsigned long intr_dw;
+		unsigned int bit;
+
+		if (!(master_ctl & GEN11_GT_DW_IRQ(bank)))
+			continue;
+
+		intr_dw = readl(regs +
+				i915_mmio_reg_offset(GEN11_GT_INTR_DW(bank)));
+
+		if (unlikely(!intr_dw))
+			DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
+
+		for_each_set_bit(bit, &intr_dw, 32) {
+			const u16 iir = gen11_gt_engine_intr(i915, bank, bit);
+
+			if (unlikely(!iir))
+				continue;
+
+			gen11_gt_engine_irq_handler(i915, bank, bit, iir);
+		}
+
+		/* Clear must be after shared has been served for engine */
+		writel(intr_dw,
+		       regs + i915_mmio_reg_offset(GEN11_GT_INTR_DW(bank)));
+	}
+}
+
+static irqreturn_t gen11_irq_handler(int irq, void *arg)
+{
+	struct drm_i915_private * const dev_priv =
+		to_i915((struct drm_device *)arg);
+	u32 master_ctl;
+
+	if (!intel_irqs_enabled(dev_priv))
+		return IRQ_NONE;
+
+	master_ctl = I915_READ_FW(GEN11_GFX_MSTR_IRQ);
+	master_ctl &= ~GEN11_MASTER_IRQ;
+	if (!master_ctl)
+		return IRQ_NONE;
+
+	/* Disable interrupts. */
+	I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, 0);
+
+	/* Find, clear, then process each source of interrupt. */
+	gen11_gt_irq_handler(dev_priv, master_ctl);
+
+	if (master_ctl & GEN11_DISPLAY_IRQ) {
+		disable_rpm_wakeref_asserts(dev_priv);
+		gen8_de_irq_handler(dev_priv,
+				    I915_READ_FW(GEN11_DISPLAY_INT_CTL));
+		enable_rpm_wakeref_asserts(dev_priv);
+	}
+
+	/* Acknowledge and enable interrupts. */
+	I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
+
+	return IRQ_HANDLED;
+}
+
 /**
  * i915_reset_device - do process context error handling work
  * @dev_priv: i915 device private
@@ -3159,6 +3302,42 @@ static void gen8_irq_reset(struct drm_device *dev)
 		ibx_irq_reset(dev_priv);
 }
 
+static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
+{
+	/* Disable RCS, BCS, VCS and VECS class engines. */
+	I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0);
+	I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE,	  0);
+
+	/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
+	I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK,	~0);
+	I915_WRITE(GEN11_BCS_RSVD_INTR_MASK,	~0);
+	I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,	~0);
+	I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,	~0);
+	I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,	~0);
+}
+
+static void gen11_irq_reset(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	int pipe;
+
+	I915_WRITE(GEN11_GFX_MSTR_IRQ, 0);
+	POSTING_READ(GEN11_GFX_MSTR_IRQ);
+
+	gen11_gt_irq_reset(dev_priv);
+
+	I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
+
+	for_each_pipe(dev_priv, pipe)
+		if (intel_display_power_is_enabled(dev_priv,
+						   POWER_DOMAIN_PIPE(pipe)))
+			GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
+
+	GEN3_IRQ_RESET(GEN8_DE_PORT_);
+	GEN3_IRQ_RESET(GEN8_DE_MISC_);
+	GEN3_IRQ_RESET(GEN8_PCU_);
+}
+
 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 				     u8 pipe_mask)
 {
@@ -3656,6 +3835,41 @@ static int gen8_irq_postinstall(struct drm_device *dev)
 	return 0;
 }
 
+static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+	const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
+
+	BUILD_BUG_ON(irqs & 0xffff0000);
+
+	/* Enable RCS, BCS, VCS and VECS class interrupts. */
+	I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs);
+	I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE,	  irqs << 16 | irqs);
+
+	/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
+	I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK,	~(irqs << 16));
+	I915_WRITE(GEN11_BCS_RSVD_INTR_MASK,	~(irqs << 16));
+	I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,	~(irqs | irqs << 16));
+	I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,	~(irqs | irqs << 16));
+	I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,	~(irqs | irqs << 16));
+
+	dev_priv->pm_imr = 0xffffffff; /* TODO */
+}
+
+static int gen11_irq_postinstall(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	gen11_gt_irq_postinstall(dev_priv);
+	gen8_de_irq_postinstall(dev_priv);
+
+	I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
+
+	I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
+	POSTING_READ(GEN11_GFX_MSTR_IRQ);
+
+	return 0;
+}
+
 static int cherryview_irq_postinstall(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -4104,6 +4318,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
 		dev->driver->enable_vblank = i965_enable_vblank;
 		dev->driver->disable_vblank = i965_disable_vblank;
 		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+	} else if (INTEL_GEN(dev_priv) >= 11) {
+		dev->driver->irq_handler = gen11_irq_handler;
+		dev->driver->irq_preinstall = gen11_irq_reset;
+		dev->driver->irq_postinstall = gen11_irq_postinstall;
+		dev->driver->irq_uninstall = gen11_irq_reset;
+		dev->driver->enable_vblank = gen8_enable_vblank;
+		dev->driver->disable_vblank = gen8_disable_vblank;
+		dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
 	} else if (INTEL_GEN(dev_priv) >= 8) {
 		dev->driver->irq_handler = gen8_irq_handler;
 		dev->driver->irq_preinstall = gen8_irq_reset;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 939b8a41580c..996ab86100ee 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8029,7 +8029,10 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 	dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
 	intel_disable_gt_powersave(dev_priv);
 
-	gen6_reset_rps_interrupts(dev_priv);
+	if (INTEL_GEN(dev_priv) < 11)
+		gen6_reset_rps_interrupts(dev_priv);
+	else
+		WARN_ON_ONCE(1);
 }
 
 static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
@@ -8142,6 +8145,8 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
 		cherryview_enable_rps(dev_priv);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
 		valleyview_enable_rps(dev_priv);
+	} else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) {
+		/* TODO */
 	} else if (INTEL_GEN(dev_priv) >= 9) {
 		gen9_enable_rps(dev_priv);
 	} else if (IS_BROADWELL(dev_priv)) {
-- 
2.14.1

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Re: [PATCH 05/19] drm/i915/icl: Interrupt handling

[Tvrtko Ursulin]

On 15/02/2018 16:27, Mika Kuoppala wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

I think a point has arrived when I almost don't recognize the code any 
longer so would want to relinquish the authorship if you don't mind.

Regards,

Tvrtko


> v2: Rebase.
> 
> v3:
>    * Remove DPF, it has been removed from SKL+.
>    * Fix -internal rebase wrt. execlists interrupt handling.
> 
> v4: Rebase.
> 
> v5:
>    * Updated for POR changes. (Daniele Ceraolo Spurio)
>    * Merged with irq handling fixes by Daniele Ceraolo Spurio:
>        * Simplify the code by using gen8_cs_irq_handler.
>        * Fix interrupt handling for the upstream kernel.
> 
> v6:
>    * Remove early bringup debug messages (Tvrtko)
>    * Add NB about arbitrary spin wait timeout (Tvrtko)
> 
> v7 (from Paulo):
>    * Don't try to write RO bits to registers.
>    * Don't check for PCH types that don't exist. PCH interrupts are not
>      here yet.
> 
> v9:
>    * squashed in selector and shared register handling (Daniele)
>    * skip writing of irq if data is not valid (Daniele)
>    * use time_after32 (Chris)
>    * use I915_MAX_VCS and I915_MAX_VECS (Daniele)
>    * remove fake pm interrupt handling for later patch (Mika)
> 
> v10:
>    * Direct processing of banks. clear banks early (Chris)
>    * remove poll on valid bit, only clear valid bit (Mika)
>    * use raw accessors, better naming (Chris)
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_irq.c | 222 ++++++++++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_pm.c |   7 +-
>   2 files changed, 228 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b886bd459acc..e3914d1e204e 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -415,6 +415,9 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
>   	if (READ_ONCE(rps->interrupts_enabled))
>   		return;
>   
> +	if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
> +		return;
> +
>   	spin_lock_irq(&dev_priv->irq_lock);
>   	WARN_ON_ONCE(rps->pm_iir);
>   	WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
> @@ -431,6 +434,9 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
>   	if (!READ_ONCE(rps->interrupts_enabled))
>   		return;
>   
> +	if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
> +		return;
> +
>   	spin_lock_irq(&dev_priv->irq_lock);
>   	rps->interrupts_enabled = false;
>   
> @@ -2746,6 +2752,143 @@ static void __fini_wedge(struct wedge_me *w)
>   	     (W)->i915;							\
>   	     __fini_wedge((W)))
>   
> +static __always_inline void
> +gen11_cs_irq_handler(struct intel_engine_cs * const engine, const u32 iir)
> +{
> +	gen8_cs_irq_handler(engine, iir, 0);
> +}
> +
> +static void
> +gen11_gt_engine_irq_handler(struct drm_i915_private * const i915,
> +			    const unsigned int bank,
> +			    const unsigned int engine_n,
> +			    const u16 iir)
> +{
> +	struct intel_engine_cs ** const engine = i915->engine;
> +
> +	switch (bank) {
> +	case 0:
> +		switch (engine_n) {
> +
> +		case GEN11_RCS0:
> +			return gen11_cs_irq_handler(engine[RCS], iir);
> +
> +		case GEN11_BCS:
> +			return gen11_cs_irq_handler(engine[BCS], iir);
> +		}
> +	case 1:
> +		switch (engine_n) {
> +
> +		case GEN11_VCS(0):
> +			return gen11_cs_irq_handler(engine[_VCS(0)], iir);
> +		case GEN11_VCS(1):
> +			return gen11_cs_irq_handler(engine[_VCS(1)], iir);
> +		case GEN11_VCS(2):
> +			return gen11_cs_irq_handler(engine[_VCS(2)], iir);
> +		case GEN11_VCS(3):
> +			return gen11_cs_irq_handler(engine[_VCS(3)], iir);
> +
> +		case GEN11_VECS(0):
> +			return gen11_cs_irq_handler(engine[_VECS(0)], iir);
> +		case GEN11_VECS(1):
> +			return gen11_cs_irq_handler(engine[_VECS(1)], iir);
> +		}
> +	}
> +}
> +
> +static u32
> +gen11_gt_engine_intr(struct drm_i915_private * const i915,
> +		     const unsigned int bank, const unsigned int bit)
> +{
> +	void __iomem * const regs = i915->regs;
> +	u32 ident;
> +
> +	writel(BIT(bit),
> +	       regs + i915_mmio_reg_offset(GEN11_IIR_REG_SELECTOR(bank)));
> +
> +	ident = readl(regs +
> +		      i915_mmio_reg_offset(GEN11_INTR_IDENTITY_REG(bank)));
> +
> +	if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
> +		DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",
> +			  bank, bit, ident);
> +		return 0;
> +	}
> +
> +	writel(GEN11_INTR_DATA_VALID,
> +	       regs + i915_mmio_reg_offset(GEN11_INTR_IDENTITY_REG(bank)));
> +
> +	return ident & GEN11_INTR_ENGINE_MASK;
> +}
> +
> +static void
> +gen11_gt_irq_handler(struct drm_i915_private * const i915,
> +		     const u32 master_ctl)
> +{
> +	void __iomem * const regs = i915->regs;
> +	unsigned int bank;
> +
> +	for (bank = 0; bank < 2; bank++) {
> +		unsigned long intr_dw;
> +		unsigned int bit;
> +
> +		if (!(master_ctl & GEN11_GT_DW_IRQ(bank)))
> +			continue;
> +
> +		intr_dw = readl(regs +
> +				i915_mmio_reg_offset(GEN11_GT_INTR_DW(bank)));
> +
> +		if (unlikely(!intr_dw))
> +			DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
> +
> +		for_each_set_bit(bit, &intr_dw, 32) {
> +			const u16 iir = gen11_gt_engine_intr(i915, bank, bit);
> +
> +			if (unlikely(!iir))
> +				continue;
> +
> +			gen11_gt_engine_irq_handler(i915, bank, bit, iir);
> +		}
> +
> +		/* Clear must be after shared has been served for engine */
> +		writel(intr_dw,
> +		       regs + i915_mmio_reg_offset(GEN11_GT_INTR_DW(bank)));
> +	}
> +}
> +
> +static irqreturn_t gen11_irq_handler(int irq, void *arg)
> +{
> +	struct drm_i915_private * const dev_priv =
> +		to_i915((struct drm_device *)arg);
> +	u32 master_ctl;
> +
> +	if (!intel_irqs_enabled(dev_priv))
> +		return IRQ_NONE;
> +
> +	master_ctl = I915_READ_FW(GEN11_GFX_MSTR_IRQ);
> +	master_ctl &= ~GEN11_MASTER_IRQ;
> +	if (!master_ctl)
> +		return IRQ_NONE;
> +
> +	/* Disable interrupts. */
> +	I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, 0);
> +
> +	/* Find, clear, then process each source of interrupt. */
> +	gen11_gt_irq_handler(dev_priv, master_ctl);
> +
> +	if (master_ctl & GEN11_DISPLAY_IRQ) {
> +		disable_rpm_wakeref_asserts(dev_priv);
> +		gen8_de_irq_handler(dev_priv,
> +				    I915_READ_FW(GEN11_DISPLAY_INT_CTL));
> +		enable_rpm_wakeref_asserts(dev_priv);
> +	}
> +
> +	/* Acknowledge and enable interrupts. */
> +	I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
> +
> +	return IRQ_HANDLED;
> +}
> +
>   /**
>    * i915_reset_device - do process context error handling work
>    * @dev_priv: i915 device private
> @@ -3159,6 +3302,42 @@ static void gen8_irq_reset(struct drm_device *dev)
>   		ibx_irq_reset(dev_priv);
>   }
>   
> +static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
> +{
> +	/* Disable RCS, BCS, VCS and VECS class engines. */
> +	I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0);
> +	I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE,	  0);
> +
> +	/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
> +	I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK,	~0);
> +	I915_WRITE(GEN11_BCS_RSVD_INTR_MASK,	~0);
> +	I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,	~0);
> +	I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,	~0);
> +	I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,	~0);
> +}
> +
> +static void gen11_irq_reset(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int pipe;
> +
> +	I915_WRITE(GEN11_GFX_MSTR_IRQ, 0);
> +	POSTING_READ(GEN11_GFX_MSTR_IRQ);
> +
> +	gen11_gt_irq_reset(dev_priv);
> +
> +	I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
> +
> +	for_each_pipe(dev_priv, pipe)
> +		if (intel_display_power_is_enabled(dev_priv,
> +						   POWER_DOMAIN_PIPE(pipe)))
> +			GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
> +
> +	GEN3_IRQ_RESET(GEN8_DE_PORT_);
> +	GEN3_IRQ_RESET(GEN8_DE_MISC_);
> +	GEN3_IRQ_RESET(GEN8_PCU_);
> +}
> +
>   void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>   				     u8 pipe_mask)
>   {
> @@ -3656,6 +3835,41 @@ static int gen8_irq_postinstall(struct drm_device *dev)
>   	return 0;
>   }
>   
> +static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> +	const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
> +
> +	BUILD_BUG_ON(irqs & 0xffff0000);
> +
> +	/* Enable RCS, BCS, VCS and VECS class interrupts. */
> +	I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs);
> +	I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE,	  irqs << 16 | irqs);
> +
> +	/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
> +	I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK,	~(irqs << 16));
> +	I915_WRITE(GEN11_BCS_RSVD_INTR_MASK,	~(irqs << 16));
> +	I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK,	~(irqs | irqs << 16));
> +	I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK,	~(irqs | irqs << 16));
> +	I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK,	~(irqs | irqs << 16));
> +
> +	dev_priv->pm_imr = 0xffffffff; /* TODO */
> +}
> +
> +static int gen11_irq_postinstall(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	gen11_gt_irq_postinstall(dev_priv);
> +	gen8_de_irq_postinstall(dev_priv);
> +
> +	I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
> +
> +	I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
> +	POSTING_READ(GEN11_GFX_MSTR_IRQ);
> +
> +	return 0;
> +}
> +
>   static int cherryview_irq_postinstall(struct drm_device *dev)
>   {
>   	struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -4104,6 +4318,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>   		dev->driver->enable_vblank = i965_enable_vblank;
>   		dev->driver->disable_vblank = i965_disable_vblank;
>   		dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
> +	} else if (INTEL_GEN(dev_priv) >= 11) {
> +		dev->driver->irq_handler = gen11_irq_handler;
> +		dev->driver->irq_preinstall = gen11_irq_reset;
> +		dev->driver->irq_postinstall = gen11_irq_postinstall;
> +		dev->driver->irq_uninstall = gen11_irq_reset;
> +		dev->driver->enable_vblank = gen8_enable_vblank;
> +		dev->driver->disable_vblank = gen8_disable_vblank;
> +		dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
>   	} else if (INTEL_GEN(dev_priv) >= 8) {
>   		dev->driver->irq_handler = gen8_irq_handler;
>   		dev->driver->irq_preinstall = gen8_irq_reset;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 939b8a41580c..996ab86100ee 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8029,7 +8029,10 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
>   	dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
>   	intel_disable_gt_powersave(dev_priv);
>   
> -	gen6_reset_rps_interrupts(dev_priv);
> +	if (INTEL_GEN(dev_priv) < 11)
> +		gen6_reset_rps_interrupts(dev_priv);
> +	else
> +		WARN_ON_ONCE(1);
>   }
>   
>   static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
> @@ -8142,6 +8145,8 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
>   		cherryview_enable_rps(dev_priv);
>   	} else if (IS_VALLEYVIEW(dev_priv)) {
>   		valleyview_enable_rps(dev_priv);
> +	} else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) {
> +		/* TODO */
>   	} else if (INTEL_GEN(dev_priv) >= 9) {
>   		gen9_enable_rps(dev_priv);
>   	} else if (IS_BROADWELL(dev_priv)) {
> 
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✗ Fi.CI.BAT: failure for ICL GEM enabling (v2) (rev5)

[Patchwork]

== Series Details ==

Series: ICL GEM enabling (v2) (rev5)
URL   : https://patchwork.freedesktop.org/series/38174/
State : failure

== Summary ==

Applying: drm/i915/icl: Add the ICL PCI IDs
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/i915_pci.c
M	include/drm/i915_pciids.h
Falling back to patching base and 3-way merge...
Auto-merging include/drm/i915_pciids.h
Auto-merging drivers/gpu/drm/i915/i915_pci.c
Applying: drm/i915/icl: add icelake_init_clock_gating()
Applying: drm/i915/icl: Show interrupt registers in debugfs
Applying: drm/i915/icl: Prepare for more rings
Applying: drm/i915/icl: Interrupt handling
Applying: drm/i915/icl: Ringbuffer interrupt handling
Applying: drm/i915/icl: Correctly initialize the Gen11 engines
Applying: drm/i915/icl: new context descriptor support
Applying: drm/i915/icl: Enhanced execution list support
Applying: drm/i915/icl: Add Indirect Context Offset for Gen11
Applying: drm/i915/icl: Gen11 forcewake support
Applying: drm/i915/icl: Check for fused-off VDBOX and VEBOX instances
Applying: drm/i915/icl: Enable the extra video decode and enhancement boxes for Icelake 11
Applying: drm/i915/icl: Update subslice define for ICL 11
Applying: drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detection
Applying: drm/i915/icl: Add reset control register changes
Applying: drm/i915/icl: Add configuring MOCS in new Icelake engines
Applying: drm/i915/icl: Split out the servicing of the Selector and Shared IIR registers
error: Failed to merge in the changes.
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/i915_irq.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_irq.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_irq.c
Patch failed at 0018 drm/i915/icl: Split out the servicing of the Selector and Shared IIR registers
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [PATCH 05/19] drm/i915/icl: Interrupt handling

[Daniele Ceraolo Spurio]

<snip>

> +
> +static void
> +gen11_gt_irq_handler(struct drm_i915_private * const i915,
> +		     const u32 master_ctl)
> +{
> +	void __iomem * const regs = i915->regs;
> +	unsigned int bank;
> +
> +	for (bank = 0; bank < 2; bank++) {
> +		unsigned long intr_dw;
> +		unsigned int bit;
> +
> +		if (!(master_ctl & GEN11_GT_DW_IRQ(bank)))
> +			continue;
> +
> +		intr_dw = readl(regs +
> +				i915_mmio_reg_offset(GEN11_GT_INTR_DW(bank)));
> +

I think we should keep some kind of polling here, because there is going 
to be some delay between writing the selector and getting the correct 
value in the identity register and the CPU might also be running at a 
higher frequency than the GPU. Spec does not specify a time but implies 
that we have to wait for the valid bit to be set.

> +		if (unlikely(!intr_dw))
> +			DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
> +
> +		for_each_set_bit(bit, &intr_dw, 32) {
> +			const u16 iir = gen11_gt_engine_intr(i915, bank, bit);
> +
> +			if (unlikely(!iir))
> +				continue;
> +
> +			gen11_gt_engine_irq_handler(i915, bank, bit, iir);

The identity register contains the class (bits 16-18) and instance (bits 
20-25), so we can potentially decode them and call directly:

	gen11_cs_irq_handler(i915->engine_class[class][instance], iir);

instead of having a big switch. The only problem with that would be that 
GuC and PM interrupts come out as class 4 instances 0 and 1, so once we 
add support for those we'd have to do something like

	if (class != OTHER_CLASS)
		gen11_cs_irq_handler(...);
	else {
		switch (instance) {
		case 0:
			gen11_guc_irq_handler(...);
			break;
		case 1:
			gen11_rps_irq_handler(...);
			break;
		default:
			MISSING_CASE();
		}
	}

not sure if decoding class and instance and having a small switch wins 
in the end against the big switch, so I won't complain whichever you pick ;)

Daniele

> +		}
> +
> +		/* Clear must be after shared has been served for engine */
> +		writel(intr_dw,
> +		       regs + i915_mmio_reg_offset(GEN11_GT_INTR_DW(bank)));
> +	}
> +}
> +
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Re: [PATCH 12/20] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Sagar Arun Kamble]

On 2/13/2018 10:07 PM, Mika Kuoppala wrote:
> From: Oscar Mateo <oscar.mateo@intel.com>
>
> In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the
> Video Enhancement engines (aka VEBOX, aka VECS) could be fused off. Also,
> each VDBOX and VEBOX has its own power well, which only exist if the related
> engine exists in the HW.
>
> Unfortunately, we have a Catch-22 situation going on: we need to read an
> MMIO register with the fuse info, but we cannot fully enable MMIO until
> we read it (since we need the real engines to initialize the forcewake
> domains).
We need to ensure BLITTER is initialized first and use low level 
functions fw_domains_get/put()
around raw read to know these engines status.
>   We workaround this problem by reading the fuse after the MMIO
> is partially ready, but before we initialize forcewake.
>
> Bspec: 20680
>
> v2: We were shifting incorrectly for vebox disable (Vinay)
>
> v3: Assert mmio is ready and warn if we have attempted to initialize
>      forcewake for fused-off engines (Paulo)
>
> v4:
>    - Use INTEL_GEN in new code (Tvrtko)
>    - Shorter local variable (Tvrtko, Michal)
>    - Keep "if (!...) continue" style (Tvrtko)
>    - No unnecessary BUG_ON (Tvrtko)
>    - WARN_ON and cleanup if wrong mask (Tvrtko, Michal)
>    - Use I915_READ_FW (Michal)
>    - Use I915_MAX_VCS/VECS macros (Michal)
>
> v5: Rebased by Rodrigo fixing conflicts on top of:
>      commit 33def1ff7b0 ("drm/i915: Simplify intel_engines_init")
>
> v6: Fix v5. Remove info->num_rings. (by Oscar)
>
> v7: Rebase (Rodrigo).
>
> v8:
>    - s/intel_device_info_fused_off_engines/intel_device_info_init_mmio (Chris)
>    - Make vdbox_disable & vebox_disable local variables (Chris)
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.c          |  2 ++
>   drivers/gpu/drm/i915/i915_drv.h          |  1 +
>   drivers/gpu/drm/i915/i915_reg.h          |  5 +++
>   drivers/gpu/drm/i915/intel_device_info.c | 54 ++++++++++++++++++++++++++++++++
>   4 files changed, 62 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 9380c9f69b0f..43b2f620bca7 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1033,6 +1033,8 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
>   	if (ret < 0)
>   		goto err_bridge;
>   
> +	intel_device_info_init_mmio(dev_priv);
This should be called during intel_uncore_fw_domains_init after
         fw_domain_init(.., FW_DOMAIN_ID_BLITTER, ..);
> +
>   	intel_uncore_init(dev_priv);
>   
>   	intel_uc_init_mmio(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 65e674668b2e..ba16c2025364 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3438,6 +3438,7 @@ void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
>   void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
>   void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
>   
> +void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);
>   void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
>   void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
>   				       struct sg_table *pages);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b6cd725ff0b7..2b8d3a13dd27 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2860,6 +2860,11 @@ enum i915_power_well_id {
>   #define GEN10_EU_DISABLE3		_MMIO(0x9140)
>   #define   GEN10_EU_DIS_SS_MASK		0xff
>   
> +#define GEN11_GT_VEBOX_VDBOX_DISABLE	_MMIO(0x9140)
> +#define GEN11_GT_VDBOX_DISABLE_MASK	0xff
> +#define GEN11_GT_VEBOX_DISABLE_SHIFT	16
> +#define GEN11_GT_VEBOX_DISABLE_MASK	(0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
> +
>   #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
>   #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
>   #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 9352f34e75c4..7c8779faf162 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -595,3 +595,57 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps,
>   {
>   	drm_printf(p, "scheduler: %x\n", caps->scheduler);
>   }
> +
> +/*
> + * Determine which engines are fused off in our particular hardware.
> + *
> + * This function needs to be called after the MMIO has been setup (as we need
> + * to read registers) but before uncore init (because the powerwell for the
> + * fused off engines doesn't exist, so we cannot initialize forcewake for them)
> + */
> +void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
How about naming this function as intel_uncore_runtime_fw_domains_init 
such that fw_domain_init for each of the
unfused engines in next patch get called as part of this. Additional 
effect is update of device info.
Calling intel_uncore_runtime_fw_domains_init from 
intel_uncore_fw_domains_init and calls to intel_device_info_init*
from i915_driver_init_* paths seems to make code consistent.
> +{
> +	struct intel_device_info *info = mkwrite_device_info(dev_priv);
> +	u8 vdbox_disable, vebox_disable;
> +	u32 media_fuse;
> +	int i;
> +
> +	if (INTEL_GEN(dev_priv) < 11)
> +		return;
> +
> +	GEM_BUG_ON(!dev_priv->regs);
> +
> +	media_fuse = I915_READ_FW(GEN11_GT_VEBOX_VDBOX_DISABLE);
this should be
fw_domains_get(dev_priv, FORCEWAKE_BLITTER);
media_fuse = I915_READ_FW(GEN11, GT_VEBOX_VDBOX_DISABLE);
fw_domains_put(dev_priv, FORCEWAKE_BLITTER);

Earlier I had thought of calling ASSIGN_FW_DOMAINS_TABLE, 
ASSIGN_*_MMIO_VFUNCS before intel_uncore_fw_domains_init
and use I915_READ here for reading the fuse. But that approach seems to 
expose the vfuncs and forcewake table before fw domains
are initialized. Although we can get to know invalid access to 
read/write accessors before fw_domains get initialized, current ordering
of fw_domains init followed by fw domain table/read/write vfuncs init 
seems right. So using fw_domains_get/put as suggested above
should be the way.

Chris, Tvrtko, Mika, do you agree?
> +
> +	vdbox_disable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> +	vebox_disable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> +			GEN11_GT_VEBOX_DISABLE_SHIFT;
> +
> +	DRM_DEBUG_DRIVER("vdbox disable: %04x\n", vdbox_disable);
> +	for (i = 0; i < I915_MAX_VCS; i++) {
> +		if (!HAS_ENGINE(dev_priv, _VCS(i)))
> +			continue;
> +
> +		if (!(BIT(i) & vdbox_disable))
> +			continue;
> +
> +		info->ring_mask &= ~ENGINE_MASK(_VCS(i));
> +		WARN_ON(dev_priv->uncore.fw_domains &
> +			BIT(FW_DOMAIN_ID_MEDIA_VDBOX0 + i));
> +		DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
> +	}
> +
> +	DRM_DEBUG_DRIVER("vebox disable: %04x\n", vebox_disable);
> +	for (i = 0; i < I915_MAX_VECS; i++) {
> +		if (!HAS_ENGINE(dev_priv, _VECS(i)))
> +			continue;
> +
> +		if (!(BIT(i) & vebox_disable))
> +			continue;
> +
> +		info->ring_mask &= ~ENGINE_MASK(_VECS(i));
> +		WARN_ON(dev_priv->uncore.fw_domains &
> +			BIT(FW_DOMAIN_ID_MEDIA_VEBOX0 + i));
> +		DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
> +	}
> +}

-- 
Thanks,
Sagar

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Re: [PATCH 12/20] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Chris Wilson]

Quoting Sagar Arun Kamble (2018-02-17 08:51:44)
> Earlier I had thought of calling ASSIGN_FW_DOMAINS_TABLE, 
> ASSIGN_*_MMIO_VFUNCS before intel_uncore_fw_domains_init
> and use I915_READ here for reading the fuse. But that approach seems to 
> expose the vfuncs and forcewake table before fw domains
> are initialized. Although we can get to know invalid access to 
> read/write accessors before fw_domains get initialized, current ordering
> of fw_domains init followed by fw domain table/read/write vfuncs init 
> seems right. So using fw_domains_get/put as suggested above
> should be the way.
> 
> Chris, Tvrtko, Mika, do you agree?

What's the complication with the fw_domains? Do the additional powerwell
depend on the fused status of the extra engines? Does it matter if the
fw_domain are prepped if they are never used?

Imo, I would have placed the fused discovery in
intel_engines_init_mmio() (where we do the setup and can take forcewake).
Then adding something like intel_uncore_reinit_mmio() (which would just
prune the uncore->fw_domains) after checking fused status with commentary
doesn't seem that horrible.
-Chris
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Re: [PATCH 12/20] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Sagar Arun Kamble]

On 2/17/2018 2:34 PM, Chris Wilson wrote:
> Quoting Sagar Arun Kamble (2018-02-17 08:51:44)
>> Earlier I had thought of calling ASSIGN_FW_DOMAINS_TABLE,
>> ASSIGN_*_MMIO_VFUNCS before intel_uncore_fw_domains_init
>> and use I915_READ here for reading the fuse. But that approach seems to
>> expose the vfuncs and forcewake table before fw domains
>> are initialized. Although we can get to know invalid access to
>> read/write accessors before fw_domains get initialized, current ordering
>> of fw_domains init followed by fw domain table/read/write vfuncs init
>> seems right. So using fw_domains_get/put as suggested above
>> should be the way.
>>
>> Chris, Tvrtko, Mika, do you agree?
> What's the complication with the fw_domains? Do the additional powerwell
> depend on the fused status of the extra engines? Does it matter if the
> fw_domain are prepped if they are never used?
Yes. To discover the available VD/VE engines/power domains, fuse needs 
to be read under blitter forcewake as
RC6 will be enabled by BIOS. We do have usage of forcewake in IVB to 
discover FORCEWAKE_MT availability in fw_domains_init.
It should not be a problem if they are prepped but never used.
> Imo, I would have placed the fused discovery in
> intel_engines_init_mmio() (where we do the setup and can take forcewake).
> Then adding something like intel_uncore_reinit_mmio() (which would just
> prune the uncore->fw_domains) after checking fused status with commentary
> doesn't seem that horrible.
Yes. This approach looks good too. But, we might want to optimize the 
driver_load to avoid this setup at first place
instead of pruning later.
Another related setup that can be avoided/pruned is the fw_range for the 
engine fused off as it can improve the fw lookup.
> -Chris

-- 
Thanks,
Sagar

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Re: [PATCH 12/20] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Chris Wilson]

Quoting Sagar Arun Kamble (2018-02-17 12:10:32)
> 
> 
> On 2/17/2018 2:34 PM, Chris Wilson wrote:
> > Quoting Sagar Arun Kamble (2018-02-17 08:51:44)
> >> Earlier I had thought of calling ASSIGN_FW_DOMAINS_TABLE,
> >> ASSIGN_*_MMIO_VFUNCS before intel_uncore_fw_domains_init
> >> and use I915_READ here for reading the fuse. But that approach seems to
> >> expose the vfuncs and forcewake table before fw domains
> >> are initialized. Although we can get to know invalid access to
> >> read/write accessors before fw_domains get initialized, current ordering
> >> of fw_domains init followed by fw domain table/read/write vfuncs init
> >> seems right. So using fw_domains_get/put as suggested above
> >> should be the way.
> >>
> >> Chris, Tvrtko, Mika, do you agree?
> > What's the complication with the fw_domains? Do the additional powerwell
> > depend on the fused status of the extra engines? Does it matter if the
> > fw_domain are prepped if they are never used?
> Yes. To discover the available VD/VE engines/power domains, fuse needs 
> to be read under blitter forcewake as
> RC6 will be enabled by BIOS. We do have usage of forcewake in IVB to 
> discover FORCEWAKE_MT availability in fw_domains_init.
> It should not be a problem if they are prepped but never used.
> > Imo, I would have placed the fused discovery in
> > intel_engines_init_mmio() (where we do the setup and can take forcewake).
> > Then adding something like intel_uncore_reinit_mmio() (which would just
> > prune the uncore->fw_domains) after checking fused status with commentary
> > doesn't seem that horrible.
> Yes. This approach looks good too. But, we might want to optimize the 
> driver_load to avoid this setup at first place
> instead of pruning later.

How many cycles does it take to run through all domains and set up the
register offsets? No mmio access required right, we are just moving
memory around without even hitting locked instructions?

> Another related setup that can be avoided/pruned is the fw_range for the 
> engine fused off as it can improve the fw lookup.

Which is a bsearch on register range, I doubt that's going to be
substantially impacted by removing a few ranges. Where it matters, we
should be looking to precalculate the result anyway.
-Chris
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Re: [PATCH 12/20] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Sagar Arun Kamble]

On 2/17/2018 5:48 PM, Chris Wilson wrote:
> Quoting Sagar Arun Kamble (2018-02-17 12:10:32)
>>
>> On 2/17/2018 2:34 PM, Chris Wilson wrote:
>>> Quoting Sagar Arun Kamble (2018-02-17 08:51:44)
>>>> Earlier I had thought of calling ASSIGN_FW_DOMAINS_TABLE,
>>>> ASSIGN_*_MMIO_VFUNCS before intel_uncore_fw_domains_init
>>>> and use I915_READ here for reading the fuse. But that approach seems to
>>>> expose the vfuncs and forcewake table before fw domains
>>>> are initialized. Although we can get to know invalid access to
>>>> read/write accessors before fw_domains get initialized, current ordering
>>>> of fw_domains init followed by fw domain table/read/write vfuncs init
>>>> seems right. So using fw_domains_get/put as suggested above
>>>> should be the way.
>>>>
>>>> Chris, Tvrtko, Mika, do you agree?
>>> What's the complication with the fw_domains? Do the additional powerwell
>>> depend on the fused status of the extra engines? Does it matter if the
>>> fw_domain are prepped if they are never used?
>> Yes. To discover the available VD/VE engines/power domains, fuse needs
>> to be read under blitter forcewake as
>> RC6 will be enabled by BIOS. We do have usage of forcewake in IVB to
>> discover FORCEWAKE_MT availability in fw_domains_init.
>> It should not be a problem if they are prepped but never used.
>>> Imo, I would have placed the fused discovery in
>>> intel_engines_init_mmio() (where we do the setup and can take forcewake).
>>> Then adding something like intel_uncore_reinit_mmio() (which would just
>>> prune the uncore->fw_domains) after checking fused status with commentary
>>> doesn't seem that horrible.
>> Yes. This approach looks good too. But, we might want to optimize the
>> driver_load to avoid this setup at first place
>> instead of pruning later.
> How many cycles does it take to run through all domains and set up the
> register offsets? No mmio access required right, we are just moving
> memory around without even hitting locked instructions?
Yes. Latency is minimal. We can go with your suggestion. Will need to 
maintain separation of engine_cs/device_info/uncore update
through separate functions.
>> Another related setup that can be avoided/pruned is the fw_range for the
>> engine fused off as it can improve the fw lookup.
> Which is a bsearch on register range, I doubt that's going to be
> substantially impacted by removing a few ranges. Where it matters, we
> should be looking to precalculate the result anyway.
Yes. seems not so worth.
> -Chris

-- 
Thanks,
Sagar

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Re: [PATCH 12/20] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Daniele Ceraolo Spurio]

On 17/02/18 06:17, Sagar Arun Kamble wrote:
> 
> 
> On 2/17/2018 5:48 PM, Chris Wilson wrote:
>> Quoting Sagar Arun Kamble (2018-02-17 12:10:32)
>>>
>>> On 2/17/2018 2:34 PM, Chris Wilson wrote:
>>>> Quoting Sagar Arun Kamble (2018-02-17 08:51:44)
>>>>> Earlier I had thought of calling ASSIGN_FW_DOMAINS_TABLE,
>>>>> ASSIGN_*_MMIO_VFUNCS before intel_uncore_fw_domains_init
>>>>> and use I915_READ here for reading the fuse. But that approach 
>>>>> seems to
>>>>> expose the vfuncs and forcewake table before fw domains
>>>>> are initialized. Although we can get to know invalid access to
>>>>> read/write accessors before fw_domains get initialized, current 
>>>>> ordering
>>>>> of fw_domains init followed by fw domain table/read/write vfuncs init
>>>>> seems right. So using fw_domains_get/put as suggested above
>>>>> should be the way.
>>>>>
>>>>> Chris, Tvrtko, Mika, do you agree?
>>>> What's the complication with the fw_domains? Do the additional 
>>>> powerwell
>>>> depend on the fused status of the extra engines? Does it matter if the
>>>> fw_domain are prepped if they are never used?
>>> Yes. To discover the available VD/VE engines/power domains, fuse needs
>>> to be read under blitter forcewake as
>>> RC6 will be enabled by BIOS. We do have usage of forcewake in IVB to
>>> discover FORCEWAKE_MT availability in fw_domains_init.
>>> It should not be a problem if they are prepped but never used.
>>>> Imo, I would have placed the fused discovery in
>>>> intel_engines_init_mmio() (where we do the setup and can take 
>>>> forcewake).
>>>> Then adding something like intel_uncore_reinit_mmio() (which would just
>>>> prune the uncore->fw_domains) after checking fused status with 
>>>> commentary
>>>> doesn't seem that horrible.
>>> Yes. This approach looks good too. But, we might want to optimize the
>>> driver_load to avoid this setup at first place
>>> instead of pruning later.
>> How many cycles does it take to run through all domains and set up the
>> register offsets? No mmio access required right, we are just moving
>> memory around without even hitting locked instructions?
> Yes. Latency is minimal. We can go with your suggestion. Will need to 
> maintain separation of engine_cs/device_info/uncore update
> through separate functions.

We do currently call fw_domain_reset on all domains at initialization 
time, which could write to a register that doesn't exist. We don't wait 
for the ack and I assume the write would just be dropped if the power 
well is not there so it shouldn't be an issue, but it might be worth 
adding a comment in fw_domain_reset to remind us that we can't start 
waiting for the ack in there unless we move the fuse read to an earlier 
point.

Daniele

>>> Another related setup that can be avoided/pruned is the fw_range for the
>>> engine fused off as it can improve the fw lookup.
>> Which is a bsearch on register range, I doubt that's going to be
>> substantially impacted by removing a few ranges. Where it matters, we
>> should be looking to precalculate the result anyway.
> Yes. seems not so worth.
>> -Chris
> 
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[PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Oscar Mateo]

In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the
Video Enhancement engines (aka VEBOX, aka VECS) could be fused off. Also,
each VDBOX and VEBOX has its own power well, which only exist if the related
engine exists in the HW.

Unfortunately, we have a Catch-22 situation going on: we need the blitter
forcewake to read the register with the fuse info, but we cannot initialize
the forcewake domains without knowin about the engines present in the HW.
We workaround this problem by pruning the forcewake domains after reading
the fuse information.

Bspec: 20680

v2: We were shifting incorrectly for vebox disable (Vinay)

v3: Assert mmio is ready and warn if we have attempted to initialize
    forcewake for fused-off engines (Paulo)

v4:
  - Use INTEL_GEN in new code (Tvrtko)
  - Shorter local variable (Tvrtko, Michal)
  - Keep "if (!...) continue" style (Tvrtko)
  - No unnecessary BUG_ON (Tvrtko)
  - WARN_ON and cleanup if wrong mask (Tvrtko, Michal)
  - Use I915_READ_FW (Michal)
  - Use I915_MAX_VCS/VECS macros (Michal)

v5: Rebased by Rodrigo fixing conflicts on top of:
    commit 33def1ff7b0 ("drm/i915: Simplify intel_engines_init")

v6: Fix v5. Remove info->num_rings. (by Oscar)

v7: Rebase (Rodrigo).

v8:
  - s/intel_device_info_fused_off_engines/intel_device_info_init_mmio (Chris)
  - Make vdbox_disable & vebox_disable local variables (Chris)

v9:
  - Move function declaration to intel_device_info.h (Michal)
  - Missing indent in bit fields definitions (Michal)
  - When RC6 is enabled by BIOS, the fuse register cannot be read until
    the blitter powerwell is awake. Shuffle where the fuse is read, prune
    the forcewake domains after the fact and change the commit message
    accordingly (Vinay, Sagar, Chris).

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c          |  4 +++
 drivers/gpu/drm/i915/i915_reg.h          |  5 +++
 drivers/gpu/drm/i915/intel_device_info.c | 47 +++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_device_info.h |  1 +
 drivers/gpu/drm/i915/intel_uncore.c      | 55 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_uncore.h      |  1 +
 6 files changed, 113 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d09f8e6..2269b56 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1031,6 +1031,10 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 
 	intel_uncore_init(dev_priv);
 
+	intel_device_info_init_mmio(dev_priv);
+
+	intel_uncore_prune(dev_priv);
+
 	intel_uc_init_mmio(dev_priv);
 
 	ret = intel_engines_init_mmio(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 784d79c..e6a0d84 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2854,6 +2854,11 @@ enum i915_power_well_id {
 #define GEN10_EU_DISABLE3		_MMIO(0x9140)
 #define   GEN10_EU_DIS_SS_MASK		0xff
 
+#define GEN11_GT_VEBOX_VDBOX_DISABLE	_MMIO(0x9140)
+#define   GEN11_GT_VDBOX_DISABLE_MASK	0xff
+#define   GEN11_GT_VEBOX_DISABLE_SHIFT	16
+#define   GEN11_GT_VEBOX_DISABLE_MASK	(0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
+
 #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
 #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
 #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 9352f34..70ea654 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -595,3 +595,50 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps,
 {
 	drm_printf(p, "scheduler: %x\n", caps->scheduler);
 }
+
+/*
+ * Determine which engines are fused off in our particular hardware. Since the
+ * fuse register is in the blitter powerwell, we need forcewake to be ready at
+ * this point (but later we need to prune the forcewake domains for engines that
+ * are indeed fused off).
+ */
+void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
+{
+	struct intel_device_info *info = mkwrite_device_info(dev_priv);
+	u8 vdbox_disable, vebox_disable;
+	u32 media_fuse;
+	int i;
+
+	if (INTEL_GEN(dev_priv) < 11)
+		return;
+
+	media_fuse = I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
+
+	vdbox_disable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
+	vebox_disable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
+			GEN11_GT_VEBOX_DISABLE_SHIFT;
+
+	DRM_DEBUG_DRIVER("vdbox disable: %04x\n", vdbox_disable);
+	for (i = 0; i < I915_MAX_VCS; i++) {
+		if (!HAS_ENGINE(dev_priv, _VCS(i)))
+			continue;
+
+		if (!(BIT(i) & vdbox_disable))
+			continue;
+
+		info->ring_mask &= ~ENGINE_MASK(_VCS(i));
+		DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
+	}
+
+	DRM_DEBUG_DRIVER("vebox disable: %04x\n", vebox_disable);
+	for (i = 0; i < I915_MAX_VECS; i++) {
+		if (!HAS_ENGINE(dev_priv, _VECS(i)))
+			continue;
+
+		if (!(BIT(i) & vebox_disable))
+			continue;
+
+		info->ring_mask &= ~ENGINE_MASK(_VECS(i));
+		DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
+	}
+}
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4c6f83b..2233a2f 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -187,6 +187,7 @@ void intel_device_info_dump_flags(const struct intel_device_info *info,
 				  struct drm_printer *p);
 void intel_device_info_dump_runtime(const struct intel_device_info *info,
 				    struct drm_printer *p);
+void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);
 
 void intel_driver_caps_print(const struct intel_driver_caps *caps,
 			     struct drm_printer *p);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 5ae9a62..5de0d26 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -56,6 +56,10 @@
 fw_domain_reset(struct drm_i915_private *i915,
 		const struct intel_uncore_forcewake_domain *d)
 {
+	/*
+	 * We don't really know if the powerwell for the forcewake domain we are
+	 * trying to reset here does exist at this point, so no waiting for acks
+	 */
 	__raw_i915_write32(i915, d->reg_set, i915->uncore.fw_reset);
 }
 
@@ -1251,6 +1255,23 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
 	fw_domain_reset(dev_priv, d);
 }
 
+static void fw_domain_fini(struct drm_i915_private *dev_priv,
+			   enum forcewake_domain_id domain_id)
+{
+	struct intel_uncore_forcewake_domain *d;
+
+	if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
+		return;
+
+	d = &dev_priv->uncore.fw_domain[domain_id];
+
+	WARN_ON(d->wake_count);
+	WARN_ON(hrtimer_cancel(&d->timer));
+	memset(d, 0, sizeof(*d));
+
+	dev_priv->uncore.fw_domains &= ~BIT(domain_id);
+}
+
 static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
 {
 	if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
@@ -1432,6 +1453,40 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
 		&dev_priv->uncore.pmic_bus_access_nb);
 }
 
+/*
+ * We might have detected that some engines are fused off after we initialized
+ * the forcewake domains. Prune them, to make sure they only reference existing
+ * engines.
+ */
+void intel_uncore_prune(struct drm_i915_private *dev_priv)
+{
+	if (INTEL_GEN(dev_priv) >= 11) {
+		enum forcewake_domains fw_domains = dev_priv->uncore.fw_domains;
+		enum forcewake_domain_id domain_id;
+		int i;
+
+		for (i = 0; i < I915_MAX_VCS; i++) {
+			domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
+
+			if (HAS_ENGINE(dev_priv, _VCS(i)))
+				continue;
+
+			if (fw_domains & BIT(domain_id))
+				fw_domain_fini(dev_priv, domain_id);
+		}
+
+		for (i = 0; i < I915_MAX_VECS; i++) {
+			domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
+
+			if (HAS_ENGINE(dev_priv, _VECS(i)))
+				continue;
+
+			if (fw_domains & BIT(domain_id))
+				fw_domain_fini(dev_priv, domain_id);
+		}
+	}
+}
+
 void intel_uncore_fini(struct drm_i915_private *dev_priv)
 {
 	/* Paranoia: make sure we have disabled everything before we exit. */
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 53ef77d..28feabf 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -129,6 +129,7 @@ struct intel_uncore {
 
 void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
 void intel_uncore_init(struct drm_i915_private *dev_priv);
+void intel_uncore_prune(struct drm_i915_private *dev_priv);
 bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
 bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
 void intel_uncore_fini(struct drm_i915_private *dev_priv);
-- 
1.9.1

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✗ Fi.CI.BAT: failure for ICL GEM enabling (v2) (rev6)

[Patchwork]

== Series Details ==

Series: ICL GEM enabling (v2) (rev6)
URL   : https://patchwork.freedesktop.org/series/38174/
State : failure

== Summary ==

Applying: drm/i915/icl: Add the ICL PCI IDs
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/i915_pci.c
M	include/drm/i915_pciids.h
Falling back to patching base and 3-way merge...
Auto-merging include/drm/i915_pciids.h
Auto-merging drivers/gpu/drm/i915/i915_pci.c
Applying: drm/i915/icl: add icelake_init_clock_gating()
Applying: drm/i915/icl: Show interrupt registers in debugfs
Applying: drm/i915/icl: Prepare for more rings
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/i915_drv.h
M	drivers/gpu/drm/i915/i915_reg.h
M	drivers/gpu/drm/i915/intel_ringbuffer.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_ringbuffer.h
Auto-merging drivers/gpu/drm/i915/i915_reg.h
Auto-merging drivers/gpu/drm/i915/i915_drv.h
Applying: drm/i915/icl: Interrupt handling
Applying: drm/i915/icl: Ringbuffer interrupt handling
Applying: drm/i915/icl: Correctly initialize the Gen11 engines
Applying: drm/i915/icl: new context descriptor support
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/i915_drv.h
M	drivers/gpu/drm/i915/i915_gem_context.c
M	drivers/gpu/drm/i915/i915_reg.h
M	drivers/gpu/drm/i915/intel_engine_cs.c
M	drivers/gpu/drm/i915/intel_lrc.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_lrc.c
Auto-merging drivers/gpu/drm/i915/intel_engine_cs.c
Auto-merging drivers/gpu/drm/i915/i915_reg.h
Auto-merging drivers/gpu/drm/i915/i915_gem_context.c
Auto-merging drivers/gpu/drm/i915/i915_drv.h
Applying: drm/i915/icl: Enhanced execution list support
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/i915_drv.h).
error: could not build fake ancestor
Patch failed at 0009 drm/i915/icl: Enhanced execution list support
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Sagar Arun Kamble]

Looks good to me. Few cosmetic changes suggested below. With those 
addressed:
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>

On 2/22/2018 5:05 AM, Oscar Mateo wrote:
> In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the
> Video Enhancement engines (aka VEBOX, aka VECS) could be fused off. Also,
> each VDBOX and VEBOX has its own power well, which only exist if the related
> engine exists in the HW.
>
> Unfortunately, we have a Catch-22 situation going on: we need the blitter
> forcewake to read the register with the fuse info, but we cannot initialize
> the forcewake domains without knowin about the engines present in the HW.
*knowing
> We workaround this problem by pruning the forcewake domains after reading
> the fuse information.
This line can be re-framed like:
"We workaround this problem by allowing initialization of all forcewake 
domains and then pruning the fused off forcewake domains
based on fuse info which can be read acquiring blitter forcewake"
>
> Bspec: 20680
>
> v2: We were shifting incorrectly for vebox disable (Vinay)
>
> v3: Assert mmio is ready and warn if we have attempted to initialize
>      forcewake for fused-off engines (Paulo)
>
> v4:
>    - Use INTEL_GEN in new code (Tvrtko)
>    - Shorter local variable (Tvrtko, Michal)
>    - Keep "if (!...) continue" style (Tvrtko)
>    - No unnecessary BUG_ON (Tvrtko)
>    - WARN_ON and cleanup if wrong mask (Tvrtko, Michal)
>    - Use I915_READ_FW (Michal)
>    - Use I915_MAX_VCS/VECS macros (Michal)
>
> v5: Rebased by Rodrigo fixing conflicts on top of:
>      commit 33def1ff7b0 ("drm/i915: Simplify intel_engines_init")
>
> v6: Fix v5. Remove info->num_rings. (by Oscar)
>
> v7: Rebase (Rodrigo).
>
> v8:
>    - s/intel_device_info_fused_off_engines/intel_device_info_init_mmio (Chris)
>    - Make vdbox_disable & vebox_disable local variables (Chris)
>
> v9:
>    - Move function declaration to intel_device_info.h (Michal)
>    - Missing indent in bit fields definitions (Michal)
>    - When RC6 is enabled by BIOS, the fuse register cannot be read until
>      the blitter powerwell is awake. Shuffle where the fuse is read, prune
>      the forcewake domains after the fact and change the commit message
>      accordingly (Vinay, Sagar, Chris).
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_drv.c          |  4 +++
>   drivers/gpu/drm/i915/i915_reg.h          |  5 +++
>   drivers/gpu/drm/i915/intel_device_info.c | 47 +++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_device_info.h |  1 +
>   drivers/gpu/drm/i915/intel_uncore.c      | 55 ++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_uncore.h      |  1 +
>   6 files changed, 113 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index d09f8e6..2269b56 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1031,6 +1031,10 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
>   
>   	intel_uncore_init(dev_priv);
>   
> +	intel_device_info_init_mmio(dev_priv);
> +
> +	intel_uncore_prune(dev_priv);
> +
>   	intel_uc_init_mmio(dev_priv);
>   
>   	ret = intel_engines_init_mmio(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 784d79c..e6a0d84 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2854,6 +2854,11 @@ enum i915_power_well_id {
>   #define GEN10_EU_DISABLE3		_MMIO(0x9140)
>   #define   GEN10_EU_DIS_SS_MASK		0xff
>   
> +#define GEN11_GT_VEBOX_VDBOX_DISABLE	_MMIO(0x9140)
> +#define   GEN11_GT_VDBOX_DISABLE_MASK	0xff
> +#define   GEN11_GT_VEBOX_DISABLE_SHIFT	16
> +#define   GEN11_GT_VEBOX_DISABLE_MASK	(0xff << GEN11_GT_VEBOX_DISABLE_SHIFT)
> +
>   #define GEN6_BSD_SLEEP_PSMI_CONTROL	_MMIO(0x12050)
>   #define   GEN6_BSD_SLEEP_MSG_DISABLE	(1 << 0)
>   #define   GEN6_BSD_SLEEP_FLUSH_DISABLE	(1 << 2)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 9352f34..70ea654 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -595,3 +595,50 @@ void intel_driver_caps_print(const struct intel_driver_caps *caps,
>   {
>   	drm_printf(p, "scheduler: %x\n", caps->scheduler);
>   }
> +
> +/*
> + * Determine which engines are fused off in our particular hardware. Since the
> + * fuse register is in the blitter powerwell, we need forcewake to be ready at
> + * this point (but later we need to prune the forcewake domains for engines that
> + * are indeed fused off).
> + */
> +void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
> +{
> +	struct intel_device_info *info = mkwrite_device_info(dev_priv);
> +	u8 vdbox_disable, vebox_disable;
> +	u32 media_fuse;
> +	int i;
> +
> +	if (INTEL_GEN(dev_priv) < 11)
> +		return;
> +
> +	media_fuse = I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
> +
> +	vdbox_disable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
> +	vebox_disable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
> +			GEN11_GT_VEBOX_DISABLE_SHIFT;
> +
> +	DRM_DEBUG_DRIVER("vdbox disable: %04x\n", vdbox_disable);
> +	for (i = 0; i < I915_MAX_VCS; i++) {
> +		if (!HAS_ENGINE(dev_priv, _VCS(i)))
> +			continue;
> +
> +		if (!(BIT(i) & vdbox_disable))
> +			continue;
> +
> +		info->ring_mask &= ~ENGINE_MASK(_VCS(i));
> +		DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
> +	}
> +
> +	DRM_DEBUG_DRIVER("vebox disable: %04x\n", vebox_disable);
> +	for (i = 0; i < I915_MAX_VECS; i++) {
> +		if (!HAS_ENGINE(dev_priv, _VECS(i)))
> +			continue;
> +
> +		if (!(BIT(i) & vebox_disable))
> +			continue;
> +
> +		info->ring_mask &= ~ENGINE_MASK(_VECS(i));
> +		DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
> +	}
> +}
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index 4c6f83b..2233a2f 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -187,6 +187,7 @@ void intel_device_info_dump_flags(const struct intel_device_info *info,
>   				  struct drm_printer *p);
>   void intel_device_info_dump_runtime(const struct intel_device_info *info,
>   				    struct drm_printer *p);
May be we need to add extra line to differentiate from 
"device_info_*_runtime_*" function declarations.
> +void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);
>   
>   void intel_driver_caps_print(const struct intel_driver_caps *caps,
>   			     struct drm_printer *p);
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 5ae9a62..5de0d26 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -56,6 +56,10 @@
>   fw_domain_reset(struct drm_i915_private *i915,
>   		const struct intel_uncore_forcewake_domain *d)
>   {
> +	/*
> +	 * We don't really know if the powerwell for the forcewake domain we are
> +	 * trying to reset here does exist at this point, so no waiting for acks
> +	 */
We should also add that this applies to ICL.
>   	__raw_i915_write32(i915, d->reg_set, i915->uncore.fw_reset);
>   }
>   
> @@ -1251,6 +1255,23 @@ static void fw_domain_init(struct drm_i915_private *dev_priv,
>   	fw_domain_reset(dev_priv, d);
>   }
>   
> +static void fw_domain_fini(struct drm_i915_private *dev_priv,
> +			   enum forcewake_domain_id domain_id)
> +{
> +	struct intel_uncore_forcewake_domain *d;
> +
> +	if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
> +		return;
> +
> +	d = &dev_priv->uncore.fw_domain[domain_id];
> +
> +	WARN_ON(d->wake_count);
> +	WARN_ON(hrtimer_cancel(&d->timer));
> +	memset(d, 0, sizeof(*d));
> +
> +	dev_priv->uncore.fw_domains &= ~BIT(domain_id);
> +}
> +
>   static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
>   {
>   	if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
> @@ -1432,6 +1453,40 @@ void intel_uncore_init(struct drm_i915_private *dev_priv)
>   		&dev_priv->uncore.pmic_bus_access_nb);
>   }
>   
> +/*
> + * We might have detected that some engines are fused off after we initialized
> + * the forcewake domains. Prune them, to make sure they only reference existing
> + * engines.
> + */
> +void intel_uncore_prune(struct drm_i915_private *dev_priv)
> +{
> +	if (INTEL_GEN(dev_priv) >= 11) {
> +		enum forcewake_domains fw_domains = dev_priv->uncore.fw_domains;
> +		enum forcewake_domain_id domain_id;
> +		int i;
> +
> +		for (i = 0; i < I915_MAX_VCS; i++) {
> +			domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
> +
> +			if (HAS_ENGINE(dev_priv, _VCS(i)))
> +				continue;
> +
> +			if (fw_domains & BIT(domain_id))
fw_domains check seems redundant as it is initialized based on HAS_ENGINE.
we can just have
if (!HAS_ENGINE(dev_priv, _VCS(i)))
     fw_domain_fini(dev_priv, domain_id);
> +				fw_domain_fini(dev_priv, domain_id);
> +		}
> +
> +		for (i = 0; i < I915_MAX_VECS; i++) {
> +			domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
> +
> +			if (HAS_ENGINE(dev_priv, _VECS(i)))
> +				continue;
> +
> +			if (fw_domains & BIT(domain_id))
> +				fw_domain_fini(dev_priv, domain_id);
> +		}
> +	}
> +}
> +
>   void intel_uncore_fini(struct drm_i915_private *dev_priv)
>   {
>   	/* Paranoia: make sure we have disabled everything before we exit. */
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index 53ef77d..28feabf 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -129,6 +129,7 @@ struct intel_uncore {
>   
>   void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
>   void intel_uncore_init(struct drm_i915_private *dev_priv);
> +void intel_uncore_prune(struct drm_i915_private *dev_priv);
>   bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
>   bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
>   void intel_uncore_fini(struct drm_i915_private *dev_priv);

-- 
Thanks,
Sagar

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Re: [PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Oscar Mateo]

On 2/21/2018 10:17 PM, Sagar Arun Kamble wrote:
> Looks good to me. Few cosmetic changes suggested below. With those 
> addressed:
> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>
> On 2/22/2018 5:05 AM, Oscar Mateo wrote:
>> In Gen11, the Video Decode engines (aka VDBOX, aka VCS, aka BSD) and the
>> Video Enhancement engines (aka VEBOX, aka VECS) could be fused off. 
>> Also,
>> each VDBOX and VEBOX has its own power well, which only exist if the 
>> related
>> engine exists in the HW.
>>
>> Unfortunately, we have a Catch-22 situation going on: we need the 
>> blitter
>> forcewake to read the register with the fuse info, but we cannot 
>> initialize
>> the forcewake domains without knowin about the engines present in the 
>> HW.
> *knowing
>> We workaround this problem by pruning the forcewake domains after 
>> reading
>> the fuse information.
> This line can be re-framed like:
> "We workaround this problem by allowing initialization of all 
> forcewake domains and then pruning the fused off forcewake domains
> based on fuse info which can be read acquiring blitter forcewake"

Can do.

>>
>> Bspec: 20680
>>
>> v2: We were shifting incorrectly for vebox disable (Vinay)
>>
>> v3: Assert mmio is ready and warn if we have attempted to initialize
>>      forcewake for fused-off engines (Paulo)
>>
>> v4:
>>    - Use INTEL_GEN in new code (Tvrtko)
>>    - Shorter local variable (Tvrtko, Michal)
>>    - Keep "if (!...) continue" style (Tvrtko)
>>    - No unnecessary BUG_ON (Tvrtko)
>>    - WARN_ON and cleanup if wrong mask (Tvrtko, Michal)
>>    - Use I915_READ_FW (Michal)
>>    - Use I915_MAX_VCS/VECS macros (Michal)
>>
>> v5: Rebased by Rodrigo fixing conflicts on top of:
>>      commit 33def1ff7b0 ("drm/i915: Simplify intel_engines_init")
>>
>> v6: Fix v5. Remove info->num_rings. (by Oscar)
>>
>> v7: Rebase (Rodrigo).
>>
>> v8:
>>    - 
>> s/intel_device_info_fused_off_engines/intel_device_info_init_mmio 
>> (Chris)
>>    - Make vdbox_disable & vebox_disable local variables (Chris)
>>
>> v9:
>>    - Move function declaration to intel_device_info.h (Michal)
>>    - Missing indent in bit fields definitions (Michal)
>>    - When RC6 is enabled by BIOS, the fuse register cannot be read until
>>      the blitter powerwell is awake. Shuffle where the fuse is read, 
>> prune
>>      the forcewake domains after the fact and change the commit message
>>      accordingly (Vinay, Sagar, Chris).
>>
>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.c          |  4 +++
>>   drivers/gpu/drm/i915/i915_reg.h          |  5 +++
>>   drivers/gpu/drm/i915/intel_device_info.c | 47 
>> +++++++++++++++++++++++++++
>>   drivers/gpu/drm/i915/intel_device_info.h |  1 +
>>   drivers/gpu/drm/i915/intel_uncore.c      | 55 
>> ++++++++++++++++++++++++++++++++
>>   drivers/gpu/drm/i915/intel_uncore.h      |  1 +
>>   6 files changed, 113 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c 
>> b/drivers/gpu/drm/i915/i915_drv.c
>> index d09f8e6..2269b56 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -1031,6 +1031,10 @@ static int i915_driver_init_mmio(struct 
>> drm_i915_private *dev_priv)
>>         intel_uncore_init(dev_priv);
>>   +    intel_device_info_init_mmio(dev_priv);
>> +
>> +    intel_uncore_prune(dev_priv);
>> +
>>       intel_uc_init_mmio(dev_priv);
>>         ret = intel_engines_init_mmio(dev_priv);
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 784d79c..e6a0d84 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2854,6 +2854,11 @@ enum i915_power_well_id {
>>   #define GEN10_EU_DISABLE3        _MMIO(0x9140)
>>   #define   GEN10_EU_DIS_SS_MASK        0xff
>>   +#define GEN11_GT_VEBOX_VDBOX_DISABLE    _MMIO(0x9140)
>> +#define   GEN11_GT_VDBOX_DISABLE_MASK    0xff
>> +#define   GEN11_GT_VEBOX_DISABLE_SHIFT    16
>> +#define   GEN11_GT_VEBOX_DISABLE_MASK    (0xff << 
>> GEN11_GT_VEBOX_DISABLE_SHIFT)
>> +
>>   #define GEN6_BSD_SLEEP_PSMI_CONTROL    _MMIO(0x12050)
>>   #define   GEN6_BSD_SLEEP_MSG_DISABLE    (1 << 0)
>>   #define   GEN6_BSD_SLEEP_FLUSH_DISABLE    (1 << 2)
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.c 
>> b/drivers/gpu/drm/i915/intel_device_info.c
>> index 9352f34..70ea654 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.c
>> +++ b/drivers/gpu/drm/i915/intel_device_info.c
>> @@ -595,3 +595,50 @@ void intel_driver_caps_print(const struct 
>> intel_driver_caps *caps,
>>   {
>>       drm_printf(p, "scheduler: %x\n", caps->scheduler);
>>   }
>> +
>> +/*
>> + * Determine which engines are fused off in our particular hardware. 
>> Since the
>> + * fuse register is in the blitter powerwell, we need forcewake to 
>> be ready at
>> + * this point (but later we need to prune the forcewake domains for 
>> engines that
>> + * are indeed fused off).
>> + */
>> +void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
>> +{
>> +    struct intel_device_info *info = mkwrite_device_info(dev_priv);
>> +    u8 vdbox_disable, vebox_disable;
>> +    u32 media_fuse;
>> +    int i;
>> +
>> +    if (INTEL_GEN(dev_priv) < 11)
>> +        return;
>> +
>> +    media_fuse = I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
>> +
>> +    vdbox_disable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
>> +    vebox_disable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
>> +            GEN11_GT_VEBOX_DISABLE_SHIFT;
>> +
>> +    DRM_DEBUG_DRIVER("vdbox disable: %04x\n", vdbox_disable);
>> +    for (i = 0; i < I915_MAX_VCS; i++) {
>> +        if (!HAS_ENGINE(dev_priv, _VCS(i)))
>> +            continue;
>> +
>> +        if (!(BIT(i) & vdbox_disable))
>> +            continue;
>> +
>> +        info->ring_mask &= ~ENGINE_MASK(_VCS(i));
>> +        DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
>> +    }
>> +
>> +    DRM_DEBUG_DRIVER("vebox disable: %04x\n", vebox_disable);
>> +    for (i = 0; i < I915_MAX_VECS; i++) {
>> +        if (!HAS_ENGINE(dev_priv, _VECS(i)))
>> +            continue;
>> +
>> +        if (!(BIT(i) & vebox_disable))
>> +            continue;
>> +
>> +        info->ring_mask &= ~ENGINE_MASK(_VECS(i));
>> +        DRM_DEBUG_DRIVER("vecs%u fused off\n", i);
>> +    }
>> +}
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
>> b/drivers/gpu/drm/i915/intel_device_info.h
>> index 4c6f83b..2233a2f 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -187,6 +187,7 @@ void intel_device_info_dump_flags(const struct 
>> intel_device_info *info,
>>                     struct drm_printer *p);
>>   void intel_device_info_dump_runtime(const struct intel_device_info 
>> *info,
>>                       struct drm_printer *p);
> May be we need to add extra line to differentiate from 
> "device_info_*_runtime_*" function declarations.

Can do.

>> +void intel_device_info_init_mmio(struct drm_i915_private *dev_priv);
>>     void intel_driver_caps_print(const struct intel_driver_caps *caps,
>>                    struct drm_printer *p);
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c 
>> b/drivers/gpu/drm/i915/intel_uncore.c
>> index 5ae9a62..5de0d26 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -56,6 +56,10 @@
>>   fw_domain_reset(struct drm_i915_private *i915,
>>           const struct intel_uncore_forcewake_domain *d)
>>   {
>> +    /*
>> +     * We don't really know if the powerwell for the forcewake 
>> domain we are
>> +     * trying to reset here does exist at this point, so no waiting 
>> for acks
>> +     */
> We should also add that this applies to ICL.

Can do.

>>       __raw_i915_write32(i915, d->reg_set, i915->uncore.fw_reset);
>>   }
>>   @@ -1251,6 +1255,23 @@ static void fw_domain_init(struct 
>> drm_i915_private *dev_priv,
>>       fw_domain_reset(dev_priv, d);
>>   }
>>   +static void fw_domain_fini(struct drm_i915_private *dev_priv,
>> +               enum forcewake_domain_id domain_id)
>> +{
>> +    struct intel_uncore_forcewake_domain *d;
>> +
>> +    if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
>> +        return;
>> +
>> +    d = &dev_priv->uncore.fw_domain[domain_id];
>> +
>> +    WARN_ON(d->wake_count);
>> +    WARN_ON(hrtimer_cancel(&d->timer));
>> +    memset(d, 0, sizeof(*d));
>> +
>> +    dev_priv->uncore.fw_domains &= ~BIT(domain_id);
>> +}
>> +
>>   static void intel_uncore_fw_domains_init(struct drm_i915_private 
>> *dev_priv)
>>   {
>>       if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv))
>> @@ -1432,6 +1453,40 @@ void intel_uncore_init(struct drm_i915_private 
>> *dev_priv)
>>           &dev_priv->uncore.pmic_bus_access_nb);
>>   }
>>   +/*
>> + * We might have detected that some engines are fused off after we 
>> initialized
>> + * the forcewake domains. Prune them, to make sure they only 
>> reference existing
>> + * engines.
>> + */
>> +void intel_uncore_prune(struct drm_i915_private *dev_priv)
>> +{
>> +    if (INTEL_GEN(dev_priv) >= 11) {
>> +        enum forcewake_domains fw_domains = 
>> dev_priv->uncore.fw_domains;
>> +        enum forcewake_domain_id domain_id;
>> +        int i;
>> +
>> +        for (i = 0; i < I915_MAX_VCS; i++) {
>> +            domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
>> +
>> +            if (HAS_ENGINE(dev_priv, _VCS(i)))
>> +                continue;
>> +
>> +            if (fw_domains & BIT(domain_id))
> fw_domains check seems redundant as it is initialized based on 
> HAS_ENGINE.
> we can just have
> if (!HAS_ENGINE(dev_priv, _VCS(i)))
>     fw_domain_fini(dev_priv, domain_id);

I don't want to call fw_domain_fini on something we never initialized in 
the first place (e.g. VCS1/3 and VECS1/2/3 on an ICL-LP).

>> +                fw_domain_fini(dev_priv, domain_id);
>> +        }
>> +
>> +        for (i = 0; i < I915_MAX_VECS; i++) {
>> +            domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
>> +
>> +            if (HAS_ENGINE(dev_priv, _VECS(i)))
>> +                continue;
>> +
>> +            if (fw_domains & BIT(domain_id))
>> +                fw_domain_fini(dev_priv, domain_id);
>> +        }
>> +    }
>> +}
>> +
>>   void intel_uncore_fini(struct drm_i915_private *dev_priv)
>>   {
>>       /* Paranoia: make sure we have disabled everything before we 
>> exit. */
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.h 
>> b/drivers/gpu/drm/i915/intel_uncore.h
>> index 53ef77d..28feabf 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.h
>> +++ b/drivers/gpu/drm/i915/intel_uncore.h
>> @@ -129,6 +129,7 @@ struct intel_uncore {
>>     void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
>>   void intel_uncore_init(struct drm_i915_private *dev_priv);
>> +void intel_uncore_prune(struct drm_i915_private *dev_priv);
>>   bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
>>   bool intel_uncore_arm_unclaimed_mmio_detection(struct 
>> drm_i915_private *dev_priv);
>>   void intel_uncore_fini(struct drm_i915_private *dev_priv);
>

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Re: [PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 6866 bytes --]

Hi Oscar,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20180222]
[cannot apply to v4.16-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Oscar-Mateo/drm-i915-icl-Check-for-fused-off-VDBOX-and-VEBOX-instances/20180223-095336
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-x004-201807 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All error/warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_device_info.c: In function 'intel_device_info_init_mmio':
>> drivers/gpu/drm/i915/intel_device_info.c:619:18: error: 'I915_MAX_VCS' undeclared (first use in this function); did you mean 'I915_MAP_WC'?
     for (i = 0; i < I915_MAX_VCS; i++) {
                     ^~~~~~~~~~~~
                     I915_MAP_WC
   drivers/gpu/drm/i915/intel_device_info.c:619:18: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/i915/intel_device_info.c:631:18: error: 'I915_MAX_VECS' undeclared (first use in this function); did you mean 'I915_MAX_VCS'?
     for (i = 0; i < I915_MAX_VECS; i++) {
                     ^~~~~~~~~~~~~
                     I915_MAX_VCS
   In file included from include/linux/kernel.h:11:0,
                    from include/asm-generic/bug.h:18,
                    from arch/x86/include/asm/bug.h:82,
                    from include/linux/bug.h:5,
                    from include/linux/seq_file.h:7,
                    from include/drm/drm_print.h:31,
                    from drivers/gpu/drm/i915/intel_device_info.c:25:
>> drivers/gpu/drm/i915/intel_device_info.c:632:29: error: implicit declaration of function '_VECS'; did you mean '_VCS'? [-Werror=implicit-function-declaration]
      if (!HAS_ENGINE(dev_priv, _VECS(i)))
                                ^
   include/linux/bitops.h:7:28: note: in definition of macro 'BIT'
    #define BIT(nr)   (1UL << (nr))
                               ^~
   drivers/gpu/drm/i915/i915_drv.h:2752:35: note: in expansion of macro 'ENGINE_MASK'
     (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
                                      ^~~~~~~~~~~
>> drivers/gpu/drm/i915/intel_device_info.c:632:8: note: in expansion of macro 'HAS_ENGINE'
      if (!HAS_ENGINE(dev_priv, _VECS(i)))
           ^~~~~~~~~~
   cc1: some warnings being treated as errors
--
   drivers/gpu/drm/i915/intel_uncore.c: In function 'intel_uncore_prune':
>> drivers/gpu/drm/i915/intel_uncore.c:1468:19: error: 'I915_MAX_VCS' undeclared (first use in this function); did you mean 'I915_MAP_WC'?
      for (i = 0; i < I915_MAX_VCS; i++) {
                      ^~~~~~~~~~~~
                      I915_MAP_WC
   drivers/gpu/drm/i915/intel_uncore.c:1468:19: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/i915/intel_uncore.c:1469:16: error: 'FW_DOMAIN_ID_MEDIA_VDBOX0' undeclared (first use in this function); did you mean 'FW_DOMAIN_ID_MEDIA'?
       domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
                   ^~~~~~~~~~~~~~~~~~~~~~~~~
                   FW_DOMAIN_ID_MEDIA
>> drivers/gpu/drm/i915/intel_uncore.c:1478:19: error: 'I915_MAX_VECS' undeclared (first use in this function); did you mean 'I915_MAX_VCS'?
      for (i = 0; i < I915_MAX_VECS; i++) {
                      ^~~~~~~~~~~~~
                      I915_MAX_VCS
>> drivers/gpu/drm/i915/intel_uncore.c:1479:16: error: 'FW_DOMAIN_ID_MEDIA_VEBOX0' undeclared (first use in this function); did you mean 'FW_DOMAIN_ID_MEDIA_VDBOX0'?
       domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
                   ^~~~~~~~~~~~~~~~~~~~~~~~~
                   FW_DOMAIN_ID_MEDIA_VDBOX0
   In file included from include/linux/kernel.h:11:0,
                    from include/asm-generic/bug.h:18,
                    from arch/x86/include/asm/bug.h:82,
                    from include/linux/bug.h:5,
                    from include/linux/mmdebug.h:5,
                    from include/linux/gfp.h:5,
                    from include/linux/slab.h:15,
                    from include/linux/io-mapping.h:22,
                    from drivers/gpu/drm/i915/i915_drv.h:36,
                    from drivers/gpu/drm/i915/intel_uncore.c:24:
>> drivers/gpu/drm/i915/intel_uncore.c:1481:29: error: implicit declaration of function '_VECS'; did you mean '_VCS'? [-Werror=implicit-function-declaration]
       if (HAS_ENGINE(dev_priv, _VECS(i)))
                                ^
   include/linux/bitops.h:7:28: note: in definition of macro 'BIT'
    #define BIT(nr)   (1UL << (nr))
                               ^~
   drivers/gpu/drm/i915/i915_drv.h:2752:35: note: in expansion of macro 'ENGINE_MASK'
     (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
                                      ^~~~~~~~~~~
   drivers/gpu/drm/i915/intel_uncore.c:1481:8: note: in expansion of macro 'HAS_ENGINE'
       if (HAS_ENGINE(dev_priv, _VECS(i)))
           ^~~~~~~~~~
   cc1: some warnings being treated as errors

vim +619 drivers/gpu/drm/i915/intel_device_info.c

   595	
   596	/*
   597	 * Determine which engines are fused off in our particular hardware. Since the
   598	 * fuse register is in the blitter powerwell, we need forcewake to be ready at
   599	 * this point (but later we need to prune the forcewake domains for engines that
   600	 * are indeed fused off).
   601	 */
   602	void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
   603	{
   604		struct intel_device_info *info = mkwrite_device_info(dev_priv);
   605		u8 vdbox_disable, vebox_disable;
   606		u32 media_fuse;
   607		int i;
   608	
   609		if (INTEL_GEN(dev_priv) < 11)
   610			return;
   611	
   612		media_fuse = I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
   613	
   614		vdbox_disable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
   615		vebox_disable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
   616				GEN11_GT_VEBOX_DISABLE_SHIFT;
   617	
   618		DRM_DEBUG_DRIVER("vdbox disable: %04x\n", vdbox_disable);
 > 619		for (i = 0; i < I915_MAX_VCS; i++) {
   620			if (!HAS_ENGINE(dev_priv, _VCS(i)))
   621				continue;
   622	
   623			if (!(BIT(i) & vdbox_disable))
   624				continue;
   625	
   626			info->ring_mask &= ~ENGINE_MASK(_VCS(i));
   627			DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
   628		}
   629	
   630		DRM_DEBUG_DRIVER("vebox disable: %04x\n", vebox_disable);
 > 631		for (i = 0; i < I915_MAX_VECS; i++) {
 > 632			if (!HAS_ENGINE(dev_priv, _VECS(i)))

---
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Re: [PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[kbuild test robot]

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Hi Oscar,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20180222]
[cannot apply to v4.16-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Oscar-Mateo/drm-i915-icl-Check-for-fused-off-VDBOX-and-VEBOX-instances/20180223-095336
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-a1-201807 (attached as .config)
compiler: gcc-4.9 (Debian 4.9.4-2) 4.9.4
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/i915/intel_device_info.c: In function 'intel_device_info_init_mmio':
>> drivers/gpu/drm/i915/intel_device_info.c:619:18: error: 'I915_MAX_VCS' undeclared (first use in this function)
     for (i = 0; i < I915_MAX_VCS; i++) {
                     ^
   drivers/gpu/drm/i915/intel_device_info.c:619:18: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/i915/intel_device_info.c:631:18: error: 'I915_MAX_VECS' undeclared (first use in this function)
     for (i = 0; i < I915_MAX_VECS; i++) {
                     ^
>> drivers/gpu/drm/i915/intel_device_info.c:632:3: error: implicit declaration of function '_VECS' [-Werror=implicit-function-declaration]
      if (!HAS_ENGINE(dev_priv, _VECS(i)))
      ^
   cc1: some warnings being treated as errors
--
   drivers/gpu/drm/i915/intel_uncore.c: In function 'intel_uncore_prune':
   drivers/gpu/drm/i915/intel_uncore.c:1468:19: error: 'I915_MAX_VCS' undeclared (first use in this function)
      for (i = 0; i < I915_MAX_VCS; i++) {
                      ^
   drivers/gpu/drm/i915/intel_uncore.c:1468:19: note: each undeclared identifier is reported only once for each function it appears in
>> drivers/gpu/drm/i915/intel_uncore.c:1469:16: error: 'FW_DOMAIN_ID_MEDIA_VDBOX0' undeclared (first use in this function)
       domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
                   ^
   drivers/gpu/drm/i915/intel_uncore.c:1478:19: error: 'I915_MAX_VECS' undeclared (first use in this function)
      for (i = 0; i < I915_MAX_VECS; i++) {
                      ^
>> drivers/gpu/drm/i915/intel_uncore.c:1479:16: error: 'FW_DOMAIN_ID_MEDIA_VEBOX0' undeclared (first use in this function)
       domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
                   ^
   drivers/gpu/drm/i915/intel_uncore.c:1481:4: error: implicit declaration of function '_VECS' [-Werror=implicit-function-declaration]
       if (HAS_ENGINE(dev_priv, _VECS(i)))
       ^
   cc1: some warnings being treated as errors

vim +/I915_MAX_VCS +619 drivers/gpu/drm/i915/intel_device_info.c

   595	
   596	/*
   597	 * Determine which engines are fused off in our particular hardware. Since the
   598	 * fuse register is in the blitter powerwell, we need forcewake to be ready at
   599	 * this point (but later we need to prune the forcewake domains for engines that
   600	 * are indeed fused off).
   601	 */
   602	void intel_device_info_init_mmio(struct drm_i915_private *dev_priv)
   603	{
   604		struct intel_device_info *info = mkwrite_device_info(dev_priv);
   605		u8 vdbox_disable, vebox_disable;
   606		u32 media_fuse;
   607		int i;
   608	
   609		if (INTEL_GEN(dev_priv) < 11)
   610			return;
   611	
   612		media_fuse = I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE);
   613	
   614		vdbox_disable = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
   615		vebox_disable = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
   616				GEN11_GT_VEBOX_DISABLE_SHIFT;
   617	
   618		DRM_DEBUG_DRIVER("vdbox disable: %04x\n", vdbox_disable);
 > 619		for (i = 0; i < I915_MAX_VCS; i++) {
   620			if (!HAS_ENGINE(dev_priv, _VCS(i)))
   621				continue;
   622	
   623			if (!(BIT(i) & vdbox_disable))
   624				continue;
   625	
   626			info->ring_mask &= ~ENGINE_MASK(_VCS(i));
   627			DRM_DEBUG_DRIVER("vcs%u fused off\n", i);
   628		}
   629	
   630		DRM_DEBUG_DRIVER("vebox disable: %04x\n", vebox_disable);
 > 631		for (i = 0; i < I915_MAX_VECS; i++) {
 > 632			if (!HAS_ENGINE(dev_priv, _VECS(i)))

---
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Re: [PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Sagar Arun Kamble]

On 2/23/2018 4:35 AM, Oscar Mateo wrote:
>
>
<snip>
>>> + * We might have detected that some engines are fused off after we 
>>> initialized
>>> + * the forcewake domains. Prune them, to make sure they only 
>>> reference existing
>>> + * engines.
>>> + */
>>> +void intel_uncore_prune(struct drm_i915_private *dev_priv)
>>> +{
>>> +    if (INTEL_GEN(dev_priv) >= 11) {
>>> +        enum forcewake_domains fw_domains = 
>>> dev_priv->uncore.fw_domains;
>>> +        enum forcewake_domain_id domain_id;
>>> +        int i;
>>> +
>>> +        for (i = 0; i < I915_MAX_VCS; i++) {
>>> +            domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
>>> +
>>> +            if (HAS_ENGINE(dev_priv, _VCS(i)))
>>> +                continue;
>>> +
>>> +            if (fw_domains & BIT(domain_id))
>> fw_domains check seems redundant as it is initialized based on 
>> HAS_ENGINE.
>> we can just have
>> if (!HAS_ENGINE(dev_priv, _VCS(i)))
>>     fw_domain_fini(dev_priv, domain_id);
>
> I don't want to call fw_domain_fini on something we never initialized 
> in the first place (e.g. VCS1/3 and VECS1/2/3 on an ICL-LP).
>
Right. Makes sense.
for loop iterating over engines based on ring_mask can help us rely on 
only HAS_ENGINE condition and then we can have complete pruning in 
single for loop.
what do you think?
>>> + fw_domain_fini(dev_priv, domain_id);
>>> +        }
>>> +
>>> +        for (i = 0; i < I915_MAX_VECS; i++) {
>>> +            domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
>>> +
>>> +            if (HAS_ENGINE(dev_priv, _VECS(i)))
>>> +                continue;
>>> +
>>> +            if (fw_domains & BIT(domain_id))
>>> +                fw_domain_fini(dev_priv, domain_id);
>>> +        }
>>> +    }
>>> +}
>>> +
>>>   void intel_uncore_fini(struct drm_i915_private *dev_priv)
>>>   {
>>>       /* Paranoia: make sure we have disabled everything before we 
>>> exit. */
>>> diff --git a/drivers/gpu/drm/i915/intel_uncore.h 
>>> b/drivers/gpu/drm/i915/intel_uncore.h
>>> index 53ef77d..28feabf 100644
>>> --- a/drivers/gpu/drm/i915/intel_uncore.h
>>> +++ b/drivers/gpu/drm/i915/intel_uncore.h
>>> @@ -129,6 +129,7 @@ struct intel_uncore {
>>>     void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
>>>   void intel_uncore_init(struct drm_i915_private *dev_priv);
>>> +void intel_uncore_prune(struct drm_i915_private *dev_priv);
>>>   bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
>>>   bool intel_uncore_arm_unclaimed_mmio_detection(struct 
>>> drm_i915_private *dev_priv);
>>>   void intel_uncore_fini(struct drm_i915_private *dev_priv);
>>
>

-- 
Thanks,
Sagar

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Re: [PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Oscar Mateo]

On 2/25/2018 9:22 PM, Sagar Arun Kamble wrote:
>
>
> On 2/23/2018 4:35 AM, Oscar Mateo wrote:
>>
>>
> <snip>
>>>> + * We might have detected that some engines are fused off after we 
>>>> initialized
>>>> + * the forcewake domains. Prune them, to make sure they only 
>>>> reference existing
>>>> + * engines.
>>>> + */
>>>> +void intel_uncore_prune(struct drm_i915_private *dev_priv)
>>>> +{
>>>> +    if (INTEL_GEN(dev_priv) >= 11) {
>>>> +        enum forcewake_domains fw_domains = 
>>>> dev_priv->uncore.fw_domains;
>>>> +        enum forcewake_domain_id domain_id;
>>>> +        int i;
>>>> +
>>>> +        for (i = 0; i < I915_MAX_VCS; i++) {
>>>> +            domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
>>>> +
>>>> +            if (HAS_ENGINE(dev_priv, _VCS(i)))
>>>> +                continue;
>>>> +
>>>> +            if (fw_domains & BIT(domain_id))
>>> fw_domains check seems redundant as it is initialized based on 
>>> HAS_ENGINE.
>>> we can just have
>>> if (!HAS_ENGINE(dev_priv, _VCS(i)))
>>>     fw_domain_fini(dev_priv, domain_id);
>>
>> I don't want to call fw_domain_fini on something we never initialized 
>> in the first place (e.g. VCS1/3 and VECS1/2/3 on an ICL-LP).
>>
> Right. Makes sense.
> for loop iterating over engines based on ring_mask can help us rely on 
> only HAS_ENGINE condition and then we can have complete pruning in 
> single for loop.
> what do you think?

Hmmm.. I'm not sure I follow: intel_device_info_init_mmio modifies 
ring_mask, so if I loop over engines based on ring_mask I am going to 
miss those I want to prune, right?

>>>> + fw_domain_fini(dev_priv, domain_id);
>>>> +        }
>>>> +
>>>> +        for (i = 0; i < I915_MAX_VECS; i++) {
>>>> +            domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
>>>> +
>>>> +            if (HAS_ENGINE(dev_priv, _VECS(i)))
>>>> +                continue;
>>>> +
>>>> +            if (fw_domains & BIT(domain_id))
>>>> +                fw_domain_fini(dev_priv, domain_id);
>>>> +        }
>>>> +    }
>>>> +}
>>>> +
>>>>   void intel_uncore_fini(struct drm_i915_private *dev_priv)
>>>>   {
>>>>       /* Paranoia: make sure we have disabled everything before we 
>>>> exit. */
>>>> diff --git a/drivers/gpu/drm/i915/intel_uncore.h 
>>>> b/drivers/gpu/drm/i915/intel_uncore.h
>>>> index 53ef77d..28feabf 100644
>>>> --- a/drivers/gpu/drm/i915/intel_uncore.h
>>>> +++ b/drivers/gpu/drm/i915/intel_uncore.h
>>>> @@ -129,6 +129,7 @@ struct intel_uncore {
>>>>     void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
>>>>   void intel_uncore_init(struct drm_i915_private *dev_priv);
>>>> +void intel_uncore_prune(struct drm_i915_private *dev_priv);
>>>>   bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
>>>>   bool intel_uncore_arm_unclaimed_mmio_detection(struct 
>>>> drm_i915_private *dev_priv);
>>>>   void intel_uncore_fini(struct drm_i915_private *dev_priv);
>>>
>>
>

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Re: [PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Sagar Arun Kamble]

On 2/27/2018 4:34 AM, Oscar Mateo wrote:
>
>
> On 2/25/2018 9:22 PM, Sagar Arun Kamble wrote:
>>
>>
>> On 2/23/2018 4:35 AM, Oscar Mateo wrote:
>>>
>>>
>> <snip>
>>>>> + * We might have detected that some engines are fused off after 
>>>>> we initialized
>>>>> + * the forcewake domains. Prune them, to make sure they only 
>>>>> reference existing
>>>>> + * engines.
>>>>> + */
>>>>> +void intel_uncore_prune(struct drm_i915_private *dev_priv)
>>>>> +{
>>>>> +    if (INTEL_GEN(dev_priv) >= 11) {
>>>>> +        enum forcewake_domains fw_domains = 
>>>>> dev_priv->uncore.fw_domains;
>>>>> +        enum forcewake_domain_id domain_id;
>>>>> +        int i;
>>>>> +
>>>>> +        for (i = 0; i < I915_MAX_VCS; i++) {
>>>>> +            domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
>>>>> +
>>>>> +            if (HAS_ENGINE(dev_priv, _VCS(i)))
>>>>> +                continue;
>>>>> +
>>>>> +            if (fw_domains & BIT(domain_id))
>>>> fw_domains check seems redundant as it is initialized based on 
>>>> HAS_ENGINE.
>>>> we can just have
>>>> if (!HAS_ENGINE(dev_priv, _VCS(i)))
>>>>     fw_domain_fini(dev_priv, domain_id);
>>>
>>> I don't want to call fw_domain_fini on something we never 
>>> initialized in the first place (e.g. VCS1/3 and VECS1/2/3 on an 
>>> ICL-LP).
>>>
>> Right. Makes sense.
>> for loop iterating over engines based on ring_mask can help us rely 
>> on only HAS_ENGINE condition and then we can have complete pruning in 
>> single for loop.
>> what do you think?
>
> Hmmm.. I'm not sure I follow: intel_device_info_init_mmio modifies 
> ring_mask, so if I loop over engines based on ring_mask I am going to 
> miss those I want to prune, right?
>
Oops ... you are right ...
My suggestion about skipping fw_domains check will not work currently. 
In future may be if we create default ring_mask and runtime ring_mask it 
can be reworked.

Other suggestion to use single for loop (for_each_engine()) can be done 
I think.
It will make it generic for all engine types.  Below is what I am 
thinking of as part of intel_uncore_prune:

for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
     if (HAS_ENGINE(dev_priv, i))
         continue;
     if (fw_domains & BIT(i))
         fw_domain_fini(dev_priv, i);
}
>>>>> + fw_domain_fini(dev_priv, domain_id);
>>>>> +        }
>>>>> +
>>>>> +        for (i = 0; i < I915_MAX_VECS; i++) {
>>>>> +            domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
>>>>> +
>>>>> +            if (HAS_ENGINE(dev_priv, _VECS(i)))
>>>>> +                continue;
>>>>> +
>>>>> +            if (fw_domains & BIT(domain_id))
>>>>> +                fw_domain_fini(dev_priv, domain_id);
>>>>> +        }
>>>>> +    }
>>>>> +}
>>>>> +
>>>>>   void intel_uncore_fini(struct drm_i915_private *dev_priv)
>>>>>   {
>>>>>       /* Paranoia: make sure we have disabled everything before we 
>>>>> exit. */
>>>>> diff --git a/drivers/gpu/drm/i915/intel_uncore.h 
>>>>> b/drivers/gpu/drm/i915/intel_uncore.h
>>>>> index 53ef77d..28feabf 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_uncore.h
>>>>> +++ b/drivers/gpu/drm/i915/intel_uncore.h
>>>>> @@ -129,6 +129,7 @@ struct intel_uncore {
>>>>>     void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
>>>>>   void intel_uncore_init(struct drm_i915_private *dev_priv);
>>>>> +void intel_uncore_prune(struct drm_i915_private *dev_priv);
>>>>>   bool intel_uncore_unclaimed_mmio(struct drm_i915_private 
>>>>> *dev_priv);
>>>>>   bool intel_uncore_arm_unclaimed_mmio_detection(struct 
>>>>> drm_i915_private *dev_priv);
>>>>>   void intel_uncore_fini(struct drm_i915_private *dev_priv);
>>>>
>>>
>>
>

-- 
Thanks,
Sagar

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Re: [PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Oscar Mateo]

On 2/26/2018 9:49 PM, Sagar Arun Kamble wrote:
>
>
> On 2/27/2018 4:34 AM, Oscar Mateo wrote:
>>
>>
>> On 2/25/2018 9:22 PM, Sagar Arun Kamble wrote:
>>>
>>>
>>> On 2/23/2018 4:35 AM, Oscar Mateo wrote:
>>>>
>>>>
>>> <snip>
>>>>>> + * We might have detected that some engines are fused off after 
>>>>>> we initialized
>>>>>> + * the forcewake domains. Prune them, to make sure they only 
>>>>>> reference existing
>>>>>> + * engines.
>>>>>> + */
>>>>>> +void intel_uncore_prune(struct drm_i915_private *dev_priv)
>>>>>> +{
>>>>>> +    if (INTEL_GEN(dev_priv) >= 11) {
>>>>>> +        enum forcewake_domains fw_domains = 
>>>>>> dev_priv->uncore.fw_domains;
>>>>>> +        enum forcewake_domain_id domain_id;
>>>>>> +        int i;
>>>>>> +
>>>>>> +        for (i = 0; i < I915_MAX_VCS; i++) {
>>>>>> +            domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
>>>>>> +
>>>>>> +            if (HAS_ENGINE(dev_priv, _VCS(i)))
>>>>>> +                continue;
>>>>>> +
>>>>>> +            if (fw_domains & BIT(domain_id))
>>>>> fw_domains check seems redundant as it is initialized based on 
>>>>> HAS_ENGINE.
>>>>> we can just have
>>>>> if (!HAS_ENGINE(dev_priv, _VCS(i)))
>>>>>     fw_domain_fini(dev_priv, domain_id);
>>>>
>>>> I don't want to call fw_domain_fini on something we never 
>>>> initialized in the first place (e.g. VCS1/3 and VECS1/2/3 on an 
>>>> ICL-LP).
>>>>
>>> Right. Makes sense.
>>> for loop iterating over engines based on ring_mask can help us rely 
>>> on only HAS_ENGINE condition and then we can have complete pruning 
>>> in single for loop.
>>> what do you think?
>>
>> Hmmm.. I'm not sure I follow: intel_device_info_init_mmio modifies 
>> ring_mask, so if I loop over engines based on ring_mask I am going to 
>> miss those I want to prune, right?
>>
> Oops ... you are right ...
> My suggestion about skipping fw_domains check will not work currently. 
> In future may be if we create default ring_mask and runtime ring_mask 
> it can be reworked.
>
> Other suggestion to use single for loop (for_each_engine()) can be 
> done I think.
> It will make it generic for all engine types.  Below is what I am 
> thinking of as part of intel_uncore_prune:
>
> for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
>     if (HAS_ENGINE(dev_priv, i))
>         continue;
>     if (fw_domains & BIT(i))
>         fw_domain_fini(dev_priv, i);
> }

This won't work either, because the index for engines and forcewake 
domains is different. If you think it is important to make the prune 
function more generic, I can translate between the two (but it will be 
for naught if, as you mentioned, we are working to create separate 
default ring_mask and runtime ring_mask in the future).

>>>>>> + fw_domain_fini(dev_priv, domain_id);
>>>>>> +        }
>>>>>> +
>>>>>> +        for (i = 0; i < I915_MAX_VECS; i++) {
>>>>>> +            domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
>>>>>> +
>>>>>> +            if (HAS_ENGINE(dev_priv, _VECS(i)))
>>>>>> +                continue;
>>>>>> +
>>>>>> +            if (fw_domains & BIT(domain_id))
>>>>>> +                fw_domain_fini(dev_priv, domain_id);
>>>>>> +        }
>>>>>> +    }
>>>>>> +}
>>>>>> +
>>>>>>   void intel_uncore_fini(struct drm_i915_private *dev_priv)
>>>>>>   {
>>>>>>       /* Paranoia: make sure we have disabled everything before 
>>>>>> we exit. */
>>>>>> diff --git a/drivers/gpu/drm/i915/intel_uncore.h 
>>>>>> b/drivers/gpu/drm/i915/intel_uncore.h
>>>>>> index 53ef77d..28feabf 100644
>>>>>> --- a/drivers/gpu/drm/i915/intel_uncore.h
>>>>>> +++ b/drivers/gpu/drm/i915/intel_uncore.h
>>>>>> @@ -129,6 +129,7 @@ struct intel_uncore {
>>>>>>     void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
>>>>>>   void intel_uncore_init(struct drm_i915_private *dev_priv);
>>>>>> +void intel_uncore_prune(struct drm_i915_private *dev_priv);
>>>>>>   bool intel_uncore_unclaimed_mmio(struct drm_i915_private 
>>>>>> *dev_priv);
>>>>>>   bool intel_uncore_arm_unclaimed_mmio_detection(struct 
>>>>>> drm_i915_private *dev_priv);
>>>>>>   void intel_uncore_fini(struct drm_i915_private *dev_priv);
>>>>>
>>>>
>>>
>>
>

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Re: [PATCH v9] drm/i915/icl: Check for fused-off VDBOX and VEBOX instances

[Sagar Arun Kamble]

On 2/28/2018 11:29 PM, Oscar Mateo wrote:
>
>
> On 2/26/2018 9:49 PM, Sagar Arun Kamble wrote:
>>
>>
>> On 2/27/2018 4:34 AM, Oscar Mateo wrote:
>>>
>>>
>>> On 2/25/2018 9:22 PM, Sagar Arun Kamble wrote:
>>>>
>>>>
>>>> On 2/23/2018 4:35 AM, Oscar Mateo wrote:
>>>>>
>>>>>
>>>> <snip>
>>>>>>> + * We might have detected that some engines are fused off after 
>>>>>>> we initialized
>>>>>>> + * the forcewake domains. Prune them, to make sure they only 
>>>>>>> reference existing
>>>>>>> + * engines.
>>>>>>> + */
>>>>>>> +void intel_uncore_prune(struct drm_i915_private *dev_priv)
>>>>>>> +{
>>>>>>> +    if (INTEL_GEN(dev_priv) >= 11) {
>>>>>>> +        enum forcewake_domains fw_domains = 
>>>>>>> dev_priv->uncore.fw_domains;
>>>>>>> +        enum forcewake_domain_id domain_id;
>>>>>>> +        int i;
>>>>>>> +
>>>>>>> +        for (i = 0; i < I915_MAX_VCS; i++) {
>>>>>>> +            domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i;
>>>>>>> +
>>>>>>> +            if (HAS_ENGINE(dev_priv, _VCS(i)))
>>>>>>> +                continue;
>>>>>>> +
>>>>>>> +            if (fw_domains & BIT(domain_id))
>>>>>> fw_domains check seems redundant as it is initialized based on 
>>>>>> HAS_ENGINE.
>>>>>> we can just have
>>>>>> if (!HAS_ENGINE(dev_priv, _VCS(i)))
>>>>>>     fw_domain_fini(dev_priv, domain_id);
>>>>>
>>>>> I don't want to call fw_domain_fini on something we never 
>>>>> initialized in the first place (e.g. VCS1/3 and VECS1/2/3 on an 
>>>>> ICL-LP).
>>>>>
>>>> Right. Makes sense.
>>>> for loop iterating over engines based on ring_mask can help us rely 
>>>> on only HAS_ENGINE condition and then we can have complete pruning 
>>>> in single for loop.
>>>> what do you think?
>>>
>>> Hmmm.. I'm not sure I follow: intel_device_info_init_mmio modifies 
>>> ring_mask, so if I loop over engines based on ring_mask I am going 
>>> to miss those I want to prune, right?
>>>
>> Oops ... you are right ...
>> My suggestion about skipping fw_domains check will not work 
>> currently. In future may be if we create default ring_mask and 
>> runtime ring_mask it can be reworked.
>>
>> Other suggestion to use single for loop (for_each_engine()) can be 
>> done I think.
>> It will make it generic for all engine types.  Below is what I am 
>> thinking of as part of intel_uncore_prune:
>>
>> for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
>>     if (HAS_ENGINE(dev_priv, i))
>>         continue;
>>     if (fw_domains & BIT(i))
>>         fw_domain_fini(dev_priv, i);
>> }
>
> This won't work either, because the index for engines and forcewake 
> domains is different. If you think it is important to make the prune 
> function more generic, I can translate between the two (but it will be 
> for naught if, as you mentioned, we are working to create separate 
> default ring_mask and runtime ring_mask in the future).
>
Yes. Translation will help (I thought of FW_D_ID_MEDIA to be reused for 
FW_D_ID_MEDIA_VDB0).
I think this patch can go in current shape and will pursue other changes 
as follow up based on inputs.

I feel making it generic will allow pruning to scale across engine types 
(if that is needed in future).
I am not sure if we want to pursue the default/runtime ring_mask change 
(another use case of this that i think is if user wants to know default 
config vs fused)
Tvrtko, Chris - what do you think?
>>>>>>> + fw_domain_fini(dev_priv, domain_id);
>>>>>>> +        }
>>>>>>> +
>>>>>>> +        for (i = 0; i < I915_MAX_VECS; i++) {
>>>>>>> +            domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i;
>>>>>>> +
>>>>>>> +            if (HAS_ENGINE(dev_priv, _VECS(i)))
>>>>>>> +                continue;
>>>>>>> +
>>>>>>> +            if (fw_domains & BIT(domain_id))
>>>>>>> +                fw_domain_fini(dev_priv, domain_id);
>>>>>>> +        }
>>>>>>> +    }
>>>>>>> +}
>>>>>>> +
>>>>>>>   void intel_uncore_fini(struct drm_i915_private *dev_priv)
>>>>>>>   {
>>>>>>>       /* Paranoia: make sure we have disabled everything before 
>>>>>>> we exit. */
>>>>>>> diff --git a/drivers/gpu/drm/i915/intel_uncore.h 
>>>>>>> b/drivers/gpu/drm/i915/intel_uncore.h
>>>>>>> index 53ef77d..28feabf 100644
>>>>>>> --- a/drivers/gpu/drm/i915/intel_uncore.h
>>>>>>> +++ b/drivers/gpu/drm/i915/intel_uncore.h
>>>>>>> @@ -129,6 +129,7 @@ struct intel_uncore {
>>>>>>>     void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
>>>>>>>   void intel_uncore_init(struct drm_i915_private *dev_priv);
>>>>>>> +void intel_uncore_prune(struct drm_i915_private *dev_priv);
>>>>>>>   bool intel_uncore_unclaimed_mmio(struct drm_i915_private 
>>>>>>> *dev_priv);
>>>>>>>   bool intel_uncore_arm_unclaimed_mmio_detection(struct 
>>>>>>> drm_i915_private *dev_priv);
>>>>>>>   void intel_uncore_fini(struct drm_i915_private *dev_priv);
>>>>>>
>>>>>
>>>>
>>>
>>
>

-- 
Thanks,
Sagar

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