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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: dri-devel@lists.freedesktop.org
Cc: mesa-dev@lists.freedesktop.org,
	James Ausmus <james.ausmus@intel.com>,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	Paulo Zanoni <paulo.r.zanoni@intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [PATCH libdrm] intel/intel_chipset.h: Sync Cannonlake IDs.
Date: Wed, 14 Feb 2018 17:42:24 -0800	[thread overview]
Message-ID: <20180215014224.13407-1-rodrigo.vivi@intel.com> (raw)

Let's sync CNL ids with Spec and kernel.

Sync with kernel commit '3f43031b1693 ("drm/i915/cnl:
Add Cannonlake PCI IDs for another SKU.")' and
commit 'e3890d05b342 ("drm/i915/cnl: Sync PCI ID with Spec.")'

Cc: James Ausmus <james.ausmus@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 intel/intel_chipset.h | 52 +++++++++++++++++++++++++++------------------------
 1 file changed, 28 insertions(+), 24 deletions(-)

diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 3818e71e..01d250e8 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -241,16 +241,20 @@
 #define PCI_CHIP_COFFEELAKE_U_GT3_4     0x3EA7
 #define PCI_CHIP_COFFEELAKE_U_GT3_5     0x3EA8
 
-#define PCI_CHIP_CANNONLAKE_U_GT2_0	0x5A52
-#define PCI_CHIP_CANNONLAKE_U_GT2_1	0x5A5A
-#define PCI_CHIP_CANNONLAKE_U_GT2_2	0x5A42
-#define PCI_CHIP_CANNONLAKE_U_GT2_3	0x5A4A
-#define PCI_CHIP_CANNONLAKE_Y_GT2_0	0x5A51
-#define PCI_CHIP_CANNONLAKE_Y_GT2_1	0x5A59
-#define PCI_CHIP_CANNONLAKE_Y_GT2_2	0x5A41
-#define PCI_CHIP_CANNONLAKE_Y_GT2_3	0x5A49
-#define PCI_CHIP_CANNONLAKE_Y_GT2_4	0x5A71
-#define PCI_CHIP_CANNONLAKE_Y_GT2_5	0x5A79
+#define PCI_CHIP_CANNONLAKE_0		0x5A51
+#define PCI_CHIP_CANNONLAKE_1		0x5A59
+#define PCI_CHIP_CANNONLAKE_2		0x5A41
+#define PCI_CHIP_CANNONLAKE_3		0x5A49
+#define PCI_CHIP_CANNONLAKE_4		0x5A52
+#define PCI_CHIP_CANNONLAKE_5		0x5A5A
+#define PCI_CHIP_CANNONLAKE_6		0x5A42
+#define PCI_CHIP_CANNONLAKE_7		0x5A4A
+#define PCI_CHIP_CANNONLAKE_8		0x5A50
+#define PCI_CHIP_CANNONLAKE_9		0x5A40
+#define PCI_CHIP_CANNONLAKE_10		0x5A54
+#define PCI_CHIP_CANNONLAKE_11		0x5A5C
+#define PCI_CHIP_CANNONLAKE_12		0x5A44
+#define PCI_CHIP_CANNONLAKE_13		0x5A4C
 
 #define IS_MOBILE(devid)	((devid) == PCI_CHIP_I855_GM || \
 				 (devid) == PCI_CHIP_I915_GM || \
@@ -515,20 +519,20 @@
 				 IS_GEMINILAKE(devid) || \
 				 IS_COFFEELAKE(devid))
 
-#define IS_CNL_Y(devid)		((devid) == PCI_CHIP_CANNONLAKE_Y_GT2_0 || \
-				 (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_1 || \
-				 (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_2 || \
-				 (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_3 || \
-				 (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_4 || \
-				 (devid) == PCI_CHIP_CANNONLAKE_Y_GT2_5)
-
-#define IS_CNL_U(devid)		((devid) == PCI_CHIP_CANNONLAKE_U_GT2_0 || \
-				 (devid) == PCI_CHIP_CANNONLAKE_U_GT2_1 || \
-				 (devid) == PCI_CHIP_CANNONLAKE_U_GT2_2 || \
-				 (devid) == PCI_CHIP_CANNONLAKE_U_GT2_3)
-
-#define IS_CANNONLAKE(devid)	(IS_CNL_U(devid) || \
-				 IS_CNL_Y(devid))
+#define IS_CANNONLAKE(devid)	((devid) == PCI_CHIP_CANNONLAKE_0 || \
+				 (devid) == PCI_CHIP_CANNONLAKE_1 || \
+				 (devid) == PCI_CHIP_CANNONLAKE_2 || \
+				 (devid) == PCI_CHIP_CANNONLAKE_3 || \
+				 (devid) == PCI_CHIP_CANNONLAKE_4 || \
+				 (devid) == PCI_CHIP_CANNONLAKE_5 || \
+				 (devid) == PCI_CHIP_CANNONLAKE_6 || \
+				 (devid) == PCI_CHIP_CANNONLAKE_7 || \
+				 (devid) == PCI_CHIP_CANNONLAKE_8 || \
+				 (devid) == PCI_CHIP_CANNONLAKE_9 || \
+				 (devid) == PCI_CHIP_CANNONLAKE_10 || \
+				 (devid) == PCI_CHIP_CANNONLAKE_11 || \
+				 (devid) == PCI_CHIP_CANNONLAKE_12 || \
+				 (devid) == PCI_CHIP_CANNONLAKE_13)
 
 #define IS_GEN10(devid)		(IS_CANNONLAKE(devid))
 
-- 
2.13.6

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             reply	other threads:[~2018-02-15  1:42 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-15  1:42 Rodrigo Vivi [this message]
2018-03-05 22:51 ` [PATCH libdrm] intel/intel_chipset.h: Sync Cannonlake IDs Rafael Antognolli
2018-03-05 23:14   ` Rodrigo Vivi

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