From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/3] drm/i915/cnl: Fix PORT_TX_DW5/7 register address
Date: Thu, 15 Feb 2018 15:43:46 -0800 [thread overview]
Message-ID: <20180215234346.GB3621@intel.com> (raw)
In-Reply-To: <874lmi4agp.fsf@intel.com>
On Thu, Feb 15, 2018 at 04:02:46PM +0200, Jani Nikula wrote:
> On Thu, 15 Feb 2018, Mahesh Kumar <mahesh1.kumar@intel.com> wrote:
> > Register Address for CNL_PORT_DW5_LN0_D is 0x162E54, but current code is
> > defining it as 0x162ED4. Similarly for CNL_PORT_DW7_LN0_D register address
> > is defined 0x162EDC instead of 0x162E5C, fix it.
>
> Which commit introduced the bug? Please add Fixes: annotation for it. We
> want this backported.
>
> BR,
> Jani.
>
>
> >
Fixes: 04416108ccea ("drm/i915/cnl: Add registers related to voltage swing sequences.")
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index f6afa5e5e7c1..1412abcb27d4 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -2034,7 +2034,7 @@ enum i915_power_well_id {
> > #define _CNL_PORT_TX_DW5_LN0_AE 0x162454
> > #define _CNL_PORT_TX_DW5_LN0_B 0x162654
> > #define _CNL_PORT_TX_DW5_LN0_C 0x162C54
> > -#define _CNL_PORT_TX_DW5_LN0_D 0x162ED4
> > +#define _CNL_PORT_TX_DW5_LN0_D 0x162E54
> > #define _CNL_PORT_TX_DW5_LN0_F 0x162854
> > #define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \
> > _CNL_PORT_TX_DW5_GRP_AE, \
> > @@ -2065,7 +2065,7 @@ enum i915_power_well_id {
> > #define _CNL_PORT_TX_DW7_LN0_AE 0x16245C
> > #define _CNL_PORT_TX_DW7_LN0_B 0x16265C
> > #define _CNL_PORT_TX_DW7_LN0_C 0x162C5C
> > -#define _CNL_PORT_TX_DW7_LN0_D 0x162EDC
> > +#define _CNL_PORT_TX_DW7_LN0_D 0x162E5C
> > #define _CNL_PORT_TX_DW7_LN0_F 0x16285C
> > #define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \
> > _CNL_PORT_TX_DW7_GRP_AE, \
>
> --
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2018-02-15 23:43 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-15 9:56 [PATCH 0/3] CNL port refactoring Mahesh Kumar
2018-02-15 9:56 ` [PATCH 1/3] drm/i915/cnl: Fix PORT_TX_DW5/7 register address Mahesh Kumar
2018-02-15 14:02 ` Jani Nikula
2018-02-15 23:43 ` Rodrigo Vivi [this message]
2018-02-16 17:57 ` Rodrigo Vivi
2018-02-15 9:56 ` [PATCH 2/3] drm/i915/cnl; Add macro to get PORT_TX register Mahesh Kumar
2018-02-15 9:56 ` [PATCH 3/3] drm/i915/cnl: Replace PORT_TX register macros with new ones Mahesh Kumar
2018-02-15 10:01 ` ✗ Fi.CI.CHECKPATCH: warning for CNL port refactoring Patchwork
2018-02-15 10:16 ` ✓ Fi.CI.BAT: success " Patchwork
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