From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752502AbeB1K3T (ORCPT ); Wed, 28 Feb 2018 05:29:19 -0500 Received: from mail.skyhub.de ([5.9.137.197]:37140 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752469AbeB1K3R (ORCPT ); Wed, 28 Feb 2018 05:29:17 -0500 From: Borislav Petkov To: X86 ML Cc: Arjan Van De Ven , Ashok Raj , Tom Lendacky , LKML Subject: [PATCH 3/7] x86/microcode/intel: Writeback and invalidate caches before updating microcode Date: Wed, 28 Feb 2018 11:28:42 +0100 Message-Id: <20180228102846.13447-4-bp@alien8.de> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20180228102846.13447-1-bp@alien8.de> References: <20180228102846.13447-1-bp@alien8.de> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ashok Raj Updating microcode is less error prone when caches have been flushed and depending on what exactly the microcode is updating. For example, some of the issues around certain Broadwell parts can be addressed by doing a full cache flush. Signed-off-by: Ashok Raj Cc: X86 ML Cc: Tony Luck Cc: Andi Kleen Cc: Tom Lendacky Cc: Arjan Van De Ven Link: http://lkml.kernel.org/r/1519352533-15992-3-git-send-email-ashok.raj@intel.com [ Massage it and use native_wbinvd() in both cases. ] Signed-off-by: Borislav Petkov --- arch/x86/kernel/cpu/microcode/intel.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 87bd6dc94081..e2864bc2d575 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -600,6 +600,12 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) return UCODE_OK; } + /* + * Writeback and invalidate caches before updating microcode to avoid + * internal issues depending on what the microcode is updating. + */ + native_wbinvd(); + /* write microcode via MSR 0x79 */ native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); @@ -816,6 +822,12 @@ static enum ucode_state apply_microcode_intel(int cpu) return UCODE_OK; } + /* + * Writeback and invalidate caches before updating microcode to avoid + * internal issues depending on what the microcode is updating. + */ + native_wbinvd(); + /* write microcode via MSR 0x79 */ wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); -- 2.13.0