From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: multipart/mixed; boundary="===============7713621587231423268==" MIME-Version: 1.0 From: =?utf-8?q?G=C3=B6k=C3=A7e_Aydos_=3Cgoekce_at_aydos=2Ede=3E?= Subject: [OPAE] OPAE on Intel FPGA SoC devices Date: Wed, 28 Feb 2018 10:41:06 +0100 Message-ID: <20180228104106.Horde.05TN3J7acKFPncAbLVmcLfD@srvh07.vc-server.de> List-ID: To: opae@lists.01.org --===============7713621587231423268== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Can OPAE also be utilized on devices where the processor and the FPGA = are interconnected via AXI bus, e.g., Cyclone5 SoC G=C3=B6k=C3=A7e --===============7713621587231423268==--