[PATCH v4 0/6] MIPS: add support for Microsemi MIPS SoCs

[PATCH v4 0/6] MIPS: add support for Microsemi MIPS SoCs

[Alexandre Belloni]

Hi,

This patch series adds initial support for the Microsemi MIPS SoCs. It
is currently focusing on the Microsemi Ocelot (VSC7513, VSC7514).

Changes in v4:
 - dropped the reset driver as it has already been taken
 - Updated the MAINTAINERS entry (new files, changed email address)
 - moved to the MIPS generic infrastructure
 - corrected the cpu compatible in ocelot.dtsi

Alexandre Belloni (6):
  dt-bindings: Add vendor prefix for Microsemi Corporation
  dt-bindings: mips: Add bindings for Microsemi SoCs
  MIPS: mscc: add ocelot dtsi
  MIPS: mscc: add ocelot PCB123 device tree
  MIPS: generic: Add support for Microsemi Ocelot
  MAINTAINERS: Add entry for Microsemi MIPS SoCs

 Documentation/devicetree/bindings/mips/mscc.txt    |  44 +++++++++
 .../devicetree/bindings/vendor-prefixes.txt        |   1 +
 MAINTAINERS                                        |   9 ++
 arch/mips/Makefile                                 |   4 +
 arch/mips/boot/dts/Makefile                        |   1 +
 arch/mips/boot/dts/mscc/Makefile                   |   3 +
 arch/mips/boot/dts/mscc/ocelot.dtsi                | 110 +++++++++++++++++++++
 arch/mips/boot/dts/mscc/ocelot_pcb123.dts          |  27 +++++
 arch/mips/configs/generic/board-ocelot.config      |  40 ++++++++
 arch/mips/generic/Kconfig                          |  17 ++++
 arch/mips/generic/Makefile                         |   1 +
 arch/mips/generic/board-ocelot.c                   |  83 ++++++++++++++++
 12 files changed, 340 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt
 create mode 100644 arch/mips/boot/dts/mscc/Makefile
 create mode 100644 arch/mips/boot/dts/mscc/ocelot.dtsi
 create mode 100644 arch/mips/boot/dts/mscc/ocelot_pcb123.dts
 create mode 100644 arch/mips/configs/generic/board-ocelot.config
 create mode 100644 arch/mips/generic/board-ocelot.c

-- 
2.16.2

[PATCH v4 1/6] dt-bindings: Add vendor prefix for Microsemi Corporation

[Alexandre Belloni]

Microsemi Corporation provides semiconductor and system solutions for
aerospace & defense, communications, data center and industrial markets.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index ae850d6c0ad3..ffc959ef53e9 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -224,6 +224,7 @@ motorola	Motorola, Inc.
 moxa	Moxa Inc.
 mpl	MPL AG
 mqmaker	mqmaker Inc.
+mscc	Microsemi Corporation
 msi	Micro-Star International Co. Ltd.
 mti	Imagination Technologies Ltd. (formerly MIPS Technologies Inc.)
 multi-inno	Multi-Inno Technology Co.,Ltd
-- 
2.16.2

[PATCH v4 2/6] dt-bindings: mips: Add bindings for Microsemi SoCs

[Alexandre Belloni]

Add bindings for Microsemi SoCs. Currently only Ocelot is supported.

Reviewed-by: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
 Documentation/devicetree/bindings/mips/mscc.txt | 44 +++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mips/mscc.txt

diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
new file mode 100644
index 000000000000..f4514c274510
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/mscc.txt
@@ -0,0 +1,44 @@
+* Microsemi MIPS CPUs
+
+Boards with a SoC of the Microsemi MIPS family shall have the following
+properties:
+
+Required properties:
+- compatible: "mscc,ocelot"
+- mips-hpt-frequency: CPU counter frequency.
+
+
+* Other peripherals:
+
+o CPU chip regs:
+
+The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
+functionalities: chip ID, general purpose register for software use, reset
+controller, hardware status and configuration, efuses.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
+- reg : Should contain registers location and length
+
+Example:
+	syscon@71070000 {
+		compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
+		reg = <0x71070000 0x1c>;
+	};
+
+
+o CPU system control:
+
+The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
+the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
+endianness, CPU bus control, CPU status.
+
+Required properties:
+- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
+- reg : Should contain registers location and length
+
+Example:
+	syscon@70000000 {
+		compatible = "mscc,ocelot-cpu-syscon", "syscon";
+		reg = <0x70000000 0x2c>;
+	};
-- 
2.16.2

[PATCH v4 3/6] MIPS: mscc: add ocelot dtsi

[Alexandre Belloni]

Add a device tree include file for the Microsemi Ocelot SoC.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
 arch/mips/boot/dts/Makefile         |   1 +
 arch/mips/boot/dts/mscc/Makefile    |   1 +
 arch/mips/boot/dts/mscc/ocelot.dtsi | 110 ++++++++++++++++++++++++++++++++++++
 3 files changed, 112 insertions(+)
 create mode 100644 arch/mips/boot/dts/mscc/Makefile
 create mode 100644 arch/mips/boot/dts/mscc/ocelot.dtsi

diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index e2c6f131c8eb..1e79cab8e269 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -4,6 +4,7 @@ subdir-y	+= cavium-octeon
 subdir-y	+= img
 subdir-y	+= ingenic
 subdir-y	+= lantiq
+subdir-y	+= mscc
 subdir-y	+= mti
 subdir-y	+= netlogic
 subdir-y	+= ni
diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
new file mode 100644
index 000000000000..dd08e63a10ba
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/Makefile
@@ -0,0 +1 @@
+obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
new file mode 100644
index 000000000000..59351da6c561
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/* Copyright (c) 2017 Microsemi Corporation */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "mscc,ocelot";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mips-hpt-frequency = <250000000>;
+
+		cpu@0 {
+			compatible = "mips,mips24KEc";
+			device_type = "cpu";
+			reg = <0>;
+		};
+	};
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	cpuintc: interrupt-controller@0 {
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		compatible = "mti,cpu-interrupt-controller";
+	};
+
+	ahb_clk: ahb-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <250000000>;
+	};
+
+	ahb {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x70000000 0x2000000>;
+
+		interrupt-parent = <&intc>;
+
+		cpu_ctrl: syscon@0 {
+			compatible = "mscc,ocelot-cpu-syscon", "syscon";
+			reg = <0x0 0x2c>;
+		};
+
+		intc: interrupt-controller@70 {
+			compatible = "mscc,ocelot-icpu-intr";
+			reg = <0x70 0x70>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			interrupt-parent = <&cpuintc>;
+			interrupts = <2>;
+		};
+
+		uart0: serial@100000 {
+			pinctrl-0 = <&uart_pins>;
+			pinctrl-names = "default";
+			compatible = "ns16550a";
+			reg = <0x100000 0x20>;
+			interrupts = <6>;
+			clocks = <&ahb_clk>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+
+			status = "disabled";
+		};
+
+		uart2: serial@100800 {
+			pinctrl-0 = <&uart2_pins>;
+			pinctrl-names = "default";
+			compatible = "ns16550a";
+			reg = <0x100800 0x20>;
+			interrupts = <7>;
+			clocks = <&ahb_clk>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+
+			status = "disabled";
+		};
+
+		reset@1070008 {
+			compatible = "mscc,ocelot-chip-reset";
+			reg = <0x1070008 0x4>;
+		};
+
+		gpio: pinctrl@1070034 {
+			compatible = "mscc,ocelot-pinctrl";
+			reg = <0x1070034 0x68>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&gpio 0 0 22>;
+
+			uart_pins: uart-pins {
+				pins = "GPIO_6", "GPIO_7";
+				function = "uart";
+			};
+
+			uart2_pins: uart2-pins {
+				pins = "GPIO_12", "GPIO_13";
+				function = "uart2";
+			};
+		};
+	};
+};
-- 
2.16.2

[PATCH v4 4/6] MIPS: mscc: add ocelot PCB123 device tree

[Alexandre Belloni]

Add a device tree for the Microsemi Ocelot PCB123 evaluation board.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
 arch/mips/boot/dts/mscc/Makefile          |  2 ++
 arch/mips/boot/dts/mscc/ocelot_pcb123.dts | 27 +++++++++++++++++++++++++++
 2 files changed, 29 insertions(+)
 create mode 100644 arch/mips/boot/dts/mscc/ocelot_pcb123.dts

diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
index dd08e63a10ba..c51164537c02 100644
--- a/arch/mips/boot/dts/mscc/Makefile
+++ b/arch/mips/boot/dts/mscc/Makefile
@@ -1 +1,3 @@
+dtb-$(CONFIG_LEGACY_BOARD_OCELOT)	+= ocelot_pcb123.dtb
+
 obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
new file mode 100644
index 000000000000..42bd404471f6
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/* Copyright (c) 2017 Microsemi Corporation */
+
+/dts-v1/;
+
+#include "ocelot.dtsi"
+
+/ {
+	compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x0 0x0e000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
-- 
2.16.2

[PATCH v4 5/6] MIPS: generic: Add support for Microsemi Ocelot

[Alexandre Belloni]

Introduce support for the MIPS based Microsemi Ocelot SoCs.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
 arch/mips/Makefile                            |  4 ++
 arch/mips/configs/generic/board-ocelot.config | 40 +++++++++++++
 arch/mips/generic/Kconfig                     | 17 ++++++
 arch/mips/generic/Makefile                    |  1 +
 arch/mips/generic/board-ocelot.c              | 83 +++++++++++++++++++++++++++
 5 files changed, 145 insertions(+)
 create mode 100644 arch/mips/configs/generic/board-ocelot.config
 create mode 100644 arch/mips/generic/board-ocelot.c

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index d1ca839c3981..d2882244cf1f 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -543,6 +543,10 @@ generic_defconfig:
 # now that the boards have been converted to use the generic kernel they are
 # wrappers around the generic rules above.
 #
+.PHONY: ocelot_defconfig
+ocelot_defconfig:
+	$(Q)$(MAKE) -f $(srctree)/Makefile 32r2el_defconfig BOARDS=ocelot
+
 .PHONY: sead3_defconfig
 sead3_defconfig:
 	$(Q)$(MAKE) -f $(srctree)/Makefile 32r2el_defconfig BOARDS=sead-3
diff --git a/arch/mips/configs/generic/board-ocelot.config b/arch/mips/configs/generic/board-ocelot.config
new file mode 100644
index 000000000000..7f9e1eaccc34
--- /dev/null
+++ b/arch/mips/configs/generic/board-ocelot.config
@@ -0,0 +1,40 @@
+# require CONFIG_32BIT=y
+
+CONFIG_LEGACY_BOARD_OCELOT=y
+
+CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
+
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+
+CONFIG_GPIO_SYSFS=y
+
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_DESIGNWARE=y
+CONFIG_SPI_SPIDEV=y
+
+CONFIG_POWER_RESET=y
+
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XZ=y
+
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index 2ff3b17bfab1..04b8d2262f9d 100644
--- a/arch/mips/generic/Kconfig
+++ b/arch/mips/generic/Kconfig
@@ -27,6 +27,23 @@ config LEGACY_BOARD_SEAD3
 	  Enable this to include support for booting on MIPS SEAD-3 FPGA-based
 	  development boards, which boot using a legacy boot protocol.
 
+comment "MSCC Ocelot doesn't work with SEAD3 enabled"
+       depends on LEGACY_BOARD_SEAD3
+
+config LEGACY_BOARD_OCELOT
+	bool "Support MSCC Ocelot boards"
+	depends on LEGACY_BOARD_SEAD3=n
+	select LEGACY_BOARDS
+	select MSCC_OCELOT
+
+config MSCC_OCELOT
+	bool
+	select DMA_NONCOHERENT
+	select GPIOLIB
+	select MSCC_OCELOT_IRQ
+	select SYS_HAS_EARLY_PRINTK
+	select USE_GENERIC_EARLY_PRINTK_8250
+
 comment "FIT/UHI Boards"
 
 config FIT_IMAGE_FDT_BOSTON
diff --git a/arch/mips/generic/Makefile b/arch/mips/generic/Makefile
index 5c31e0c4697d..d03a36f869a4 100644
--- a/arch/mips/generic/Makefile
+++ b/arch/mips/generic/Makefile
@@ -14,5 +14,6 @@ obj-y += proc.o
 
 obj-$(CONFIG_YAMON_DT_SHIM)		+= yamon-dt.o
 obj-$(CONFIG_LEGACY_BOARD_SEAD3)	+= board-sead3.o
+obj-$(CONFIG_LEGACY_BOARD_OCELOT)	+= board-ocelot.o
 obj-$(CONFIG_KEXEC)			+= kexec.o
 obj-$(CONFIG_VIRT_BOARD_RANCHU)		+= board-ranchu.o
diff --git a/arch/mips/generic/board-ocelot.c b/arch/mips/generic/board-ocelot.c
new file mode 100644
index 000000000000..752c6edbe1d5
--- /dev/null
+++ b/arch/mips/generic/board-ocelot.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi MIPS SoC support
+ *
+ * Copyright (c) 2017 Microsemi Corporation
+ */
+#include <asm/machine.h>
+#include <asm/prom.h>
+
+#define DEVCPU_GCB_CHIP_REGS_CHIP_ID	0x71070000
+#define CHIP_ID_PART_ID			GENMASK(27, 12)
+
+#define OCELOT_PART_ID			(0x7514 << 12)
+
+#define UART_UART			0x70100000
+
+static __init bool ocelot_detect(void)
+{
+	u32 rev;
+
+	rev = __raw_readl((void *)DEVCPU_GCB_CHIP_REGS_CHIP_ID);
+
+	if ((rev & CHIP_ID_PART_ID) != OCELOT_PART_ID)
+		return 0;
+
+	/* Copy command line from bootloader early for Initrd detection */
+	if (fw_arg0 < 10 && (fw_arg1 & 0xFFF00000) == 0x80000000) {
+		unsigned int prom_argc = fw_arg0;
+		const char **prom_argv = (const char **)fw_arg1;
+
+		if (prom_argc > 1 && strlen(prom_argv[1]) > 0)
+			/* ignore all built-in args if any f/w args given */
+			strcpy(arcs_cmdline, prom_argv[1]);
+	}
+
+	return 1;
+}
+
+static __init unsigned int ocelot_measure_hpt_freq(void)
+{
+	struct device_node *np;
+	u32 freq;
+
+	np = of_find_node_by_name(NULL, "cpus");
+	if (!np)
+		panic("missing 'cpus' DT node");
+	if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
+		panic("missing 'mips-hpt-frequency' property");
+	of_node_put(np);
+
+	return freq;
+}
+
+static void __init ocelot_earlyprintk_init(void)
+{
+	void __iomem *uart_base;
+
+	uart_base = ioremap_nocache(UART_UART, 0x20);
+	setup_8250_early_printk_port((unsigned long)uart_base, 2, 50000);
+}
+
+static void __init ocelot_late_init(void)
+{
+	ocelot_earlyprintk_init();
+}
+
+static __init const void *ocelot_fixup_fdt(const void *fdt,
+					   const void *match_data)
+{
+	/* This has to be done so late because ioremap needs to work */
+	late_time_init = ocelot_late_init;
+
+	return fdt;
+}
+
+extern char __dtb_ocelot_pcb123_begin[];
+
+MIPS_MACHINE(ocelot) = {
+	.fdt = __dtb_ocelot_pcb123_begin,
+	.fixup_fdt = ocelot_fixup_fdt,
+	.detect = ocelot_detect,
+	.measure_hpt_freq = ocelot_measure_hpt_freq,
+};
-- 
2.16.2

[PATCH v4 6/6] MAINTAINERS: Add entry for Microsemi MIPS SoCs

[Alexandre Belloni]

Add myself as a maintainer for the Microsemi MIPS SoCs.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
 MAINTAINERS | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 3bdc260e36b7..14ce8b290fea 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9156,6 +9156,15 @@ S:	Maintained
 F:	drivers/usb/misc/usb251xb.c
 F:	Documentation/devicetree/bindings/usb/usb251xb.txt
 
+MICROSEMI MIPS SOCS
+M:	Alexandre Belloni <alexandre.belloni@bootlin.com>
+L:	linux-mips@linux-mips.org
+S:	Maintained
+F:	arch/mips/generic/board-ocelot.c
+F:	arch/mips/configs/generic/board-ocelot.config
+F:	arch/mips/boot/dts/mscc/
+F:	Documentation/devicetree/bindings/mips/mscc.txt
+
 MICROSEMI SMART ARRAY SMARTPQI DRIVER (smartpqi)
 M:	Don Brace <don.brace@microsemi.com>
 L:	esc.storagedev@microsemi.com
-- 
2.16.2

Re: [PATCH v4 5/6] MIPS: generic: Add support for Microsemi Ocelot

[James Hogan]

[-- Attachment #1: Type: text/plain, Size: 6712 bytes --]

On Fri, Mar 02, 2018 at 11:48:10PM +0100, Alexandre Belloni wrote:
> Introduce support for the MIPS based Microsemi Ocelot SoCs.
> 
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
>  arch/mips/Makefile                            |  4 ++
>  arch/mips/configs/generic/board-ocelot.config | 40 +++++++++++++
>  arch/mips/generic/Kconfig                     | 17 ++++++
>  arch/mips/generic/Makefile                    |  1 +
>  arch/mips/generic/board-ocelot.c              | 83 +++++++++++++++++++++++++++
>  5 files changed, 145 insertions(+)
>  create mode 100644 arch/mips/configs/generic/board-ocelot.config
>  create mode 100644 arch/mips/generic/board-ocelot.c

very nice :-)

> diff --git a/arch/mips/configs/generic/board-ocelot.config b/arch/mips/configs/generic/board-ocelot.config
> new file mode 100644
> index 000000000000..7f9e1eaccc34
> --- /dev/null
> +++ b/arch/mips/configs/generic/board-ocelot.config
> @@ -0,0 +1,40 @@
> +# require CONFIG_32BIT=y

If this has a 24KEc, does it make sense to use:
# require CONFIG_CPU_MIPS32_R2=y
like ni169445 and xilfpga do. There doesn't seem to be any point
enabling support in 32r6 generic kernels for example.

Similarly if the platform is little endian only, you could also add:
# require CONFIG_CPU_LITTLE_ENDIAN=y

> +
> +CONFIG_LEGACY_BOARD_OCELOT=y
> +
> +CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y

Hmm, can this break any other generic platforms that already make the
DTB command line override the arcs_cmdline? Paul?

I.e. In arch_mem_init() the condition of copying arcs_cmdline to
boot_command_line would switch from !boot_command_line[0] to
arcs_cmdline[0]. I suppose arcs_cmdline[] may not have been written in
those cases. If its safe then it should probably be a standard thing
selected by MIPS_GENERIC instead of a board specific thing.

> +CONFIG_MAGIC_SYSRQ=y

Perhaps its worth adding this to the base generic_defconfig if its
useful to have.

> +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1

That is already the default, though I wonder if we should set it to 0
for safety, which still retains the functionality, but just may require
writing to /proc/sys/kernel/sysrq or passing sysrq_always_enabled as a
kernel parameter to use sysrq from keyboard / uart.

> diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
> index 2ff3b17bfab1..04b8d2262f9d 100644
> --- a/arch/mips/generic/Kconfig
> +++ b/arch/mips/generic/Kconfig
> @@ -27,6 +27,23 @@ config LEGACY_BOARD_SEAD3
>  	  Enable this to include support for booting on MIPS SEAD-3 FPGA-based
>  	  development boards, which boot using a legacy boot protocol.
>  
> +comment "MSCC Ocelot doesn't work with SEAD3 enabled"
> +       depends on LEGACY_BOARD_SEAD3

broken indentation. Tab please.

> +
> +config LEGACY_BOARD_OCELOT
> +	bool "Support MSCC Ocelot boards"
> +	depends on LEGACY_BOARD_SEAD3=n
> +	select LEGACY_BOARDS
> +	select MSCC_OCELOT
> +
> +config MSCC_OCELOT
> +	bool
> +	select DMA_NONCOHERENT

MIPS_GENERIC already selects DMA_PERFDEV_COHERENT, which should already
treat devices as non-coherent unless they have the dma-coherent DT
property.

> +	select GPIOLIB
> +	select MSCC_OCELOT_IRQ
> +	select SYS_HAS_EARLY_PRINTK
> +	select USE_GENERIC_EARLY_PRINTK_8250
> +
>  comment "FIT/UHI Boards"
>  
>  config FIT_IMAGE_FDT_BOSTON
> diff --git a/arch/mips/generic/Makefile b/arch/mips/generic/Makefile
> index 5c31e0c4697d..d03a36f869a4 100644
> --- a/arch/mips/generic/Makefile
> +++ b/arch/mips/generic/Makefile
> @@ -14,5 +14,6 @@ obj-y += proc.o
>  
>  obj-$(CONFIG_YAMON_DT_SHIM)		+= yamon-dt.o
>  obj-$(CONFIG_LEGACY_BOARD_SEAD3)	+= board-sead3.o
> +obj-$(CONFIG_LEGACY_BOARD_OCELOT)	+= board-ocelot.o
>  obj-$(CONFIG_KEXEC)			+= kexec.o
>  obj-$(CONFIG_VIRT_BOARD_RANCHU)		+= board-ranchu.o
> diff --git a/arch/mips/generic/board-ocelot.c b/arch/mips/generic/board-ocelot.c
> new file mode 100644
> index 000000000000..752c6edbe1d5
> --- /dev/null
> +++ b/arch/mips/generic/board-ocelot.c
> @@ -0,0 +1,83 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Microsemi MIPS SoC support
> + *
> + * Copyright (c) 2017 Microsemi Corporation
> + */
> +#include <asm/machine.h>
> +#include <asm/prom.h>
> +
> +#define DEVCPU_GCB_CHIP_REGS_CHIP_ID	0x71070000
> +#define CHIP_ID_PART_ID			GENMASK(27, 12)
> +
> +#define OCELOT_PART_ID			(0x7514 << 12)
> +
> +#define UART_UART			0x70100000
> +
> +static __init bool ocelot_detect(void)
> +{
> +	u32 rev;
> +
> +	rev = __raw_readl((void *)DEVCPU_GCB_CHIP_REGS_CHIP_ID);

Isn't that an address in the user segment, i.e. TLB mapped virtual
memory? Does the bootloader set up a wired mapping for it or something?

The address looks similar to UART_UART which is given to ioremap so must
be a physical address. Perhaps the mapping you're using is 1:1
virtual:physical address?

If its using a TLB mapping, then:
1) That isn't safe this early to run on other platforms, as it'll give a
   TLB refill exception. It should be quite possible to detect such a
   mapping to make it safer though.
2) If yamon initialises the TLB to a known state, then that may well be
   a hacky but workable way to distinguish yamon (sead3) from redboot
   (mscc) in future.

> +
> +	if ((rev & CHIP_ID_PART_ID) != OCELOT_PART_ID)
> +		return 0;
> +
> +	/* Copy command line from bootloader early for Initrd detection */
> +	if (fw_arg0 < 10 && (fw_arg1 & 0xFFF00000) == 0x80000000) {
> +		unsigned int prom_argc = fw_arg0;
> +		const char **prom_argv = (const char **)fw_arg1;
> +
> +		if (prom_argc > 1 && strlen(prom_argv[1]) > 0)
> +			/* ignore all built-in args if any f/w args given */
> +			strcpy(arcs_cmdline, prom_argv[1]);
> +	}
> +
> +	return 1;
> +}
> +
> +static __init unsigned int ocelot_measure_hpt_freq(void)
> +{
> +	struct device_node *np;
> +	u32 freq;
> +
> +	np = of_find_node_by_name(NULL, "cpus");
> +	if (!np)
> +		panic("missing 'cpus' DT node");
> +	if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
> +		panic("missing 'mips-hpt-frequency' property");
> +	of_node_put(np);
> +
> +	return freq;
> +}

Is it too late to change this to use the generic mips_hpt_frequency
calculation in plat_time_init()? The DT would have to provide e.g. a
fixed-clock and link to it from the CPU node.

See arch/mips/boot/dts/ni/169445.dts for an example of how it could
look.

That would allow you to eliminate this machine callback altogether, as
well as being more flexible if you ever needed the frequency to be
calculated more dynamically based on platform registers.

Thanks!
James

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Re: [PATCH v4 4/6] MIPS: mscc: add ocelot PCB123 device tree

[Sergei Shtylyov]

Hello!

On 3/3/2018 1:48 AM, Alexandre Belloni wrote:

> Add a device tree for the Microsemi Ocelot PCB123 evaluation board.
> 
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
[...]
> diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
> new file mode 100644
> index 000000000000..42bd404471f6
> --- /dev/null
> +++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/* Copyright (c) 2017 Microsemi Corporation */
> +
> +/dts-v1/;
> +
> +#include "ocelot.dtsi"
> +
> +/ {
> +	compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory {

    Needs to be "memory@0" as you have the "regs" prop.

> +		device_type = "memory";
> +		reg = <0x0 0x0e000000>;
> +	};
> +};
[...]

MBR, Sergei

Re: [PATCH v4 5/6] MIPS: generic: Add support for Microsemi Ocelot

[Alexandre Belloni]

On 03/03/2018 at 00:25:29 +0000, James Hogan wrote:
> Similarly if the platform is little endian only, you could also add:
> # require CONFIG_CPU_LITTLE_ENDIAN=y
> 

It supports big endian.

> > +
> > +CONFIG_LEGACY_BOARD_OCELOT=y
> > +
> > +CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
> 
> Hmm, can this break any other generic platforms that already make the
> DTB command line override the arcs_cmdline? Paul?
> 
> I.e. In arch_mem_init() the condition of copying arcs_cmdline to
> boot_command_line would switch from !boot_command_line[0] to
> arcs_cmdline[0]. I suppose arcs_cmdline[] may not have been written in
> those cases. If its safe then it should probably be a standard thing
> selected by MIPS_GENERIC instead of a board specific thing.
> 

Actually, this is not needed so I'm removing it.

> > +CONFIG_MAGIC_SYSRQ=y
> 
> Perhaps its worth adding this to the base generic_defconfig if its
> useful to have.
> 

Our test automation tool is using it to reboot the platform but I don't
know if this is useful for anybody else.

> > +static __init bool ocelot_detect(void)
> > +{
> > +	u32 rev;
> > +
> > +	rev = __raw_readl((void *)DEVCPU_GCB_CHIP_REGS_CHIP_ID);
> 
> Isn't that an address in the user segment, i.e. TLB mapped virtual
> memory? Does the bootloader set up a wired mapping for it or something?
> 
> The address looks similar to UART_UART which is given to ioremap so must
> be a physical address. Perhaps the mapping you're using is 1:1
> virtual:physical address?
> 
> If its using a TLB mapping, then:
> 1) That isn't safe this early to run on other platforms, as it'll give a
>    TLB refill exception. It should be quite possible to detect such a
>    mapping to make it safer though.
> 2) If yamon initialises the TLB to a known state, then that may well be
>    a hacky but workable way to distinguish yamon (sead3) from redboot
>    (mscc) in future.
> 

Yes, this is an identity mapping that is installed by redboot because
all the peripherals are in the user segment.

-- 
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com