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X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Mar 2018 12:55:44.2399 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a0a93633-d7c7-4a93-998e-08d583619309 X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;Ip=[192.88.168.50];Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR0301MB0597 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1594193028765615716?= X-GMAIL-MSGID: =?utf-8?q?1594193028765615716?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: From: Changming Huang Add the macro definition for global soc bus configuration register 0/1 Signed-off-by: Changming Huang Signed-off-by: Ran Wang --- Changes in v5: - no change Changes in v4: - no change Changes in v3: - no change Changes in v2: - split the patch - add more macro definition for soc bus configuration register drivers/usb/dwc3/core.h | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+), 0 deletions(-) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 860d2bc..8f97f61 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -153,6 +153,32 @@ /* Bit fields */ +/* Global SoC Bus Configuration Register 0 */ +#define AXI3_CACHE_TYPE_AW 0x8 /* write allocate */ +#define AXI3_CACHE_TYPE_AR 0x4 /* read allocate */ +#define AXI3_CACHE_TYPE_SNP 0x2 /* cacheable */ +#define AXI3_CACHE_TYPE_BUF 0x1 /* bufferable */ +#define DWC3_GSBUSCFG0_DATARD_SHIFT 28 +#define DWC3_GSBUSCFG0_DESCRD_SHIFT 24 +#define DWC3_GSBUSCFG0_DATAWR_SHIFT 20 +#define DWC3_GSBUSCFG0_DESCWR_SHIFT 16 +#define DWC3_GSBUSCFG0_SNP_MASK 0xffff0000 +#define DWC3_GSBUSCFG0_DATABIGEND (1 << 11) +#define DWC3_GSBUSCFG0_DESCBIGEND (1 << 10) +#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */ +#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */ +#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */ +#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */ +#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */ +#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */ +#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */ +#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */ +#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff + +/* Global SoC Bus Configuration Register 1 */ +#define DWC3_GSBUSCFG1_1KPAGEENA (1 << 12) /* 1K page boundary enable */ +#define DWC3_GSBUSCFG1_PTRANSLIMIT_MASK 0xf00 + /* Global Debug Queue/FIFO Space Available Register */ #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) -- 1.7.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ran Wang Subject: [PATCH v5 1/3] USB3/DWC3: Add definition for global soc bus configuration register Date: Tue, 6 Mar 2018 16:59:09 +0800 Message-ID: <20180306085911.5930-1-ran.wang_1@nxp.com> Mime-Version: 1.0 Content-Type: text/plain Return-path: Sender: linux-kernel-owner@vger.kernel.org To: Felipe Balbi , Shawn Guo , Greg Kroah-Hartman , Rob Herring , Mark Rutland , Russell King , Catalin Marinas , Will Deacon , Li Yang Cc: ran.wang_1@nxp.com, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Changming Huang List-Id: devicetree@vger.kernel.org From: Changming Huang Add the macro definition for global soc bus configuration register 0/1 Signed-off-by: Changming Huang Signed-off-by: Ran Wang --- Changes in v5: - no change Changes in v4: - no change Changes in v3: - no change Changes in v2: - split the patch - add more macro definition for soc bus configuration register drivers/usb/dwc3/core.h | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+), 0 deletions(-) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 860d2bc..8f97f61 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -153,6 +153,32 @@ /* Bit fields */ +/* Global SoC Bus Configuration Register 0 */ +#define AXI3_CACHE_TYPE_AW 0x8 /* write allocate */ +#define AXI3_CACHE_TYPE_AR 0x4 /* read allocate */ +#define AXI3_CACHE_TYPE_SNP 0x2 /* cacheable */ +#define AXI3_CACHE_TYPE_BUF 0x1 /* bufferable */ +#define DWC3_GSBUSCFG0_DATARD_SHIFT 28 +#define DWC3_GSBUSCFG0_DESCRD_SHIFT 24 +#define DWC3_GSBUSCFG0_DATAWR_SHIFT 20 +#define DWC3_GSBUSCFG0_DESCWR_SHIFT 16 +#define DWC3_GSBUSCFG0_SNP_MASK 0xffff0000 +#define DWC3_GSBUSCFG0_DATABIGEND (1 << 11) +#define DWC3_GSBUSCFG0_DESCBIGEND (1 << 10) +#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */ +#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */ +#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */ +#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */ +#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */ +#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */ +#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */ +#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */ +#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff + +/* Global SoC Bus Configuration Register 1 */ +#define DWC3_GSBUSCFG1_1KPAGEENA (1 << 12) /* 1K page boundary enable */ +#define DWC3_GSBUSCFG1_PTRANSLIMIT_MASK 0xf00 + /* Global Debug Queue/FIFO Space Available Register */ #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) -- 1.7.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v5,1/3] USB3/DWC3: Add definition for global soc bus configuration register From: Ran Wang Message-Id: <20180306085911.5930-1-ran.wang_1@nxp.com> Date: Tue, 6 Mar 2018 16:59:09 +0800 To: Felipe Balbi , Shawn Guo , Greg Kroah-Hartman , Rob Herring , Mark Rutland , Russell King , Catalin Marinas , Will Deacon , Li Yang Cc: ran.wang_1@nxp.com, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Changming Huang List-ID: RnJvbTogQ2hhbmdtaW5nIEh1YW5nIDxqZXJyeS5odWFuZ0BueHAuY29tPgoKQWRkIHRoZSBtYWNy byBkZWZpbml0aW9uIGZvciBnbG9iYWwgc29jIGJ1cyBjb25maWd1cmF0aW9uIHJlZ2lzdGVyIDAv MQoKU2lnbmVkLW9mZi1ieTogQ2hhbmdtaW5nIEh1YW5nIDxqZXJyeS5odWFuZ0BueHAuY29tPgpT aWduZWQtb2ZmLWJ5OiBSYW4gV2FuZyA8cmFuLndhbmdfMUBueHAuY29tPgotLS0KQ2hhbmdlcyBp biB2NToKICAtIG5vIGNoYW5nZQpDaGFuZ2VzIGluIHY0OgogIC0gbm8gY2hhbmdlCkNoYW5nZXMg aW4gdjM6CiAgLSBubyBjaGFuZ2UKQ2hhbmdlcyBpbiB2MjoKICAtIHNwbGl0IHRoZSBwYXRjaAog IC0gYWRkIG1vcmUgbWFjcm8gZGVmaW5pdGlvbiBmb3Igc29jIGJ1cyBjb25maWd1cmF0aW9uIHJl Z2lzdGVyCgogZHJpdmVycy91c2IvZHdjMy9jb3JlLmggfCAgIDI2ICsrKysrKysrKysrKysrKysr KysrKysrKysrCiAxIGZpbGVzIGNoYW5nZWQsIDI2IGluc2VydGlvbnMoKyksIDAgZGVsZXRpb25z KC0pCgpkaWZmIC0tZ2l0IGEvZHJpdmVycy91c2IvZHdjMy9jb3JlLmggYi9kcml2ZXJzL3VzYi9k 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YWlsYWJsZSBSZWdpc3RlciAqLwogI2RlZmluZSBEV0MzX0dEQkdGSUZPU1BBQ0VfTlVNKG4pCSgo bikgJiAweDFmKQogI2RlZmluZSBEV0MzX0dEQkdGSUZPU1BBQ0VfVFlQRShuKQkoKChuKSA8PCA1 KSAmIDB4MWUwKQo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: ran.wang_1@nxp.com (Ran Wang) Date: Tue, 6 Mar 2018 16:59:09 +0800 Subject: [PATCH v5 1/3] USB3/DWC3: Add definition for global soc bus configuration register Message-ID: <20180306085911.5930-1-ran.wang_1@nxp.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org From: Changming Huang Add the macro definition for global soc bus configuration register 0/1 Signed-off-by: Changming Huang Signed-off-by: Ran Wang --- Changes in v5: - no change Changes in v4: - no change Changes in v3: - no change Changes in v2: - split the patch - add more macro definition for soc bus configuration register drivers/usb/dwc3/core.h | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+), 0 deletions(-) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 860d2bc..8f97f61 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -153,6 +153,32 @@ /* Bit fields */ +/* Global SoC Bus Configuration Register 0 */ +#define AXI3_CACHE_TYPE_AW 0x8 /* write allocate */ +#define AXI3_CACHE_TYPE_AR 0x4 /* read allocate */ +#define AXI3_CACHE_TYPE_SNP 0x2 /* cacheable */ +#define AXI3_CACHE_TYPE_BUF 0x1 /* bufferable */ +#define DWC3_GSBUSCFG0_DATARD_SHIFT 28 +#define DWC3_GSBUSCFG0_DESCRD_SHIFT 24 +#define DWC3_GSBUSCFG0_DATAWR_SHIFT 20 +#define DWC3_GSBUSCFG0_DESCWR_SHIFT 16 +#define DWC3_GSBUSCFG0_SNP_MASK 0xffff0000 +#define DWC3_GSBUSCFG0_DATABIGEND (1 << 11) +#define DWC3_GSBUSCFG0_DESCBIGEND (1 << 10) +#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */ +#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */ +#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */ +#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */ +#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */ +#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */ +#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */ +#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */ +#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff + +/* Global SoC Bus Configuration Register 1 */ +#define DWC3_GSBUSCFG1_1KPAGEENA (1 << 12) /* 1K page boundary enable */ +#define DWC3_GSBUSCFG1_PTRANSLIMIT_MASK 0xf00 + /* Global Debug Queue/FIFO Space Available Register */ #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) -- 1.7.1