From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753601AbeCFMxI (ORCPT ); Tue, 6 Mar 2018 07:53:08 -0500 Received: from bombadil.infradead.org ([198.137.202.133]:34034 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753223AbeCFMxG (ORCPT ); Tue, 6 Mar 2018 07:53:06 -0500 Date: Tue, 6 Mar 2018 04:53:04 -0800 From: Matthew Wilcox To: Aaron Lu Cc: Vlastimil Babka , Michal Hocko , linux-mm@kvack.org, linux-kernel@vger.kernel.org, Andrew Morton , Huang Ying , Dave Hansen , Kemi Wang , Tim Chen , Andi Kleen , Mel Gorman , David Rientjes Subject: Re: [PATCH v4 3/3] mm/free_pcppages_bulk: prefetch buddy while not holding lock Message-ID: <20180306125303.GA13722@bombadil.infradead.org> References: <20180301062845.26038-1-aaron.lu@intel.com> <20180301062845.26038-4-aaron.lu@intel.com> <20180301140044.GK15057@dhcp22.suse.cz> <20180305114159.GA32573@intel.com> <20180306122733.GA9664@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180306122733.GA9664@intel.com> User-Agent: Mutt/1.9.2 (2017-12-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 06, 2018 at 08:27:33PM +0800, Aaron Lu wrote: > On Tue, Mar 06, 2018 at 08:55:57AM +0100, Vlastimil Babka wrote: > > So the adjacent line prefetch might be disabled? Could you check bios or > > the MSR mentioned in > > https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-control-on-some-intel-processors > > root@lkp-bdw-ep2 ~# rdmsr 0x1a4 > 0 Technically 0x1a4 is per-core, so you should run rdmsr -a 0x1a4 in order to check all the cores. But I can't imagine they're being set differently on each core. > > instructions (calculated from itlb misses and insns-per-itlb-miss) shows > > less than 1% increase, so dunno. And the improvement comes from reduced > > dTLB-load-misses? That makes no sense for order-0 buddy struct pages > > which always share a page. And the memmap mapping should use huge pages. > > THP is disabled to stress order 0 pages(should have mentioned this in > patch's description, sorry about this). THP isn't related to memmap; the kernel uses huge pages (usually the 1G pages) in order to map its own memory. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl0-f69.google.com (mail-pl0-f69.google.com [209.85.160.69]) by kanga.kvack.org (Postfix) with ESMTP id CBB836B0005 for ; Tue, 6 Mar 2018 07:53:07 -0500 (EST) Received: by mail-pl0-f69.google.com with SMTP id l5-v6so9740115pli.8 for ; Tue, 06 Mar 2018 04:53:07 -0800 (PST) Received: from bombadil.infradead.org (bombadil.infradead.org. [2607:7c80:54:e::133]) by mx.google.com with ESMTPS id l11-v6si11541906pln.323.2018.03.06.04.53.06 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Mar 2018 04:53:06 -0800 (PST) Date: Tue, 6 Mar 2018 04:53:04 -0800 From: Matthew Wilcox Subject: Re: [PATCH v4 3/3] mm/free_pcppages_bulk: prefetch buddy while not holding lock Message-ID: <20180306125303.GA13722@bombadil.infradead.org> References: <20180301062845.26038-1-aaron.lu@intel.com> <20180301062845.26038-4-aaron.lu@intel.com> <20180301140044.GK15057@dhcp22.suse.cz> <20180305114159.GA32573@intel.com> <20180306122733.GA9664@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180306122733.GA9664@intel.com> Sender: owner-linux-mm@kvack.org List-ID: To: Aaron Lu Cc: Vlastimil Babka , Michal Hocko , linux-mm@kvack.org, linux-kernel@vger.kernel.org, Andrew Morton , Huang Ying , Dave Hansen , Kemi Wang , Tim Chen , Andi Kleen , Mel Gorman , David Rientjes On Tue, Mar 06, 2018 at 08:27:33PM +0800, Aaron Lu wrote: > On Tue, Mar 06, 2018 at 08:55:57AM +0100, Vlastimil Babka wrote: > > So the adjacent line prefetch might be disabled? Could you check bios or > > the MSR mentioned in > > https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-control-on-some-intel-processors > > root@lkp-bdw-ep2 ~# rdmsr 0x1a4 > 0 Technically 0x1a4 is per-core, so you should run rdmsr -a 0x1a4 in order to check all the cores. But I can't imagine they're being set differently on each core. > > instructions (calculated from itlb misses and insns-per-itlb-miss) shows > > less than 1% increase, so dunno. And the improvement comes from reduced > > dTLB-load-misses? That makes no sense for order-0 buddy struct pages > > which always share a page. And the memmap mapping should use huge pages. > > THP is disabled to stress order 0 pages(should have mentioned this in > patch's description, sorry about this). THP isn't related to memmap; the kernel uses huge pages (usually the 1G pages) in order to map its own memory. -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. 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