* [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND)
@ 2018-03-08 9:50 Michal Wajdeczko
2018-03-08 9:50 ` [PATCH v2 1/4] drm/i915: Include i915_reg.h in intel_ringbuffer.h Michal Wajdeczko
` (6 more replies)
0 siblings, 7 replies; 13+ messages in thread
From: Michal Wajdeczko @ 2018-03-08 9:50 UTC (permalink / raw)
To: intel-gfx
This is a resend, to make patchwork happy.
All patches already been reviewed.
Michal Wajdeczko (4):
drm/i915: Include i915_reg.h in intel_ringbuffer.h
drm/i915: Change parameters order in i915_gem_batch_pool_init
drm/i915: Make header i915_pmu.h more robust
drm/i915: Move i915_gpu_error into its own header
drivers/gpu/drm/i915/i915_drv.h | 332 +--------------------------
drivers/gpu/drm/i915/i915_gem_batch_pool.c | 30 +--
drivers/gpu/drm/i915/i915_gem_batch_pool.h | 29 +--
drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
drivers/gpu/drm/i915/i915_gpu_error.h | 355 +++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_pmu.c | 27 +--
drivers/gpu/drm/i915/i915_pmu.h | 30 +--
drivers/gpu/drm/i915/intel_engine_cs.c | 9 +-
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
9 files changed, 388 insertions(+), 426 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_gpu_error.h
--
1.9.1
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 1/4] drm/i915: Include i915_reg.h in intel_ringbuffer.h
2018-03-08 9:50 [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND) Michal Wajdeczko
@ 2018-03-08 9:50 ` Michal Wajdeczko
2018-03-08 9:50 ` [PATCH v2 2/4] drm/i915: Change parameters order in i915_gem_batch_pool_init Michal Wajdeczko
` (5 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Michal Wajdeczko @ 2018-03-08 9:50 UTC (permalink / raw)
To: intel-gfx
Header intel_ringbuffer.h is using definitions from i915_reg.h
but forget to include it. Remove this hidden dependency by
explicitly include missing header.
v2: add reminder (Chris)
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index d8ddea0..adf0f3b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -7,6 +7,7 @@
#include "i915_gem_batch_pool.h"
#include "i915_gem_timeline.h"
+#include "i915_reg.h" /* FIXME split out i915_gpu_commands.h */
#include "i915_pmu.h"
#include "i915_request.h"
#include "i915_selftest.h"
--
1.9.1
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 2/4] drm/i915: Change parameters order in i915_gem_batch_pool_init
2018-03-08 9:50 [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND) Michal Wajdeczko
2018-03-08 9:50 ` [PATCH v2 1/4] drm/i915: Include i915_reg.h in intel_ringbuffer.h Michal Wajdeczko
@ 2018-03-08 9:50 ` Michal Wajdeczko
2018-03-08 9:50 ` [PATCH v2 3/4] drm/i915: Make header i915_pmu.h more robust Michal Wajdeczko
` (4 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Michal Wajdeczko @ 2018-03-08 9:50 UTC (permalink / raw)
To: intel-gfx
Function i915_gem_batch_pool_init() failed to follow obj-verb
naming schema. Fix that by swapping function parameters.
While here, change license text to SPDX format.
v2: use intel_engine_init_batch_pool (Chris) as proxy (Michal)
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem_batch_pool.c | 30 ++++++------------------------
drivers/gpu/drm/i915/i915_gem_batch_pool.h | 29 +++++------------------------
drivers/gpu/drm/i915/intel_engine_cs.c | 9 ++++++---
3 files changed, 17 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.c b/drivers/gpu/drm/i915/i915_gem_batch_pool.c
index d3cbe84..f3890b6 100644
--- a/drivers/gpu/drm/i915/i915_gem_batch_pool.c
+++ b/drivers/gpu/drm/i915/i915_gem_batch_pool.c
@@ -1,29 +1,11 @@
/*
- * Copyright © 2014 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
+ * SPDX-License-Identifier: MIT
*
+ * Copyright © 2014-2018 Intel Corporation
*/
-#include "i915_drv.h"
#include "i915_gem_batch_pool.h"
+#include "i915_drv.h"
/**
* DOC: batch pool
@@ -41,11 +23,11 @@
/**
* i915_gem_batch_pool_init() - initialize a batch buffer pool
- * @engine: the associated request submission engine
* @pool: the batch buffer pool
+ * @engine: the associated request submission engine
*/
-void i915_gem_batch_pool_init(struct intel_engine_cs *engine,
- struct i915_gem_batch_pool *pool)
+void i915_gem_batch_pool_init(struct i915_gem_batch_pool *pool,
+ struct intel_engine_cs *engine)
{
int n;
diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.h b/drivers/gpu/drm/i915/i915_gem_batch_pool.h
index 10d5ac4..56947da 100644
--- a/drivers/gpu/drm/i915/i915_gem_batch_pool.h
+++ b/drivers/gpu/drm/i915/i915_gem_batch_pool.h
@@ -1,31 +1,13 @@
/*
- * Copyright © 2014 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
+ * SPDX-License-Identifier: MIT
*
+ * Copyright © 2014-2018 Intel Corporation
*/
#ifndef I915_GEM_BATCH_POOL_H
#define I915_GEM_BATCH_POOL_H
-#include "i915_drv.h"
+#include <linux/types.h>
struct intel_engine_cs;
@@ -34,9 +16,8 @@ struct i915_gem_batch_pool {
struct list_head cache_list[4];
};
-/* i915_gem_batch_pool.c */
-void i915_gem_batch_pool_init(struct intel_engine_cs *engine,
- struct i915_gem_batch_pool *pool);
+void i915_gem_batch_pool_init(struct i915_gem_batch_pool *pool,
+ struct intel_engine_cs *engine);
void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool);
struct drm_i915_gem_object*
i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool, size_t size);
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 4ba139c..9a48d4a 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -441,6 +441,11 @@ static void intel_engine_init_timeline(struct intel_engine_cs *engine)
engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id];
}
+static void intel_engine_init_batch_pool(struct intel_engine_cs *engine)
+{
+ i915_gem_batch_pool_init(&engine->batch_pool, engine);
+}
+
static bool csb_force_mmio(struct drm_i915_private *i915)
{
/*
@@ -485,11 +490,9 @@ static void intel_engine_init_execlist(struct intel_engine_cs *engine)
void intel_engine_setup_common(struct intel_engine_cs *engine)
{
intel_engine_init_execlist(engine);
-
intel_engine_init_timeline(engine);
intel_engine_init_hangcheck(engine);
- i915_gem_batch_pool_init(engine, &engine->batch_pool);
-
+ intel_engine_init_batch_pool(engine);
intel_engine_init_cmd_parser(engine);
}
--
1.9.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 3/4] drm/i915: Make header i915_pmu.h more robust
2018-03-08 9:50 [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND) Michal Wajdeczko
2018-03-08 9:50 ` [PATCH v2 1/4] drm/i915: Include i915_reg.h in intel_ringbuffer.h Michal Wajdeczko
2018-03-08 9:50 ` [PATCH v2 2/4] drm/i915: Change parameters order in i915_gem_batch_pool_init Michal Wajdeczko
@ 2018-03-08 9:50 ` Michal Wajdeczko
2018-03-08 9:50 ` [PATCH v2 4/4] drm/i915: Move i915_gpu_error into its own header Michal Wajdeczko
` (3 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Michal Wajdeczko @ 2018-03-08 9:50 UTC (permalink / raw)
To: intel-gfx
Definitions in i915_pmu.h header depend on other types and
declarations that were not explicitly included. Fix that by
adding related headers and forward declarations.
While here, change license text to SPDX format.
v2: don't drop "intel_ringbuffer.h" (Tvrtko)
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_pmu.c | 27 +++------------------------
drivers/gpu/drm/i915/i915_pmu.h | 30 ++++++++++--------------------
2 files changed, 13 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 964467b..4bc7aef 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -1,33 +1,12 @@
/*
- * Copyright © 2017 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
+ * SPDX-License-Identifier: MIT
*
+ * Copyright © 2017-2018 Intel Corporation
*/
-#include <linux/perf_event.h>
-#include <linux/pm_runtime.h>
-
-#include "i915_drv.h"
#include "i915_pmu.h"
#include "intel_ringbuffer.h"
+#include "i915_drv.h"
/* Frequency for the sampling timer for events which need it. */
#define FREQUENCY 200
diff --git a/drivers/gpu/drm/i915/i915_pmu.h b/drivers/gpu/drm/i915/i915_pmu.h
index aa1b1a9..2ba7352 100644
--- a/drivers/gpu/drm/i915/i915_pmu.h
+++ b/drivers/gpu/drm/i915/i915_pmu.h
@@ -1,29 +1,19 @@
/*
- * Copyright © 2017 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
+ * SPDX-License-Identifier: MIT
*
+ * Copyright © 2017-2018 Intel Corporation
*/
+
#ifndef __I915_PMU_H__
#define __I915_PMU_H__
+#include <linux/hrtimer.h>
+#include <linux/perf_event.h>
+#include <linux/spinlock_types.h>
+#include <drm/i915_drm.h>
+
+struct drm_i915_private;
+
enum {
__I915_SAMPLE_FREQ_ACT = 0,
__I915_SAMPLE_FREQ_REQ,
--
1.9.1
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^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 4/4] drm/i915: Move i915_gpu_error into its own header
2018-03-08 9:50 [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND) Michal Wajdeczko
` (2 preceding siblings ...)
2018-03-08 9:50 ` [PATCH v2 3/4] drm/i915: Make header i915_pmu.h more robust Michal Wajdeczko
@ 2018-03-08 9:50 ` Michal Wajdeczko
2018-03-08 12:11 ` [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND) Chris Wilson
` (2 subsequent siblings)
6 siblings, 0 replies; 13+ messages in thread
From: Michal Wajdeczko @ 2018-03-08 9:50 UTC (permalink / raw)
To: intel-gfx
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=UTF-8, Size: 21286 bytes --]
Error state management code was moved into separate .c unit
but we didn't move related definitions into own header.
v2: move also intel_display_error_state forward decl
fix ("Prefer 'unsigned int' to bare use of 'unsigned'")
warnings detected by checkpatch in moved code (Michal)
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 332 +------------------------------
drivers/gpu/drm/i915/i915_gpu_error.c | 1 +
drivers/gpu/drm/i915/i915_gpu_error.h | 355 ++++++++++++++++++++++++++++++++++
3 files changed, 357 insertions(+), 331 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_gpu_error.h
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 604389d..3341af7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -72,7 +72,7 @@
#include "i915_gem_object.h"
#include "i915_gem_gtt.h"
#include "i915_gem_timeline.h"
-
+#include "i915_gpu_error.h"
#include "i915_request.h"
#include "i915_vma.h"
@@ -453,172 +453,6 @@ struct intel_csr {
uint32_t allowed_dc_mask;
};
-struct intel_display_error_state;
-
-struct i915_gpu_state {
- struct kref ref;
- ktime_t time;
- ktime_t boottime;
- ktime_t uptime;
-
- struct drm_i915_private *i915;
-
- char error_msg[128];
- bool simulated;
- bool awake;
- bool wakelock;
- bool suspended;
- int iommu;
- u32 reset_count;
- u32 suspend_count;
- struct intel_device_info device_info;
- struct intel_driver_caps driver_caps;
- struct i915_params params;
-
- struct i915_error_uc {
- struct intel_uc_fw guc_fw;
- struct intel_uc_fw huc_fw;
- struct drm_i915_error_object *guc_log;
- } uc;
-
- /* Generic register state */
- u32 eir;
- u32 pgtbl_er;
- u32 ier;
- u32 gtier[4], ngtier;
- u32 ccid;
- u32 derrmr;
- u32 forcewake;
- u32 error; /* gen6+ */
- u32 err_int; /* gen7 */
- u32 fault_data0; /* gen8, gen9 */
- u32 fault_data1; /* gen8, gen9 */
- u32 done_reg;
- u32 gac_eco;
- u32 gam_ecochk;
- u32 gab_ctl;
- u32 gfx_mode;
-
- u32 nfence;
- u64 fence[I915_MAX_NUM_FENCES];
- struct intel_overlay_error_state *overlay;
- struct intel_display_error_state *display;
-
- struct drm_i915_error_engine {
- int engine_id;
- /* Software tracked state */
- bool idle;
- bool waiting;
- int num_waiters;
- unsigned long hangcheck_timestamp;
- bool hangcheck_stalled;
- enum intel_engine_hangcheck_action hangcheck_action;
- struct i915_address_space *vm;
- int num_requests;
- u32 reset_count;
-
- /* position of active request inside the ring */
- u32 rq_head, rq_post, rq_tail;
-
- /* our own tracking of ring head and tail */
- u32 cpu_ring_head;
- u32 cpu_ring_tail;
-
- u32 last_seqno;
-
- /* Register state */
- u32 start;
- u32 tail;
- u32 head;
- u32 ctl;
- u32 mode;
- u32 hws;
- u32 ipeir;
- u32 ipehr;
- u32 bbstate;
- u32 instpm;
- u32 instps;
- u32 seqno;
- u64 bbaddr;
- u64 acthd;
- u32 fault_reg;
- u64 faddr;
- u32 rc_psmi; /* sleep state */
- u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
- struct intel_instdone instdone;
-
- struct drm_i915_error_context {
- char comm[TASK_COMM_LEN];
- pid_t pid;
- u32 handle;
- u32 hw_id;
- int priority;
- int ban_score;
- int active;
- int guilty;
- bool bannable;
- } context;
-
- struct drm_i915_error_object {
- u64 gtt_offset;
- u64 gtt_size;
- int page_count;
- int unused;
- u32 *pages[0];
- } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
-
- struct drm_i915_error_object **user_bo;
- long user_bo_count;
-
- struct drm_i915_error_object *wa_ctx;
- struct drm_i915_error_object *default_state;
-
- struct drm_i915_error_request {
- long jiffies;
- pid_t pid;
- u32 context;
- int priority;
- int ban_score;
- u32 seqno;
- u32 head;
- u32 tail;
- } *requests, execlist[EXECLIST_MAX_PORTS];
- unsigned int num_ports;
-
- struct drm_i915_error_waiter {
- char comm[TASK_COMM_LEN];
- pid_t pid;
- u32 seqno;
- } *waiters;
-
- struct {
- u32 gfx_mode;
- union {
- u64 pdp[4];
- u32 pp_dir_base;
- };
- } vm_info;
- } engine[I915_NUM_ENGINES];
-
- struct drm_i915_error_buffer {
- u32 size;
- u32 name;
- u32 rseqno[I915_NUM_ENGINES], wseqno;
- u64 gtt_offset;
- u32 read_domains;
- u32 write_domain;
- s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
- u32 tiling:2;
- u32 dirty:1;
- u32 purgeable:1;
- u32 userptr:1;
- s32 engine:4;
- u32 cache_level:3;
- } *active_bo[I915_NUM_ENGINES], *pinned_bo;
- u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
- struct i915_address_space *active_vm[I915_NUM_ENGINES];
-};
-
enum i915_cache_level {
I915_CACHE_NONE = 0,
I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
@@ -1146,16 +980,6 @@ struct i915_gem_mm {
u32 object_count;
};
-struct drm_i915_error_state_buf {
- struct drm_i915_private *i915;
- unsigned bytes;
- unsigned size;
- int err;
- u8 *buf;
- loff_t start;
- loff_t pos;
-};
-
#define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
@@ -1164,102 +988,6 @@ struct drm_i915_error_state_buf {
#define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
#define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
-struct i915_gpu_error {
- /* For hangcheck timer */
-#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
-#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
-
- struct delayed_work hangcheck_work;
-
- /* For reset and error_state handling. */
- spinlock_t lock;
- /* Protected by the above dev->gpu_error.lock. */
- struct i915_gpu_state *first_error;
-
- atomic_t pending_fb_pin;
-
- unsigned long missed_irq_rings;
-
- /**
- * State variable controlling the reset flow and count
- *
- * This is a counter which gets incremented when reset is triggered,
- *
- * Before the reset commences, the I915_RESET_BACKOFF bit is set
- * meaning that any waiters holding onto the struct_mutex should
- * relinquish the lock immediately in order for the reset to start.
- *
- * If reset is not completed succesfully, the I915_WEDGE bit is
- * set meaning that hardware is terminally sour and there is no
- * recovery. All waiters on the reset_queue will be woken when
- * that happens.
- *
- * This counter is used by the wait_seqno code to notice that reset
- * event happened and it needs to restart the entire ioctl (since most
- * likely the seqno it waited for won't ever signal anytime soon).
- *
- * This is important for lock-free wait paths, where no contended lock
- * naturally enforces the correct ordering between the bail-out of the
- * waiter and the gpu reset work code.
- */
- unsigned long reset_count;
-
- /**
- * flags: Control various stages of the GPU reset
- *
- * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
- * other users acquiring the struct_mutex. To do this we set the
- * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
- * and then check for that bit before acquiring the struct_mutex (in
- * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
- * secondary role in preventing two concurrent global reset attempts.
- *
- * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
- * struct_mutex. We try to acquire the struct_mutex in the reset worker,
- * but it may be held by some long running waiter (that we cannot
- * interrupt without causing trouble). Once we are ready to do the GPU
- * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
- * they already hold the struct_mutex and want to participate they can
- * inspect the bit and do the reset directly, otherwise the worker
- * waits for the struct_mutex.
- *
- * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
- * acquire the struct_mutex to reset an engine, we need an explicit
- * flag to prevent two concurrent reset attempts in the same engine.
- * As the number of engines continues to grow, allocate the flags from
- * the most significant bits.
- *
- * #I915_WEDGED - If reset fails and we can no longer use the GPU,
- * we set the #I915_WEDGED bit. Prior to command submission, e.g.
- * i915_request_alloc(), this bit is checked and the sequence
- * aborted (with -EIO reported to userspace) if set.
- */
- unsigned long flags;
-#define I915_RESET_BACKOFF 0
-#define I915_RESET_HANDOFF 1
-#define I915_RESET_MODESET 2
-#define I915_WEDGED (BITS_PER_LONG - 1)
-#define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES)
-
- /** Number of times an engine has been reset */
- u32 reset_engine_count[I915_NUM_ENGINES];
-
- /**
- * Waitqueue to signal when a hang is detected. Used to for waiters
- * to release the struct_mutex for the reset to procede.
- */
- wait_queue_head_t wait_queue;
-
- /**
- * Waitqueue to signal when the reset has completed. Used by clients
- * that wait for dev_priv->mm.wedged to settle.
- */
- wait_queue_head_t reset_queue;
-
- /* For missed irq/seqno simulation. */
- unsigned long test_irq_rings;
-};
-
enum modeset_restore {
MODESET_ON_LID_OPEN,
MODESET_DONE,
@@ -3589,64 +3317,6 @@ static inline int i915_debugfs_connector_add(struct drm_connector *connector)
static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
#endif
-/* i915_gpu_error.c */
-#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
-
-__printf(2, 3)
-void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
-int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
- const struct i915_gpu_state *gpu);
-int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
- struct drm_i915_private *i915,
- size_t count, loff_t pos);
-static inline void i915_error_state_buf_release(
- struct drm_i915_error_state_buf *eb)
-{
- kfree(eb->buf);
-}
-
-struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
-void i915_capture_error_state(struct drm_i915_private *dev_priv,
- u32 engine_mask,
- const char *error_msg);
-
-static inline struct i915_gpu_state *
-i915_gpu_state_get(struct i915_gpu_state *gpu)
-{
- kref_get(&gpu->ref);
- return gpu;
-}
-
-void __i915_gpu_state_free(struct kref *kref);
-static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
-{
- if (gpu)
- kref_put(&gpu->ref, __i915_gpu_state_free);
-}
-
-struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
-void i915_reset_error_state(struct drm_i915_private *i915);
-
-#else
-
-static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
- u32 engine_mask,
- const char *error_msg)
-{
-}
-
-static inline struct i915_gpu_state *
-i915_first_error_state(struct drm_i915_private *i915)
-{
- return NULL;
-}
-
-static inline void i915_reset_error_state(struct drm_i915_private *i915)
-{
-}
-
-#endif
-
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
/* i915_cmd_parser.c */
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 9e5e954..9b3bf45 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -32,6 +32,7 @@
#include <linux/zlib.h>
#include <drm/drm_print.h>
+#include "i915_gpu_error.h"
#include "i915_drv.h"
static inline const struct intel_engine_cs *
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
new file mode 100644
index 0000000..840318b
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -0,0 +1,355 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2008-2018 Intel Corporation
+ */
+
+#ifndef _I915_GPU_ERROR_H_
+#define _I915_GPU_ERROR_H_
+
+#include <linux/kref.h>
+#include <linux/ktime.h>
+#include <linux/sched.h>
+
+#include <drm/drm_mm.h>
+
+#include "intel_device_info.h"
+#include "intel_ringbuffer.h"
+#include "intel_uc_fw.h"
+
+#include "i915_gem.h"
+#include "i915_gem_gtt.h"
+#include "i915_params.h"
+
+struct drm_i915_private;
+struct intel_overlay_error_state;
+struct intel_display_error_state;
+
+struct i915_gpu_state {
+ struct kref ref;
+ ktime_t time;
+ ktime_t boottime;
+ ktime_t uptime;
+
+ struct drm_i915_private *i915;
+
+ char error_msg[128];
+ bool simulated;
+ bool awake;
+ bool wakelock;
+ bool suspended;
+ int iommu;
+ u32 reset_count;
+ u32 suspend_count;
+ struct intel_device_info device_info;
+ struct intel_driver_caps driver_caps;
+ struct i915_params params;
+
+ struct i915_error_uc {
+ struct intel_uc_fw guc_fw;
+ struct intel_uc_fw huc_fw;
+ struct drm_i915_error_object *guc_log;
+ } uc;
+
+ /* Generic register state */
+ u32 eir;
+ u32 pgtbl_er;
+ u32 ier;
+ u32 gtier[4], ngtier;
+ u32 ccid;
+ u32 derrmr;
+ u32 forcewake;
+ u32 error; /* gen6+ */
+ u32 err_int; /* gen7 */
+ u32 fault_data0; /* gen8, gen9 */
+ u32 fault_data1; /* gen8, gen9 */
+ u32 done_reg;
+ u32 gac_eco;
+ u32 gam_ecochk;
+ u32 gab_ctl;
+ u32 gfx_mode;
+
+ u32 nfence;
+ u64 fence[I915_MAX_NUM_FENCES];
+ struct intel_overlay_error_state *overlay;
+ struct intel_display_error_state *display;
+
+ struct drm_i915_error_engine {
+ int engine_id;
+ /* Software tracked state */
+ bool idle;
+ bool waiting;
+ int num_waiters;
+ unsigned long hangcheck_timestamp;
+ bool hangcheck_stalled;
+ enum intel_engine_hangcheck_action hangcheck_action;
+ struct i915_address_space *vm;
+ int num_requests;
+ u32 reset_count;
+
+ /* position of active request inside the ring */
+ u32 rq_head, rq_post, rq_tail;
+
+ /* our own tracking of ring head and tail */
+ u32 cpu_ring_head;
+ u32 cpu_ring_tail;
+
+ u32 last_seqno;
+
+ /* Register state */
+ u32 start;
+ u32 tail;
+ u32 head;
+ u32 ctl;
+ u32 mode;
+ u32 hws;
+ u32 ipeir;
+ u32 ipehr;
+ u32 bbstate;
+ u32 instpm;
+ u32 instps;
+ u32 seqno;
+ u64 bbaddr;
+ u64 acthd;
+ u32 fault_reg;
+ u64 faddr;
+ u32 rc_psmi; /* sleep state */
+ u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
+ struct intel_instdone instdone;
+
+ struct drm_i915_error_context {
+ char comm[TASK_COMM_LEN];
+ pid_t pid;
+ u32 handle;
+ u32 hw_id;
+ int priority;
+ int ban_score;
+ int active;
+ int guilty;
+ bool bannable;
+ } context;
+
+ struct drm_i915_error_object {
+ u64 gtt_offset;
+ u64 gtt_size;
+ int page_count;
+ int unused;
+ u32 *pages[0];
+ } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
+
+ struct drm_i915_error_object **user_bo;
+ long user_bo_count;
+
+ struct drm_i915_error_object *wa_ctx;
+ struct drm_i915_error_object *default_state;
+
+ struct drm_i915_error_request {
+ long jiffies;
+ pid_t pid;
+ u32 context;
+ int priority;
+ int ban_score;
+ u32 seqno;
+ u32 head;
+ u32 tail;
+ } *requests, execlist[EXECLIST_MAX_PORTS];
+ unsigned int num_ports;
+
+ struct drm_i915_error_waiter {
+ char comm[TASK_COMM_LEN];
+ pid_t pid;
+ u32 seqno;
+ } *waiters;
+
+ struct {
+ u32 gfx_mode;
+ union {
+ u64 pdp[4];
+ u32 pp_dir_base;
+ };
+ } vm_info;
+ } engine[I915_NUM_ENGINES];
+
+ struct drm_i915_error_buffer {
+ u32 size;
+ u32 name;
+ u32 rseqno[I915_NUM_ENGINES], wseqno;
+ u64 gtt_offset;
+ u32 read_domains;
+ u32 write_domain;
+ s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
+ u32 tiling:2;
+ u32 dirty:1;
+ u32 purgeable:1;
+ u32 userptr:1;
+ s32 engine:4;
+ u32 cache_level:3;
+ } *active_bo[I915_NUM_ENGINES], *pinned_bo;
+ u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
+ struct i915_address_space *active_vm[I915_NUM_ENGINES];
+};
+
+struct i915_gpu_error {
+ /* For hangcheck timer */
+#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
+#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
+
+ struct delayed_work hangcheck_work;
+
+ /* For reset and error_state handling. */
+ spinlock_t lock;
+ /* Protected by the above dev->gpu_error.lock. */
+ struct i915_gpu_state *first_error;
+
+ atomic_t pending_fb_pin;
+
+ unsigned long missed_irq_rings;
+
+ /**
+ * State variable controlling the reset flow and count
+ *
+ * This is a counter which gets incremented when reset is triggered,
+ *
+ * Before the reset commences, the I915_RESET_BACKOFF bit is set
+ * meaning that any waiters holding onto the struct_mutex should
+ * relinquish the lock immediately in order for the reset to start.
+ *
+ * If reset is not completed successfully, the I915_WEDGE bit is
+ * set meaning that hardware is terminally sour and there is no
+ * recovery. All waiters on the reset_queue will be woken when
+ * that happens.
+ *
+ * This counter is used by the wait_seqno code to notice that reset
+ * event happened and it needs to restart the entire ioctl (since most
+ * likely the seqno it waited for won't ever signal anytime soon).
+ *
+ * This is important for lock-free wait paths, where no contended lock
+ * naturally enforces the correct ordering between the bail-out of the
+ * waiter and the gpu reset work code.
+ */
+ unsigned long reset_count;
+
+ /**
+ * flags: Control various stages of the GPU reset
+ *
+ * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
+ * other users acquiring the struct_mutex. To do this we set the
+ * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
+ * and then check for that bit before acquiring the struct_mutex (in
+ * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
+ * secondary role in preventing two concurrent global reset attempts.
+ *
+ * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
+ * struct_mutex. We try to acquire the struct_mutex in the reset worker,
+ * but it may be held by some long running waiter (that we cannot
+ * interrupt without causing trouble). Once we are ready to do the GPU
+ * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
+ * they already hold the struct_mutex and want to participate they can
+ * inspect the bit and do the reset directly, otherwise the worker
+ * waits for the struct_mutex.
+ *
+ * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
+ * acquire the struct_mutex to reset an engine, we need an explicit
+ * flag to prevent two concurrent reset attempts in the same engine.
+ * As the number of engines continues to grow, allocate the flags from
+ * the most significant bits.
+ *
+ * #I915_WEDGED - If reset fails and we can no longer use the GPU,
+ * we set the #I915_WEDGED bit. Prior to command submission, e.g.
+ * i915_request_alloc(), this bit is checked and the sequence
+ * aborted (with -EIO reported to userspace) if set.
+ */
+ unsigned long flags;
+#define I915_RESET_BACKOFF 0
+#define I915_RESET_HANDOFF 1
+#define I915_RESET_MODESET 2
+#define I915_WEDGED (BITS_PER_LONG - 1)
+#define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES)
+
+ /** Number of times an engine has been reset */
+ u32 reset_engine_count[I915_NUM_ENGINES];
+
+ /**
+ * Waitqueue to signal when a hang is detected. Used to for waiters
+ * to release the struct_mutex for the reset to procede.
+ */
+ wait_queue_head_t wait_queue;
+
+ /**
+ * Waitqueue to signal when the reset has completed. Used by clients
+ * that wait for dev_priv->mm.wedged to settle.
+ */
+ wait_queue_head_t reset_queue;
+
+ /* For missed irq/seqno simulation. */
+ unsigned long test_irq_rings;
+};
+
+struct drm_i915_error_state_buf {
+ struct drm_i915_private *i915;
+ unsigned int bytes;
+ unsigned int size;
+ int err;
+ u8 *buf;
+ loff_t start;
+ loff_t pos;
+};
+
+#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
+
+__printf(2, 3)
+void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
+int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
+ const struct i915_gpu_state *gpu);
+int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
+ struct drm_i915_private *i915,
+ size_t count, loff_t pos);
+static inline void i915_error_state_buf_release(
+ struct drm_i915_error_state_buf *eb)
+{
+ kfree(eb->buf);
+}
+
+struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
+void i915_capture_error_state(struct drm_i915_private *dev_priv,
+ u32 engine_mask,
+ const char *error_msg);
+
+static inline struct i915_gpu_state *
+i915_gpu_state_get(struct i915_gpu_state *gpu)
+{
+ kref_get(&gpu->ref);
+ return gpu;
+}
+
+void __i915_gpu_state_free(struct kref *kref);
+static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
+{
+ if (gpu)
+ kref_put(&gpu->ref, __i915_gpu_state_free);
+}
+
+struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
+void i915_reset_error_state(struct drm_i915_private *i915);
+
+#else
+
+static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
+ u32 engine_mask,
+ const char *error_msg)
+{
+}
+
+static inline struct i915_gpu_state *
+i915_first_error_state(struct drm_i915_private *i915)
+{
+ return NULL;
+}
+
+static inline void i915_reset_error_state(struct drm_i915_private *i915)
+{
+}
+
+#endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
+
+#endif /* _I915_GPU_ERROR_H_ */
--
1.9.1
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND)
2018-03-08 9:50 [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND) Michal Wajdeczko
` (3 preceding siblings ...)
2018-03-08 9:50 ` [PATCH v2 4/4] drm/i915: Move i915_gpu_error into its own header Michal Wajdeczko
@ 2018-03-08 12:11 ` Chris Wilson
2018-03-08 12:20 ` Jani Nikula
2018-03-09 17:18 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-03-09 22:12 ` ✗ Fi.CI.IGT: failure " Patchwork
6 siblings, 1 reply; 13+ messages in thread
From: Chris Wilson @ 2018-03-08 12:11 UTC (permalink / raw)
To: Michal Wajdeczko, intel-gfx
Quoting Michal Wajdeczko (2018-03-08 09:50:33)
> This is a resend, to make patchwork happy.
> All patches already been reviewed.
It's still being ignored. :(
-Chris
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND)
2018-03-08 12:11 ` [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND) Chris Wilson
@ 2018-03-08 12:20 ` Jani Nikula
2018-03-08 12:58 ` Petri Latvala
0 siblings, 1 reply; 13+ messages in thread
From: Jani Nikula @ 2018-03-08 12:20 UTC (permalink / raw)
To: Chris Wilson, Michal Wajdeczko, intel-gfx; +Cc: Sarvela, Tomi P
On Thu, 08 Mar 2018, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> Quoting Michal Wajdeczko (2018-03-08 09:50:33)
>> This is a resend, to make patchwork happy.
>> All patches already been reviewed.
>
> It's still being ignored. :(
At least patchwork detected this as a series [1], often that's the
problem.
I tried to start testing manually from patchwork, it gives me "failed!".
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/39589/
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND)
2018-03-08 12:20 ` Jani Nikula
@ 2018-03-08 12:58 ` Petri Latvala
2018-03-08 15:22 ` Michal Wajdeczko
0 siblings, 1 reply; 13+ messages in thread
From: Petri Latvala @ 2018-03-08 12:58 UTC (permalink / raw)
To: Jani Nikula; +Cc: Sarvela, Tomi P, intel-gfx
On Thu, Mar 08, 2018 at 02:20:41PM +0200, Jani Nikula wrote:
> On Thu, 08 Mar 2018, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > Quoting Michal Wajdeczko (2018-03-08 09:50:33)
> >> This is a resend, to make patchwork happy.
> >> All patches already been reviewed.
> >
> > It's still being ignored. :(
>
> At least patchwork detected this as a series [1], often that's the
> problem.
Patchwork is not seeing patch 4/4, and due to its weird logic, it's
still waiting for it instead of considering the series "incomplete".
Looking at the series page, it doesn't even have a revision number.
This causes the pw REST api to show the series as one with 0 patches
when listing series, there's no series-new-revision event (CI is
watching that), and it also causes the below:
> I tried to start testing manually from patchwork, it gives me "failed!".
Arek checked the logs and patch 4/4 hasn't been received by pw at
all. Maybe it's still on the way, who knows.
--
Petri Latvala
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND)
2018-03-08 12:58 ` Petri Latvala
@ 2018-03-08 15:22 ` Michal Wajdeczko
2018-03-09 16:16 ` Arkadiusz Hiler
0 siblings, 1 reply; 13+ messages in thread
From: Michal Wajdeczko @ 2018-03-08 15:22 UTC (permalink / raw)
To: Jani Nikula, Petri Latvala; +Cc: Sarvela, Tomi P, intel-gfx
On Thu, 08 Mar 2018 13:58:48 +0100, Petri Latvala
<petri.latvala@intel.com> wrote:
> On Thu, Mar 08, 2018 at 02:20:41PM +0200, Jani Nikula wrote:
>> On Thu, 08 Mar 2018, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>> > Quoting Michal Wajdeczko (2018-03-08 09:50:33)
>> >> This is a resend, to make patchwork happy.
>> >> All patches already been reviewed.
>> >
>> > It's still being ignored. :(
>>
>> At least patchwork detected this as a series [1], often that's the
>> problem.
>
>
> Patchwork is not seeing patch 4/4, and due to its weird logic, it's
> still waiting for it instead of considering the series "incomplete".
>
> Looking at the series page, it doesn't even have a revision number.
>
> This causes the pw REST api to show the series as one with 0 patches
> when listing series, there's no series-new-revision event (CI is
> watching that), and it also causes the below:
>
>> I tried to start testing manually from patchwork, it gives me "failed!".
>
>
> Arek checked the logs and patch 4/4 hasn't been received by pw at
> all. Maybe it's still on the way, who knows.
>
I'm not sure if this is related, but list archive decided to assign
patch 1/4 [1] to old series [2] instead new one [3]
[1] https://lists.freedesktop.org/archives/intel-gfx/2018-March/158080.html
[2]
https://lists.freedesktop.org/archives/intel-gfx/2018-March/thread.html#157974
[3]
https://lists.freedesktop.org/archives/intel-gfx/2018-March/thread.html#158081
ps. patch 4/4 is already in archive [4]
[4] https://lists.freedesktop.org/archives/intel-gfx/2018-March/158082.html
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND)
2018-03-08 15:22 ` Michal Wajdeczko
@ 2018-03-09 16:16 ` Arkadiusz Hiler
0 siblings, 0 replies; 13+ messages in thread
From: Arkadiusz Hiler @ 2018-03-09 16:16 UTC (permalink / raw)
To: Michal Wajdeczko; +Cc: Sarvela, Tomi P, intel-gfx
On Thu, Mar 08, 2018 at 04:22:55PM +0100, Michal Wajdeczko wrote:
> On Thu, 08 Mar 2018 13:58:48 +0100, Petri Latvala <petri.latvala@intel.com>
> wrote:
>
> > On Thu, Mar 08, 2018 at 02:20:41PM +0200, Jani Nikula wrote:
> > > On Thu, 08 Mar 2018, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > > > Quoting Michal Wajdeczko (2018-03-08 09:50:33)
> > > >> This is a resend, to make patchwork happy.
> > > >> All patches already been reviewed.
> > > >
> > > > It's still being ignored. :(
> > >
> > > At least patchwork detected this as a series [1], often that's the
> > > problem.
> >
> >
> > Patchwork is not seeing patch 4/4, and due to its weird logic, it's
> > still waiting for it instead of considering the series "incomplete".
> >
> > Looking at the series page, it doesn't even have a revision number.
> >
> > This causes the pw REST api to show the series as one with 0 patches
> > when listing series, there's no series-new-revision event (CI is
> > watching that), and it also causes the below:
> >
> > > I tried to start testing manually from patchwork, it gives me "failed!".
> >
> >
> > Arek checked the logs and patch 4/4 hasn't been received by pw at
> > all. Maybe it's still on the way, who knows.
> >
>
> I'm not sure if this is related, but list archive decided to assign
> patch 1/4 [1] to old series [2] instead new one [3]
>
> [1] https://lists.freedesktop.org/archives/intel-gfx/2018-March/158080.html
> [2] https://lists.freedesktop.org/archives/intel-gfx/2018-March/thread.html#157974
> [3] https://lists.freedesktop.org/archives/intel-gfx/2018-March/thread.html#158081
>
> ps. patch 4/4 is already in archive [4]
>
> [4] https://lists.freedesktop.org/archives/intel-gfx/2018-March/158082.html
The patch got lost in time and space and has never reached patchwork's
mail server.
I feed the patchwork with a copy of the mail manually. Expect results soon.
--
Cheers,
Arek
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^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: misc fixes in headers (RESEND)
2018-03-08 9:50 [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND) Michal Wajdeczko
` (4 preceding siblings ...)
2018-03-08 12:11 ` [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND) Chris Wilson
@ 2018-03-09 17:18 ` Patchwork
2018-03-09 22:12 ` ✗ Fi.CI.IGT: failure " Patchwork
6 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-03-09 17:18 UTC (permalink / raw)
To: Michal Wajdeczko; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: misc fixes in headers (RESEND)
URL : https://patchwork.freedesktop.org/series/39589/
State : success
== Summary ==
Series 39589v1 drm/i915: misc fixes in headers (RESEND)
https://patchwork.freedesktop.org/api/1.0/series/39589/revisions/1/mbox/
---- Known issues:
Test debugfs_test:
Subgroup read_all_entries:
incomplete -> PASS (fi-snb-2520m) fdo#103713
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
fail -> PASS (fi-gdg-551) fdo#102575
Test kms_chamelium:
Subgroup dp-edid-read:
pass -> FAIL (fi-kbl-7500u) fdo#102505
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#102505 https://bugs.freedesktop.org/show_bug.cgi?id=102505
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:424s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:426s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:370s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:509s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:281s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:490s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:493s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:481s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:469s
fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:405s
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:584s
fi-cnl-y3 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:592s
fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:422s
fi-gdg-551 total:288 pass:180 dwarn:0 dfail:0 fail:0 skip:108 time:290s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:520s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:397s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:411s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:457s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:422s
fi-kbl-7500u total:288 pass:262 dwarn:1 dfail:0 fail:1 skip:24 time:467s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:460s
fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:506s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:584s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:429s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:525s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:535s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:503s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:492s
fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:425s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:430s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:514s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:393s
Blacklisted hosts:
fi-cnl-drrs total:288 pass:257 dwarn:3 dfail:0 fail:0 skip:19 time:511s
2e2ef5a5221a7469ecd72c68ed15dd8b94e2e0c6 drm-tip: 2018y-03m-09d-14h-28m-10s UTC integration manifest
2b518e87976b drm/i915: Move i915_gpu_error into its own header
f2969e101bac drm/i915: Make header i915_pmu.h more robust
87481ecfb862 drm/i915: Change parameters order in i915_gem_batch_pool_init
c055bfc9c223 drm/i915: Include i915_reg.h in intel_ringbuffer.h
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8294/issues.html
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^ permalink raw reply [flat|nested] 13+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915: misc fixes in headers (RESEND)
2018-03-08 9:50 [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND) Michal Wajdeczko
` (5 preceding siblings ...)
2018-03-09 17:18 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2018-03-09 22:12 ` Patchwork
2018-03-09 22:22 ` Chris Wilson
6 siblings, 1 reply; 13+ messages in thread
From: Patchwork @ 2018-03-09 22:12 UTC (permalink / raw)
To: Michal Wajdeczko; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: misc fixes in headers (RESEND)
URL : https://patchwork.freedesktop.org/series/39589/
State : failure
== Summary ==
---- Possible new issues:
Test kms_cursor_legacy:
Subgroup short-flip-after-cursor-atomic-transitions:
pass -> FAIL (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-rgb101010-draw-pwrite:
pass -> FAIL (shard-apl)
---- Known issues:
Test gem_eio:
Subgroup in-flight:
incomplete -> PASS (shard-apl) fdo#105341
Test kms_cursor_crc:
Subgroup cursor-128x128-suspend:
skip -> PASS (shard-hsw) fdo#103540
Test kms_flip:
Subgroup 2x-modeset-vs-vblank-race:
pass -> DMESG-WARN (shard-hsw) fdo#103060
Subgroup plain-flip-ts-check-interruptible:
fail -> PASS (shard-hsw) fdo#100368
Test pm_lpsp:
Subgroup screens-disabled:
pass -> FAIL (shard-hsw) fdo#104941
fdo#105341 https://bugs.freedesktop.org/show_bug.cgi?id=105341
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#104941 https://bugs.freedesktop.org/show_bug.cgi?id=104941
shard-apl total:3398 pass:1792 dwarn:1 dfail:0 fail:8 skip:1596 time:11758s
shard-hsw total:3467 pass:1770 dwarn:2 dfail:0 fail:3 skip:1691 time:11639s
shard-snb total:3467 pass:1365 dwarn:1 dfail:0 fail:1 skip:2100 time:6999s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8294/shards.html
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: ✗ Fi.CI.IGT: failure for drm/i915: misc fixes in headers (RESEND)
2018-03-09 22:12 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-03-09 22:22 ` Chris Wilson
0 siblings, 0 replies; 13+ messages in thread
From: Chris Wilson @ 2018-03-09 22:22 UTC (permalink / raw)
To: Patchwork, Michal Wajdeczko; +Cc: intel-gfx
Quoting Patchwork (2018-03-09 22:12:20)
> == Series Details ==
>
> Series: drm/i915: misc fixes in headers (RESEND)
> URL : https://patchwork.freedesktop.org/series/39589/
> State : failure
>
> == Summary ==
>
> ---- Possible new issues:
>
> Test kms_cursor_legacy:
> Subgroup short-flip-after-cursor-atomic-transitions:
> pass -> FAIL (shard-hsw)
> Test kms_frontbuffer_tracking:
> Subgroup fbc-rgb101010-draw-pwrite:
> pass -> FAIL (shard-apl)
>
> ---- Known issues:
>
> Test gem_eio:
> Subgroup in-flight:
> incomplete -> PASS (shard-apl) fdo#105341
> Test kms_cursor_crc:
> Subgroup cursor-128x128-suspend:
> skip -> PASS (shard-hsw) fdo#103540
> Test kms_flip:
> Subgroup 2x-modeset-vs-vblank-race:
> pass -> DMESG-WARN (shard-hsw) fdo#103060
> Subgroup plain-flip-ts-check-interruptible:
> fail -> PASS (shard-hsw) fdo#100368
> Test pm_lpsp:
> Subgroup screens-disabled:
> pass -> FAIL (shard-hsw) fdo#104941
>
> fdo#105341 https://bugs.freedesktop.org/show_bug.cgi?id=105341
> fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
> fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
> fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
> fdo#104941 https://bugs.freedesktop.org/show_bug.cgi?id=104941
>
> shard-apl total:3398 pass:1792 dwarn:1 dfail:0 fail:8 skip:1596 time:11758s
> shard-hsw total:3467 pass:1770 dwarn:2 dfail:0 fail:3 skip:1691 time:11639s
> shard-snb total:3467 pass:1365 dwarn:1 dfail:0 fail:1 skip:2100 time:6999s
As pw is finally happy, pushed. Thanks for the cleanup,
-Chris
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^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2018-03-09 22:22 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-03-08 9:50 [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND) Michal Wajdeczko
2018-03-08 9:50 ` [PATCH v2 1/4] drm/i915: Include i915_reg.h in intel_ringbuffer.h Michal Wajdeczko
2018-03-08 9:50 ` [PATCH v2 2/4] drm/i915: Change parameters order in i915_gem_batch_pool_init Michal Wajdeczko
2018-03-08 9:50 ` [PATCH v2 3/4] drm/i915: Make header i915_pmu.h more robust Michal Wajdeczko
2018-03-08 9:50 ` [PATCH v2 4/4] drm/i915: Move i915_gpu_error into its own header Michal Wajdeczko
2018-03-08 12:11 ` [PATCH v2 0/4] drm/i915: misc fixes in headers (RESEND) Chris Wilson
2018-03-08 12:20 ` Jani Nikula
2018-03-08 12:58 ` Petri Latvala
2018-03-08 15:22 ` Michal Wajdeczko
2018-03-09 16:16 ` Arkadiusz Hiler
2018-03-09 17:18 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-03-09 22:12 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-03-09 22:22 ` Chris Wilson
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