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From: Niklas Cassel <niklas.cassel@axis.com>
To: kishon@ti.com, Jingoo Han <jingoohan1@gmail.com>,
	Joao Pinto <Joao.Pinto@synopsys.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>
Cc: Niklas Cassel <niklass@axis.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v4 3/5] PCI: designware-ep: Make dw_pcie_ep_reset_bar() handle 64-bit BARs properly
Date: Thu,  8 Mar 2018 14:33:28 +0100	[thread overview]
Message-ID: <20180308133331.19464-4-niklas.cassel@axis.com> (raw)
In-Reply-To: <20180308133331.19464-1-niklas.cassel@axis.com>

Since a 64-bit BAR consists of a BAR pair, we need to write to both
BARs in the BAR pair to clear the BAR properly.

Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
---
 drivers/pci/dwc/pcie-designware-ep.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
index 946bbdf53c4d..b20b2651caf9 100644
--- a/drivers/pci/dwc/pcie-designware-ep.c
+++ b/drivers/pci/dwc/pcie-designware-ep.c
@@ -22,11 +22,18 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
 void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
 {
 	u32 reg;
+	u32 val;
 
 	reg = PCI_BASE_ADDRESS_0 + (4 * bar);
+	val = dw_pcie_readl_dbi(pci, reg);
 	dw_pcie_dbi_ro_wr_en(pci);
 	dw_pcie_writel_dbi2(pci, reg, 0x0);
 	dw_pcie_writel_dbi(pci, reg, 0x0);
+	if (!(val & PCI_BASE_ADDRESS_SPACE_IO) &&
+	    (val & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
+		dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
+		dw_pcie_writel_dbi(pci, reg + 4, 0x0);
+	}
 	dw_pcie_dbi_ro_wr_dis(pci);
 }
 
-- 
2.14.2

  parent reply	other threads:[~2018-03-08 13:33 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-08 13:33 [PATCH v4 0/5] PCI endpoint 64-bit BAR fixes Niklas Cassel
2018-03-08 13:33 ` [PATCH v4 1/5] PCI: endpoint: BAR width should not depend on sizeof dma_addr_t Niklas Cassel
2018-03-16 18:02   ` Lorenzo Pieralisi
2018-03-17  0:55     ` Niklas Cassel
2018-03-19 12:36       ` Lorenzo Pieralisi
2018-03-21  5:29   ` Kishon Vijay Abraham I
2018-03-08 13:33 ` [PATCH v4 2/5] PCI: designware-ep: Make dw_pcie_ep_set_bar() handle 64-bit BARs properly Niklas Cassel
2018-03-21  5:49   ` Kishon Vijay Abraham I
2018-03-08 13:33 ` Niklas Cassel [this message]
2018-03-21  5:54   ` [PATCH v4 3/5] PCI: designware-ep: Make dw_pcie_ep_reset_bar() " Kishon Vijay Abraham I
2018-03-08 13:33 ` [PATCH v4 4/5] PCI: endpoint: Make pci_epc_set_bar() return the BAR width that was set-up Niklas Cassel
2018-03-21  6:06   ` Kishon Vijay Abraham I
2018-03-08 13:33 ` [PATCH v4 5/5] misc: pci_endpoint_test: Handle 64-bit BARs properly Niklas Cassel
2018-03-15 13:22   ` Greg Kroah-Hartman
2018-03-16 12:55     ` Niklas Cassel
2018-03-21  3:59   ` Niklas Cassel
2018-03-21  9:22     ` Greg Kroah-Hartman
2018-03-21  5:55   ` Kishon Vijay Abraham I
2018-03-19 16:52 ` [PATCH v4 0/5] PCI endpoint 64-bit BAR fixes Lorenzo Pieralisi
2018-03-21  4:10   ` Niklas Cassel

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