From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752031AbeCZUKs (ORCPT ); Mon, 26 Mar 2018 16:10:48 -0400 Received: from mail.skyhub.de ([5.9.137.197]:38318 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750983AbeCZUKq (ORCPT ); Mon, 26 Mar 2018 16:10:46 -0400 Date: Mon, 26 Mar 2018 22:09:55 +0200 From: Borislav Petkov To: "Ghannam, Yazen" Cc: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "tony.luck@intel.com" , "x86@kernel.org" Subject: Re: [PATCH 2/2] x86/MCE: Always save MCA_{ADDR,MISC,SYND} register contents Message-ID: <20180326200955.GG28372@pd.tnic> References: <20180326191526.64314-1-Yazen.Ghannam@amd.com> <20180326191526.64314-2-Yazen.Ghannam@amd.com> <20180326193526.GK25548@pd.tnic> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.3 (2018-01-21) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 26, 2018 at 08:05:37PM +0000, Ghannam, Yazen wrote: > Sure, I can do that. But I didn't think it was necessary because it doesn't hurt > to read the registers whether or not the valid bits are set. No, this needs to be AMD-specific because it will confuse people using Intel machines. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply. From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [2/2] x86/MCE: Always save MCA_{ADDR,MISC,SYND} register contents From: Borislav Petkov Message-Id: <20180326200955.GG28372@pd.tnic> Date: Mon, 26 Mar 2018 22:09:55 +0200 To: "Ghannam, Yazen" Cc: "linux-edac@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "tony.luck@intel.com" , "x86@kernel.org" List-ID: T24gTW9uLCBNYXIgMjYsIDIwMTggYXQgMDg6MDU6MzdQTSArMDAwMCwgR2hhbm5hbSwgWWF6ZW4g d3JvdGU6Cj4gU3VyZSwgSSBjYW4gZG8gdGhhdC4gQnV0IEkgZGlkbid0IHRoaW5rIGl0IHdhcyBu ZWNlc3NhcnkgYmVjYXVzZSBpdCBkb2Vzbid0IGh1cnQKPiB0byByZWFkIHRoZSByZWdpc3RlcnMg d2hldGhlciBvciBub3QgdGhlIHZhbGlkIGJpdHMgYXJlIHNldC4KCk5vLCB0aGlzIG5lZWRzIHRv IGJlIEFNRC1zcGVjaWZpYyBiZWNhdXNlIGl0IHdpbGwgY29uZnVzZSBwZW9wbGUgdXNpbmcKSW50 ZWwgbWFjaGluZXMuCg==