From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com ([192.55.52.93]:40105 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752609AbeDBQT4 (ORCPT ); Mon, 2 Apr 2018 12:19:56 -0400 From: Keith Busch To: Linux PCI , Bjorn Helgaas Cc: Oza Pawandeep , Sinan Kaya , Keith Busch Subject: [PATCHv2 1/7] PCI/DPC: Enable ERR_COR Date: Mon, 2 Apr 2018 10:21:57 -0600 Message-Id: <20180402162203.3370-2-keith.busch@intel.com> In-Reply-To: <20180402162203.3370-1-keith.busch@intel.com> References: <20180402162203.3370-1-keith.busch@intel.com> Sender: linux-pci-owner@vger.kernel.org List-ID: A DPC port may be configured to send ERR_COR message when the triggered. This patch enables this feature so additional notification of the event is possible. Signed-off-by: Keith Busch --- drivers/pci/pcie/pcie-dpc.c | 5 ++++- include/uapi/linux/pci_regs.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pcie/pcie-dpc.c b/drivers/pci/pcie/pcie-dpc.c index 38e40c6c576f..a9be6938417f 100644 --- a/drivers/pci/pcie/pcie-dpc.c +++ b/drivers/pci/pcie/pcie-dpc.c @@ -269,7 +269,10 @@ static int dpc_probe(struct pcie_device *dev) } } - ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN; + ctl = (ctl & 0xfff4) | + PCI_EXP_DPC_CTL_EN_NONFATAL | + PCI_EXP_DPC_CTL_INT_EN | + PCI_EXP_DPC_CTL_ERR_COR; pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl); dev_info(device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n", diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 0c79eac5e9b8..9cfcecdc3ec7 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -980,6 +980,7 @@ #define PCI_EXP_DPC_CTL 6 /* DPC control */ #define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */ #define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */ +#define PCI_EXP_DPC_CTL_ERR_COR 0x0010 /* DPC ERR_COR Enable */ #define PCI_EXP_DPC_STATUS 8 /* DPC Status */ #define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */ -- 2.14.3