From mboxrd@z Thu Jan  1 00:00:00 1970
From: Olivier Matz <olivier.matz@6wind.com>
Subject: Re: [PATCH] ring: relax alignment constraint on ring
 structure
Date: Tue, 3 Apr 2018 17:25:17 +0200
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References: <20170630142609.6180-1-olivier.matz@6wind.com>
 <20180403132644.23729-1-olivier.matz@6wind.com>
 <20180403150722.GB15937@jerin>
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To: Jerin Jacob <jerin.jacob@caviumnetworks.com>
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On Tue, Apr 03, 2018 at 08:37:23PM +0530, Jerin Jacob wrote:
> -----Original Message-----
> > Date: Tue, 3 Apr 2018 15:26:44 +0200
> > From: Olivier Matz <olivier.matz@6wind.com>
> > To: dev@dpdk.org
> > Subject: [dpdk-dev] [PATCH] ring: relax alignment constraint on ring
> >  structure
> > X-Mailer: git-send-email 2.11.0
> > 
> > The initial objective of
> > commit d9f0d3a1ffd4 ("ring: remove split cacheline build setting")
> > was to add an empty cache line betwee, the producer and consumer
> > data (on platform with cache line size = 64B), preventing from
> > having them on adjacent cache lines.
> > 
> > Following discussion on the mailing list, it appears that this
> > also imposes an alignment constraint that is not required.
> > 
> > This patch removes the extra alignment constraint and adds the
> > empty cache lines using padding fields in the structure. The
> > size of rte_ring structure and the offset of the fields remain
> > the same on platforms with cache line size = 64B:
> > 
> >   rte_ring = 384
> >   rte_ring.name = 0
> >   rte_ring.flags = 32
> >   rte_ring.memzone = 40
> >   rte_ring.size = 48
> >   rte_ring.mask = 52
> >   rte_ring.prod = 128
> >   rte_ring.cons = 256
> > 
> > But it has an impact on platform where cache line size is 128B:
> > 
> >   rte_ring = 384        -> 768
> >   rte_ring.name = 0
> >   rte_ring.flags = 32
> >   rte_ring.memzone = 40
> >   rte_ring.size = 48
> >   rte_ring.mask = 52
> >   rte_ring.prod = 128   -> 256
> >   rte_ring.cons = 256   -> 512
> 
> Are we leaving TWO cacheline to make sure, HW prefetch don't load
> the adjust cacheline(consumer)?
> 
> If so, Will it have impact on those machine where it is 128B Cache line
> and the HW prefetcher is not loading the next caching explicitly. Right?

The impact on machines that have a 128B cache line is that an unused
cache line will be added between the producer and consumer data. I
expect that the impact is positive in case there is a hw prefetcher, and
null in case there is no such prefetcher.

On machines with 64B cache line, this was already the case. It just
reduces the alignment constraint.

Olivier