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Sun, 8 Apr 2018 20:31:25 -0400 From: Sasha Levin To: "stable@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: Paul Burton , "linux-mips@linux-mips.org" , Ralf Baechle , Sasha Levin Subject: [PATCH AUTOSEL for 4.9 171/293] MIPS: CPS: Handle spurious VP starts more gracefully Thread-Topic: [PATCH AUTOSEL for 4.9 171/293] MIPS: CPS: Handle spurious VP starts more gracefully Thread-Index: AQHTz5k2XxVssYY/NEKhyOL9pt1Zbw== Date: Mon, 9 Apr 2018 00:25:08 +0000 Message-ID: <20180409002239.163177-171-alexander.levin@microsoft.com> References: <20180409002239.163177-1-alexander.levin@microsoft.com> In-Reply-To: <20180409002239.163177-1-alexander.levin@microsoft.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [52.168.54.252] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;DM5PR2101MB0917;7:u7Y+4lOFnBLRwxnDJF5Vv/cB0jhF2zVGCoePqOm8EjiKK/1z6zPyJBKF+8bmBwUh0/iPFOq95bUyapG0THotYXFlGt2ORx/FYnLQJ6gbQ+K3xG1Qcmx4AWLLcjkGQxvLUAX95sqXTwuOJW671eZaEfsGOSRZCOOl6oa7+UXaURnR6zc+pKA+w0IMsGceCQZ1CAFxOnmaNHbOhZ3yJ9AD+tt45IMUeHUn19GzcN5RhaMHmt2yXKMGwqFeQNtPThq9;20:r09pQJy6ll4cNInjbef9PIEwibH6ExBOfoDXs6urXa8Ee/74XhQiekdoMg3+nJq+IhxqyT1mR1B37J1VS7gZNt8kWfU9icbmZkpC47YRtwXfMd8pgEAljLALqQ4/gMoCk3k0QHvjC3M/ClFE2jcj0l/I74wgi3Hdd0HypOFewBY= X-MS-Office365-Filtering-Correlation-Id: 8b1ed94f-c1de-4847-4d42-08d59db13623 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(7020095)(4652020)(4534165)(4627221)(201703031133081)(201702281549075)(5600026)(4604075)(3008032)(48565401081)(2017052603328)(7193020);SRVR:DM5PR2101MB0917; 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x-microsoft-antispam-message-info: G/856DcZFXkDvtzlR1XX8+XBbLVde0wxlTvYskO0Ax2UctFY+FM6pgfUR1I3526/ShZ9PN0yKJW+ViygTwZAR/b1UsVzNfGqQGe9LkBLfy5v/8n9ShdXqrjfFVuuw8LGbO8MuLHtXevqaFVigl8L4PzX7tqdxKZMlQXv2BWpAwYmykCC0I3jNssXH3iDxclMobYZdHtFE4U3zNWlaQPwtMVVkpf80ymmg7c9OquHTiSXKnnTDBFmzjBHo8e6E98uQJAtC93+LGsKJWF7Z7ok+jPTkCBzhVbAqwejX5Y380Uk7C6D79siFg2n0V9u7TEHTCg1eSMv3YFQiVbMG3PyeMQtoNPK3shcGQpbK5nKjwGf93KWa/vRnInxHJAs8iamxv501SqiJDTUvRSFJ0Jeb9kyLg6BJQmTvY5HwhD+D+w= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8b1ed94f-c1de-4847-4d42-08d59db13623 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2018 00:25:08.4251 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR2101MB0917 Sender: stable-owner@vger.kernel.org X-Mailing-List: stable@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: From: Paul Burton [ Upstream commit fa7a3b4a7217b40bf58c4f38e5ee573b43a8aa2f ] On pre-r6 systems with the MT ASE the CPS SMP code included checks to halt the VPE running mips_cps_boot_vpes() if its bit in the struct core_boot_config vpe_mask field is clear. This was largely done in order to allow us to start arbitrary VPEs within a core despite the fact that hardware is typically configured to run only VPE0 after powering up a core. VPE0 would start the desired other VPEs, halt itself, and the fact that VPE0 started would be largely hidden & irrelevant. In MIPSr6 multithreading we have control over which VPs start executing when a core powers up via the cores CPC registers accessed remotely through the redirect block. For this reason the MIPSr6 multithreading path in mips_cps_boot_vpes() hasn't bothered up until now to handle halting the VP running it. However it is possible to power up cores entirely in hardware by using a pwr_up pin associated with the core. Unfortunately some systems wire this pin to a logic 1, which means that it is possible for a core to power up at a point that software doesn't expect. The result is that we generally go execute the kernel on a CPU that ought not to be running & the results can be unpredictable. Handle this case by stopping VPs that we don't expect to be running in mips_cps_boot_vpes() - with this change even if a core powers up it will do nothing useful & all VPs within it will stop running before they proceed to run general kernel code & do any damage. Ideally we would produce some sort of warning here, but given the stage of core bringup this happens at that would be non-trivial. We also will only hit this if a core starts up after being offlined via hotplug, and when that happens we will already produce a warning that the CPU didn't power down in cps_cpu_die() which seems sufficient. Signed-off-by: Paul Burton Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16198/ Signed-off-by: Ralf Baechle Signed-off-by: Sasha Levin --- arch/mips/kernel/cps-vec.S | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index a00e87b0256d..b849fe6aad94 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -22,6 +22,7 @@ #define GCR_CL_COHERENCE_OFS 0x2008 #define GCR_CL_ID_OFS 0x2028 =20 +#define CPC_CL_VC_STOP_OFS 0x2020 #define CPC_CL_VC_RUN_OFS 0x2028 =20 .extern mips_cm_base @@ -376,8 +377,12 @@ LEAF(mips_cps_boot_vpes) PTR_LI t2, UNCAC_BASE PTR_ADD t1, t1, t2 =20 - /* Set VC_RUN to the VPE mask */ + /* Start any other VPs that ought to be running */ PTR_S ta2, CPC_CL_VC_RUN_OFS(t1) + + /* Ensure this VP stops running if it shouldn't be */ + not ta2 + PTR_S ta2, CPC_CL_VC_STOP_OFS(t1) ehb =20 #elif defined(CONFIG_MIPS_MT) --=20 2.15.1