From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [RFC,5/6] dmaengine: xilinx_dma: Program interrupt delay timeout From: Vinod Koul Message-Id: <20180411091159.GA6014@localhost> Date: Wed, 11 Apr 2018 14:41:59 +0530 To: Radhey Shyam Pandey Cc: dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, radheys@xilinx.com, lars@metafoo.de, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-ID: T24gTW9uLCBBcHIgMDIsIDIwMTggYXQgMDQ6MDk6MDVQTSArMDUzMCwgUmFkaGV5IFNoeWFtIFBh bmRleSB3cm90ZToKPiBQcm9ncmFtIElSUURlbGF5IGZvciBBWEkgRE1BLiBUaGUgaW50ZXJydXB0 IHRpbWVvdXQgbWVjaGFuaXNtIGNhdXNlcwo+IHRoZSBETUEgZW5naW5lIHRvIGdlbmVyYXRlIGFu IGludGVycnVwdCBhZnRlciB0aGUgZGVsYXkgdGltZSBwZXJpb2QKPiBoYXMgZXhwaXJlZC4gSXQg ZW5hYmxlcyBkbWFlbmdpbmUgdG8gcmVzcG9uZCBpbiByZWFsLXRpbWUgZXZlbiB0aG91Z2gKPiBp bnRlcnJ1cHQgY29hbGVzY2luZyBpcyBjb25maWd1cmVkLgoKYWdhaW4geW91IGFyZSBkb2luZyB0 aGlzIG9ubHkgZm9yIGF4aWV0aF9jb25uZWN0ZWQsIHdoeSBpcyB0aGF0PwoKPiAKPiBTaWduZWQt b2ZmLWJ5OiBSYWRoZXkgU2h5YW0gUGFuZGV5IDxyYWRoZXlzQHhpbGlueC5jb20+Cj4gLS0tCj4g IGRyaXZlcnMvZG1hL3hpbGlueC94aWxpbnhfZG1hLmMgfCAgIDE2ICsrKysrKysrKysrKysrLS0K PiAgMSBmaWxlcyBjaGFuZ2VkLCAxNCBpbnNlcnRpb25zKCspLCAyIGRlbGV0aW9ucygtKQo+IAo+ IGRpZmYgLS1naXQgYS9kcml2ZXJzL2RtYS94aWxpbngveGlsaW54X2RtYS5jIGIvZHJpdmVycy9k bWEveGlsaW54L3hpbGlueF9kbWEuYwo+IGluZGV4IDUxODQ2NWUuLmFiOGYxYjAgMTAwNjQ0Cj4g LS0tIGEvZHJpdmVycy9kbWEveGlsaW54L3hpbGlueF9kbWEuYwo+ICsrKyBiL2RyaXZlcnMvZG1h L3hpbGlueC94aWxpbnhfZG1hLmMKPiBAQCAtMTYxLDggKzE2MSwxMiBAQAo+ICAvKiBBWEkgRE1B IFNwZWNpZmljIE1hc2tzL0JpdCBmaWVsZHMgKi8KPiAgI2RlZmluZSBYSUxJTlhfRE1BX01BWF9U UkFOU19MRU4JR0VOTUFTSygyMiwgMCkKPiAgI2RlZmluZSBYSUxJTlhfRE1BX0NSX0NPQUxFU0NF X01BWAlHRU5NQVNLKDIzLCAxNikKPiArI2RlZmluZSBYSUxJTlhfRE1BX0NSX0RFTEFZX01BWAkJ R0VOTUFTSygzMSwgMjQpCj4gICNkZWZpbmUgWElMSU5YX0RNQV9DUl9DWUNMSUNfQkRfRU5fTUFT SwlCSVQoNCkKPiAgI2RlZmluZSBYSUxJTlhfRE1BX0NSX0NPQUxFU0NFX1NISUZUCTE2Cj4gKyNk ZWZpbmUgWElMSU5YX0RNQV9DUl9ERUxBWV9TSElGVAkyNAo+ICsjZGVmaW5lIFhJTElOWF9ETUFf Q1JfV0FJVEJPVU5EX0RGVAkyNTQKPiArCj4gICNkZWZpbmUgWElMSU5YX0RNQV9CRF9TT1AJCUJJ VCgyNykKPiAgI2RlZmluZSBYSUxJTlhfRE1BX0JEX0VPUAkJQklUKDI2KQo+ICAjZGVmaW5lIFhJ TElOWF9ETUFfQ09BTEVTQ0VfTUFYCQkyNTUKPiBAQCAtMTI5NCw2ICsxMjk4LDEyIEBAIHN0YXRp YyB2b2lkIHhpbGlueF9kbWFfc3RhcnRfdHJhbnNmZXIoc3RydWN0IHhpbGlueF9kbWFfY2hhbiAq Y2hhbikKPiAgCQlyZWcgJj0gflhJTElOWF9ETUFfQ1JfQ09BTEVTQ0VfTUFYOwo+ICAJCXJlZyB8 PSBjaGFuLT5kZXNjX3BlbmRpbmdjb3VudCA8PAo+ICAJCQkJICBYSUxJTlhfRE1BX0NSX0NPQUxF U0NFX1NISUZUOwo+ICsKPiArCQlpZiAoY2hhbi0+eGRldi0+aGFzX2F4aWV0aF9jb25uZWN0ZWQp IHsKPiArCQkJcmVnICAmPSB+WElMSU5YX0RNQV9DUl9ERUxBWV9NQVg7Cj4gKwkJCXJlZyAgfD0g WElMSU5YX0RNQV9DUl9XQUlUQk9VTkRfREZUIDw8Cj4gKwkJCQkJWElMSU5YX0RNQV9DUl9ERUxB WV9TSElGVDsKPiArCQl9Cj4gIAkJZG1hX2N0cmxfd3JpdGUoY2hhbiwgWElMSU5YX0RNQV9SRUdf RE1BQ1IsIHJlZyk7Cj4gIAl9Cj4gIAo+IEBAIC0xNTA4LDcgKzE1MTgsOCBAQCBzdGF0aWMgaXJx cmV0dXJuX3QgeGlsaW54X2RtYV9pcnFfaGFuZGxlcihpbnQgaXJxLCB2b2lkICpkYXRhKQo+ICAJ CX0KPiAgCX0KPiAgCj4gLQlpZiAoc3RhdHVzICYgWElMSU5YX0RNQV9ETUFTUl9ETFlfQ05UX0lS USkgewo+ICsJaWYgKCFjaGFuLT54ZGV2LT5oYXNfYXhpZXRoX2Nvbm5lY3RlZCAmJiAoc3RhdHVz ICYKPiArCQkJWElMSU5YX0RNQV9ETUFTUl9ETFlfQ05UX0lSUSkpIHsKPiAgCQkvKgo+ICAJCSAq IERldmljZSB0YWtlcyB0b28gbG9uZyB0byBkbyB0aGUgdHJhbnNmZXIgd2hlbiB1c2VyIHJlcXVp cmVzCj4gIAkJICogcmVzcG9uc2l2ZW5lc3MuCj4gQEAgLTE1MTYsNyArMTUyNyw4IEBAIHN0YXRp YyBpcnFyZXR1cm5fdCB4aWxpbnhfZG1hX2lycV9oYW5kbGVyKGludCBpcnEsIHZvaWQgKmRhdGEp Cj4gIAkJZGV2X2RiZyhjaGFuLT5kZXYsICJJbnRlci1wYWNrZXQgbGF0ZW5jeSB0b28gbG9uZ1xu Iik7Cj4gIAl9Cj4gIAo+IC0JaWYgKHN0YXR1cyAmIFhJTElOWF9ETUFfRE1BU1JfRlJNX0NOVF9J UlEpIHsKPiArCWlmIChzdGF0dXMgJiAoWElMSU5YX0RNQV9ETUFTUl9GUk1fQ05UX0lSUSB8Cj4g KwkJICAgICAgWElMSU5YX0RNQV9ETUFTUl9ETFlfQ05UX0lSUSkpIHsKPiAgCQlzcGluX2xvY2so JmNoYW4tPmxvY2spOwo+ICAJCXhpbGlueF9kbWFfY29tcGxldGVfZGVzY3JpcHRvcihjaGFuKTsK PiAgCQljaGFuLT5pZGxlID0gdHJ1ZTsKPiAtLSAKPiAxLjcuMQo+Cg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752469AbeDKJHh (ORCPT ); Wed, 11 Apr 2018 05:07:37 -0400 Received: from mga18.intel.com ([134.134.136.126]:20098 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751758AbeDKJHf (ORCPT ); Wed, 11 Apr 2018 05:07:35 -0400 X-Amp-Result: UNSCANNABLE X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,435,1517904000"; d="scan'208";a="32509798" Date: Wed, 11 Apr 2018 14:41:59 +0530 From: Vinod Koul To: Radhey Shyam Pandey Cc: dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, radheys@xilinx.com, lars@metafoo.de, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RFC 5/6] dmaengine: xilinx_dma: Program interrupt delay timeout Message-ID: <20180411091159.GA6014@localhost> References: <1522665546-10035-1-git-send-email-radheys@xilinx.com> <1522665546-10035-6-git-send-email-radheys@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1522665546-10035-6-git-send-email-radheys@xilinx.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Apr 02, 2018 at 04:09:05PM +0530, Radhey Shyam Pandey wrote: > Program IRQDelay for AXI DMA. The interrupt timeout mechanism causes > the DMA engine to generate an interrupt after the delay time period > has expired. It enables dmaengine to respond in real-time even though > interrupt coalescing is configured. again you are doing this only for axieth_connected, why is that? > > Signed-off-by: Radhey Shyam Pandey > --- > drivers/dma/xilinx/xilinx_dma.c | 16 ++++++++++++++-- > 1 files changed, 14 insertions(+), 2 deletions(-) > > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c > index 518465e..ab8f1b0 100644 > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -161,8 +161,12 @@ > /* AXI DMA Specific Masks/Bit fields */ > #define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) > #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) > +#define XILINX_DMA_CR_DELAY_MAX GENMASK(31, 24) > #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) > #define XILINX_DMA_CR_COALESCE_SHIFT 16 > +#define XILINX_DMA_CR_DELAY_SHIFT 24 > +#define XILINX_DMA_CR_WAITBOUND_DFT 254 > + > #define XILINX_DMA_BD_SOP BIT(27) > #define XILINX_DMA_BD_EOP BIT(26) > #define XILINX_DMA_COALESCE_MAX 255 > @@ -1294,6 +1298,12 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) > reg &= ~XILINX_DMA_CR_COALESCE_MAX; > reg |= chan->desc_pendingcount << > XILINX_DMA_CR_COALESCE_SHIFT; > + > + if (chan->xdev->has_axieth_connected) { > + reg &= ~XILINX_DMA_CR_DELAY_MAX; > + reg |= XILINX_DMA_CR_WAITBOUND_DFT << > + XILINX_DMA_CR_DELAY_SHIFT; > + } > dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); > } > > @@ -1508,7 +1518,8 @@ static irqreturn_t xilinx_dma_irq_handler(int irq, void *data) > } > } > > - if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) { > + if (!chan->xdev->has_axieth_connected && (status & > + XILINX_DMA_DMASR_DLY_CNT_IRQ)) { > /* > * Device takes too long to do the transfer when user requires > * responsiveness. > @@ -1516,7 +1527,8 @@ static irqreturn_t xilinx_dma_irq_handler(int irq, void *data) > dev_dbg(chan->dev, "Inter-packet latency too long\n"); > } > > - if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) { > + if (status & (XILINX_DMA_DMASR_FRM_CNT_IRQ | > + XILINX_DMA_DMASR_DLY_CNT_IRQ)) { > spin_lock(&chan->lock); > xilinx_dma_complete_descriptor(chan); > chan->idle = true; > -- > 1.7.1 > -- ~Vinod From mboxrd@z Thu Jan 1 00:00:00 1970 From: vinod.koul@intel.com (Vinod Koul) Date: Wed, 11 Apr 2018 14:41:59 +0530 Subject: [RFC 5/6] dmaengine: xilinx_dma: Program interrupt delay timeout In-Reply-To: <1522665546-10035-6-git-send-email-radheys@xilinx.com> References: <1522665546-10035-1-git-send-email-radheys@xilinx.com> <1522665546-10035-6-git-send-email-radheys@xilinx.com> Message-ID: <20180411091159.GA6014@localhost> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Apr 02, 2018 at 04:09:05PM +0530, Radhey Shyam Pandey wrote: > Program IRQDelay for AXI DMA. The interrupt timeout mechanism causes > the DMA engine to generate an interrupt after the delay time period > has expired. It enables dmaengine to respond in real-time even though > interrupt coalescing is configured. again you are doing this only for axieth_connected, why is that? > > Signed-off-by: Radhey Shyam Pandey > --- > drivers/dma/xilinx/xilinx_dma.c | 16 ++++++++++++++-- > 1 files changed, 14 insertions(+), 2 deletions(-) > > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c > index 518465e..ab8f1b0 100644 > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -161,8 +161,12 @@ > /* AXI DMA Specific Masks/Bit fields */ > #define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) > #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) > +#define XILINX_DMA_CR_DELAY_MAX GENMASK(31, 24) > #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) > #define XILINX_DMA_CR_COALESCE_SHIFT 16 > +#define XILINX_DMA_CR_DELAY_SHIFT 24 > +#define XILINX_DMA_CR_WAITBOUND_DFT 254 > + > #define XILINX_DMA_BD_SOP BIT(27) > #define XILINX_DMA_BD_EOP BIT(26) > #define XILINX_DMA_COALESCE_MAX 255 > @@ -1294,6 +1298,12 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) > reg &= ~XILINX_DMA_CR_COALESCE_MAX; > reg |= chan->desc_pendingcount << > XILINX_DMA_CR_COALESCE_SHIFT; > + > + if (chan->xdev->has_axieth_connected) { > + reg &= ~XILINX_DMA_CR_DELAY_MAX; > + reg |= XILINX_DMA_CR_WAITBOUND_DFT << > + XILINX_DMA_CR_DELAY_SHIFT; > + } > dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); > } > > @@ -1508,7 +1518,8 @@ static irqreturn_t xilinx_dma_irq_handler(int irq, void *data) > } > } > > - if (status & XILINX_DMA_DMASR_DLY_CNT_IRQ) { > + if (!chan->xdev->has_axieth_connected && (status & > + XILINX_DMA_DMASR_DLY_CNT_IRQ)) { > /* > * Device takes too long to do the transfer when user requires > * responsiveness. > @@ -1516,7 +1527,8 @@ static irqreturn_t xilinx_dma_irq_handler(int irq, void *data) > dev_dbg(chan->dev, "Inter-packet latency too long\n"); > } > > - if (status & XILINX_DMA_DMASR_FRM_CNT_IRQ) { > + if (status & (XILINX_DMA_DMASR_FRM_CNT_IRQ | > + XILINX_DMA_DMASR_DLY_CNT_IRQ)) { > spin_lock(&chan->lock); > xilinx_dma_complete_descriptor(chan); > chan->idle = true; > -- > 1.7.1 > -- ~Vinod