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* [PATCH] drm/i915/selftests: Wait for idle between idle resets as well
@ 2018-04-11 12:03 Chris Wilson
  2018-04-11 13:08 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
                   ` (4 more replies)
  0 siblings, 5 replies; 7+ messages in thread
From: Chris Wilson @ 2018-04-11 12:03 UTC (permalink / raw)
  To: intel-gfx

Even though we weren't injecting guilty requests to be reset, we could
still fall over the issue of resetting the same request too fast -- where
the GPU refuses to start again. (Although it is interesting to note that
reloading the driver is sufficient, suggesting that we could recover if
we delayed the setup after reset?) Continue to paper over the problem by
adding a small delay by waiting for the engine to idle between tests,
and ensure that the engines are idle before starting the idle tests.

References: 028666793a02 ("drm/i915/selftests: Avoid repeatedly harming the same innocent context")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 .../gpu/drm/i915/selftests/intel_hangcheck.c  | 48 ++++++++++++++++++-
 1 file changed, 47 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index 24f913f26a7b..7e23e6a6719c 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -454,6 +454,11 @@ static int igt_global_reset(void *arg)
 	return err;
 }
 
+static bool wait_for_idle(struct intel_engine_cs *engine)
+{
+	return wait_for(intel_engine_is_idle(engine), 50) == 0;
+}
+
 static int __igt_reset_engine(struct drm_i915_private *i915, bool active)
 {
 	struct intel_engine_cs *engine;
@@ -481,6 +486,13 @@ static int __igt_reset_engine(struct drm_i915_private *i915, bool active)
 		if (active && !intel_engine_can_store_dword(engine))
 			continue;
 
+		if (!wait_for_idle(engine)) {
+			pr_err("%s failed to idle before reset\n",
+			       engine->name);
+			err = -EIO;
+			break;
+		}
+
 		reset_count = i915_reset_count(&i915->gpu_error);
 		reset_engine_count = i915_reset_engine_count(&i915->gpu_error,
 							     engine);
@@ -542,6 +554,19 @@ static int __igt_reset_engine(struct drm_i915_private *i915, bool active)
 				err = -EINVAL;
 				break;
 			}
+
+			if (!wait_for_idle(engine)) {
+				struct drm_printer p =
+					drm_info_printer(i915->drm.dev);
+
+				pr_err("%s failed to idle after reset\n",
+				       engine->name);
+				intel_engine_dump(engine, &p,
+						  "%s\n", engine->name);
+
+				err = -EIO;
+				break;
+			}
 		} while (time_before(jiffies, end_time));
 		clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
 
@@ -696,6 +721,13 @@ static int __igt_reset_engines(struct drm_i915_private *i915,
 		    !intel_engine_can_store_dword(engine))
 			continue;
 
+		if (!wait_for_idle(engine)) {
+			pr_err("i915_reset_engine(%s:%s): failed to idle before reset\n",
+			       engine->name, test_name);
+			err = -EIO;
+			break;
+		}
+
 		memset(threads, 0, sizeof(threads));
 		for_each_engine(other, i915, tmp) {
 			struct task_struct *tsk;
@@ -772,6 +804,20 @@ static int __igt_reset_engines(struct drm_i915_private *i915,
 				i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
 				i915_request_put(rq);
 			}
+
+			if (!(flags & TEST_SELF) && !wait_for_idle(engine)) {
+				struct drm_printer p =
+					drm_info_printer(i915->drm.dev);
+
+				pr_err("i915_reset_engine(%s:%s):"
+				       " failed to idle after reset\n",
+				       engine->name, test_name);
+				intel_engine_dump(engine, &p,
+						  "%s\n", engine->name);
+
+				err = -EIO;
+				break;
+			}
 		} while (time_before(jiffies, end_time));
 		clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
 		pr_info("i915_reset_engine(%s:%s): %lu resets\n",
@@ -981,7 +1027,7 @@ static int wait_for_others(struct drm_i915_private *i915,
 		if (engine == exclude)
 			continue;
 
-		if (wait_for(intel_engine_is_idle(engine), 10))
+		if (!wait_for_idle(engine))
 			return -EIO;
 	}
 
-- 
2.17.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Wait for idle between idle resets as well
  2018-04-11 12:03 [PATCH] drm/i915/selftests: Wait for idle between idle resets as well Chris Wilson
@ 2018-04-11 13:08 ` Patchwork
  2018-04-11 13:24 ` ✓ Fi.CI.BAT: success " Patchwork
                   ` (3 subsequent siblings)
  4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2018-04-11 13:08 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/selftests: Wait for idle between idle resets as well
URL   : https://patchwork.freedesktop.org/series/41543/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b63ecede2893 drm/i915/selftests: Wait for idle between idle resets as well
-:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#17: 
References: 028666793a02 ("drm/i915/selftests: Avoid repeatedly harming the same innocent context")

-:17: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 028666793a02 ("drm/i915/selftests: Avoid repeatedly harming the same innocent context")'
#17: 
References: 028666793a02 ("drm/i915/selftests: Avoid repeatedly harming the same innocent context")

total: 1 errors, 1 warnings, 0 checks, 84 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* ✓ Fi.CI.BAT: success for drm/i915/selftests: Wait for idle between idle resets as well
  2018-04-11 12:03 [PATCH] drm/i915/selftests: Wait for idle between idle resets as well Chris Wilson
  2018-04-11 13:08 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2018-04-11 13:24 ` Patchwork
  2018-04-11 16:18 ` ✗ Fi.CI.IGT: failure " Patchwork
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2018-04-11 13:24 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/selftests: Wait for idle between idle resets as well
URL   : https://patchwork.freedesktop.org/series/41543/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4045 -> Patchwork_8667 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_8667 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8667, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8667/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8667:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_gttfill@basic:
      fi-pnv-d510:        PASS -> SKIP

    igt@kms_force_connector_basic@prune-stale-modes:
      fi-snb-2520m:       PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_8667 that come from known issues:

  === IGT changes ===

    ==== Possible fixes ====

    igt@gem_mmap_gtt@basic-small-bo-tiledx:
      fi-gdg-551:         FAIL (fdo#102575) -> PASS

    igt@prime_vgem@basic-fence-flip:
      fi-pnv-d510:        FAIL (fdo#104008) -> PASS

    
  fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008


== Participating hosts (35 -> 32) ==

  Missing    (3): fi-ilk-m540 fi-cnl-y3 fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4045 -> Patchwork_8667

  CI_DRM_4045: f736eddc7f0ba0eb82a43adc674d7eb2523e6de4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4422: a914075d55dd089095121906bf4c3e825a3cecf2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8667: b63ecede2893ced259b45ae773c61379c8842d58 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4422: 45e115f293fd6acc0c9647cf2d3b76be78819ba5 @ git://anongit.freedesktop.org/piglit


== Linux commits ==

b63ecede2893 drm/i915/selftests: Wait for idle between idle resets as well

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8667/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* ✗ Fi.CI.IGT: failure for drm/i915/selftests: Wait for idle between idle resets as well
  2018-04-11 12:03 [PATCH] drm/i915/selftests: Wait for idle between idle resets as well Chris Wilson
  2018-04-11 13:08 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
  2018-04-11 13:24 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-04-11 16:18 ` Patchwork
  2018-04-26 10:08 ` [PATCH] " Chris Wilson
  2018-04-26 16:21 ` Michał Winiarski
  4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2018-04-11 16:18 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/selftests: Wait for idle between idle resets as well
URL   : https://patchwork.freedesktop.org/series/41543/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4045_full -> Patchwork_8667_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_8667_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_8667_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8667/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_8667_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
      shard-kbl:          PASS -> FAIL

    igt@kms_atomic_transition@2x-modeset-transitions:
      shard-hsw:          PASS -> DMESG-FAIL

    
    ==== Warnings ====

    igt@pm_rc6_residency@rc6-accuracy:
      shard-kbl:          SKIP -> PASS +1
      shard-snb:          PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_8667_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_flip@plain-flip-ts-check:
      shard-hsw:          PASS -> FAIL (fdo#100368) +1

    igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
      shard-kbl:          PASS -> DMESG-WARN (fdo#103558) +5

    igt@kms_flip@wf_vblank-ts-check-interruptible:
      shard-hsw:          PASS -> FAIL (fdo#103928)

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-mmap-cpu:
      shard-apl:          PASS -> DMESG-FAIL (fdo#103167)

    igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
      shard-kbl:          PASS -> FAIL (fdo#101623)

    igt@kms_plane@plane-position-hole-dpms-pipe-a-planes:
      shard-hsw:          PASS -> DMESG-WARN (fdo#102614)

    igt@kms_setmode@basic:
      shard-kbl:          PASS -> FAIL (fdo#99912)

    igt@perf@polling:
      shard-hsw:          PASS -> FAIL (fdo#102252)

    igt@perf_pmu@busy-accuracy-50-vecs0:
      shard-kbl:          PASS -> FAIL (fdo#105157)

    
    ==== Possible fixes ====

    igt@kms_cursor_crc@cursor-128x42-sliding:
      shard-kbl:          DMESG-WARN (fdo#103558) -> PASS +9

    igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
      shard-hsw:          FAIL (fdo#102887) -> PASS

    igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
      shard-hsw:          FAIL (fdo#103928) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#105157 https://bugs.freedesktop.org/show_bug.cgi?id=105157
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (6 -> 4) ==

  Missing    (2): shard-glk shard-glkb 


== Build changes ==

    * Linux: CI_DRM_4045 -> Patchwork_8667

  CI_DRM_4045: f736eddc7f0ba0eb82a43adc674d7eb2523e6de4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4422: a914075d55dd089095121906bf4c3e825a3cecf2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_8667: b63ecede2893ced259b45ae773c61379c8842d58 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4422: 45e115f293fd6acc0c9647cf2d3b76be78819ba5 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8667/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] drm/i915/selftests: Wait for idle between idle resets as well
  2018-04-11 12:03 [PATCH] drm/i915/selftests: Wait for idle between idle resets as well Chris Wilson
                   ` (2 preceding siblings ...)
  2018-04-11 16:18 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-04-26 10:08 ` Chris Wilson
  2018-04-26 16:21 ` Michał Winiarski
  4 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2018-04-26 10:08 UTC (permalink / raw)
  To: intel-gfx; +Cc: Mika

Quoting Chris Wilson (2018-04-11 13:03:46)
> Even though we weren't injecting guilty requests to be reset, we could
> still fall over the issue of resetting the same request too fast -- where
> the GPU refuses to start again. (Although it is interesting to note that
> reloading the driver is sufficient, suggesting that we could recover if
> we delayed the setup after reset?) Continue to paper over the problem by
> adding a small delay by waiting for the engine to idle between tests,
> and ensure that the engines are idle before starting the idle tests.
> 
> References: 028666793a02 ("drm/i915/selftests: Avoid repeatedly harming the same innocent context")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Ping?

> ---
>  .../gpu/drm/i915/selftests/intel_hangcheck.c  | 48 ++++++++++++++++++-
>  1 file changed, 47 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> index 24f913f26a7b..7e23e6a6719c 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> @@ -454,6 +454,11 @@ static int igt_global_reset(void *arg)
>         return err;
>  }
>  
> +static bool wait_for_idle(struct intel_engine_cs *engine)
> +{
> +       return wait_for(intel_engine_is_idle(engine), 50) == 0;
> +}
> +
>  static int __igt_reset_engine(struct drm_i915_private *i915, bool active)
>  {
>         struct intel_engine_cs *engine;
> @@ -481,6 +486,13 @@ static int __igt_reset_engine(struct drm_i915_private *i915, bool active)
>                 if (active && !intel_engine_can_store_dword(engine))
>                         continue;
>  
> +               if (!wait_for_idle(engine)) {
> +                       pr_err("%s failed to idle before reset\n",
> +                              engine->name);
> +                       err = -EIO;
> +                       break;
> +               }
> +
>                 reset_count = i915_reset_count(&i915->gpu_error);
>                 reset_engine_count = i915_reset_engine_count(&i915->gpu_error,
>                                                              engine);
> @@ -542,6 +554,19 @@ static int __igt_reset_engine(struct drm_i915_private *i915, bool active)
>                                 err = -EINVAL;
>                                 break;
>                         }
> +
> +                       if (!wait_for_idle(engine)) {
> +                               struct drm_printer p =
> +                                       drm_info_printer(i915->drm.dev);
> +
> +                               pr_err("%s failed to idle after reset\n",
> +                                      engine->name);
> +                               intel_engine_dump(engine, &p,
> +                                                 "%s\n", engine->name);
> +
> +                               err = -EIO;
> +                               break;
> +                       }
>                 } while (time_before(jiffies, end_time));
>                 clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
>  
> @@ -696,6 +721,13 @@ static int __igt_reset_engines(struct drm_i915_private *i915,
>                     !intel_engine_can_store_dword(engine))
>                         continue;
>  
> +               if (!wait_for_idle(engine)) {
> +                       pr_err("i915_reset_engine(%s:%s): failed to idle before reset\n",
> +                              engine->name, test_name);
> +                       err = -EIO;
> +                       break;
> +               }
> +
>                 memset(threads, 0, sizeof(threads));
>                 for_each_engine(other, i915, tmp) {
>                         struct task_struct *tsk;
> @@ -772,6 +804,20 @@ static int __igt_reset_engines(struct drm_i915_private *i915,
>                                 i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
>                                 i915_request_put(rq);
>                         }
> +
> +                       if (!(flags & TEST_SELF) && !wait_for_idle(engine)) {
> +                               struct drm_printer p =
> +                                       drm_info_printer(i915->drm.dev);
> +
> +                               pr_err("i915_reset_engine(%s:%s):"
> +                                      " failed to idle after reset\n",
> +                                      engine->name, test_name);
> +                               intel_engine_dump(engine, &p,
> +                                                 "%s\n", engine->name);
> +
> +                               err = -EIO;
> +                               break;
> +                       }
>                 } while (time_before(jiffies, end_time));
>                 clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
>                 pr_info("i915_reset_engine(%s:%s): %lu resets\n",
> @@ -981,7 +1027,7 @@ static int wait_for_others(struct drm_i915_private *i915,
>                 if (engine == exclude)
>                         continue;
>  
> -               if (wait_for(intel_engine_is_idle(engine), 10))
> +               if (!wait_for_idle(engine))
>                         return -EIO;
>         }
>  
> -- 
> 2.17.0
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] drm/i915/selftests: Wait for idle between idle resets as well
  2018-04-11 12:03 [PATCH] drm/i915/selftests: Wait for idle between idle resets as well Chris Wilson
                   ` (3 preceding siblings ...)
  2018-04-26 10:08 ` [PATCH] " Chris Wilson
@ 2018-04-26 16:21 ` Michał Winiarski
  2018-04-26 16:34   ` Chris Wilson
  4 siblings, 1 reply; 7+ messages in thread
From: Michał Winiarski @ 2018-04-26 16:21 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

On Wed, Apr 11, 2018 at 01:03:46PM +0100, Chris Wilson wrote:
> Even though we weren't injecting guilty requests to be reset, we could
> still fall over the issue of resetting the same request too fast -- where
> the GPU refuses to start again. (Although it is interesting to note that
> reloading the driver is sufficient, suggesting that we could recover if
> we delayed the setup after reset?) Continue to paper over the problem by
> adding a small delay by waiting for the engine to idle between tests,
> and ensure that the engines are idle before starting the idle tests.
> 
> References: 028666793a02 ("drm/i915/selftests: Avoid repeatedly harming the same innocent context")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Michel Thierry <michel.thierry@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  .../gpu/drm/i915/selftests/intel_hangcheck.c  | 48 ++++++++++++++++++-
>  1 file changed, 47 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> index 24f913f26a7b..7e23e6a6719c 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> @@ -454,6 +454,11 @@ static int igt_global_reset(void *arg)
>  	return err;
>  }
>  

#define IGT_IDLE_TIMEOUT 50 ?
It should even fit within a line.

With or without that:

Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>

-Michał

> +static bool wait_for_idle(struct intel_engine_cs *engine)
> +{
> +	return wait_for(intel_engine_is_idle(engine), 50) == 0;
> +}
> +
>  static int __igt_reset_engine(struct drm_i915_private *i915, bool active)
>  {
>  	struct intel_engine_cs *engine;
> @@ -481,6 +486,13 @@ static int __igt_reset_engine(struct drm_i915_private *i915, bool active)
>  		if (active && !intel_engine_can_store_dword(engine))
>  			continue;
>  
> +		if (!wait_for_idle(engine)) {
> +			pr_err("%s failed to idle before reset\n",
> +			       engine->name);
> +			err = -EIO;
> +			break;
> +		}
> +
>  		reset_count = i915_reset_count(&i915->gpu_error);
>  		reset_engine_count = i915_reset_engine_count(&i915->gpu_error,
>  							     engine);
> @@ -542,6 +554,19 @@ static int __igt_reset_engine(struct drm_i915_private *i915, bool active)
>  				err = -EINVAL;
>  				break;
>  			}
> +
> +			if (!wait_for_idle(engine)) {
> +				struct drm_printer p =
> +					drm_info_printer(i915->drm.dev);
> +
> +				pr_err("%s failed to idle after reset\n",
> +				       engine->name);
> +				intel_engine_dump(engine, &p,
> +						  "%s\n", engine->name);
> +
> +				err = -EIO;
> +				break;
> +			}
>  		} while (time_before(jiffies, end_time));
>  		clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
>  
> @@ -696,6 +721,13 @@ static int __igt_reset_engines(struct drm_i915_private *i915,
>  		    !intel_engine_can_store_dword(engine))
>  			continue;
>  
> +		if (!wait_for_idle(engine)) {
> +			pr_err("i915_reset_engine(%s:%s): failed to idle before reset\n",
> +			       engine->name, test_name);
> +			err = -EIO;
> +			break;
> +		}
> +
>  		memset(threads, 0, sizeof(threads));
>  		for_each_engine(other, i915, tmp) {
>  			struct task_struct *tsk;
> @@ -772,6 +804,20 @@ static int __igt_reset_engines(struct drm_i915_private *i915,
>  				i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT);
>  				i915_request_put(rq);
>  			}
> +
> +			if (!(flags & TEST_SELF) && !wait_for_idle(engine)) {
> +				struct drm_printer p =
> +					drm_info_printer(i915->drm.dev);
> +
> +				pr_err("i915_reset_engine(%s:%s):"
> +				       " failed to idle after reset\n",
> +				       engine->name, test_name);
> +				intel_engine_dump(engine, &p,
> +						  "%s\n", engine->name);
> +
> +				err = -EIO;
> +				break;
> +			}
>  		} while (time_before(jiffies, end_time));
>  		clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
>  		pr_info("i915_reset_engine(%s:%s): %lu resets\n",
> @@ -981,7 +1027,7 @@ static int wait_for_others(struct drm_i915_private *i915,
>  		if (engine == exclude)
>  			continue;
>  
> -		if (wait_for(intel_engine_is_idle(engine), 10))
> +		if (!wait_for_idle(engine))
>  			return -EIO;
>  	}
>  
> -- 
> 2.17.0
> 
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^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] drm/i915/selftests: Wait for idle between idle resets as well
  2018-04-26 16:21 ` Michał Winiarski
@ 2018-04-26 16:34   ` Chris Wilson
  0 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2018-04-26 16:34 UTC (permalink / raw)
  To: Michał Winiarski; +Cc: intel-gfx

Quoting Michał Winiarski (2018-04-26 17:21:39)
> On Wed, Apr 11, 2018 at 01:03:46PM +0100, Chris Wilson wrote:
> > Even though we weren't injecting guilty requests to be reset, we could
> > still fall over the issue of resetting the same request too fast -- where
> > the GPU refuses to start again. (Although it is interesting to note that
> > reloading the driver is sufficient, suggesting that we could recover if
> > we delayed the setup after reset?) Continue to paper over the problem by
> > adding a small delay by waiting for the engine to idle between tests,
> > and ensure that the engines are idle before starting the idle tests.
> > 
> > References: 028666793a02 ("drm/i915/selftests: Avoid repeatedly harming the same innocent context")
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > Cc: Michał Winiarski <michal.winiarski@intel.com>
> > Cc: Michel Thierry <michel.thierry@intel.com>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> >  .../gpu/drm/i915/selftests/intel_hangcheck.c  | 48 ++++++++++++++++++-
> >  1 file changed, 47 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> > index 24f913f26a7b..7e23e6a6719c 100644
> > --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> > +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> > @@ -454,6 +454,11 @@ static int igt_global_reset(void *arg)
> >       return err;
> >  }
> >  
> 
> #define IGT_IDLE_TIMEOUT 50 ?
> It should even fit within a line.
> 
> With or without that:
> 
> Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>

Done. Thanks for the review, pushed.
-Chris
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^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2018-04-26 16:34 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-04-11 12:03 [PATCH] drm/i915/selftests: Wait for idle between idle resets as well Chris Wilson
2018-04-11 13:08 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2018-04-11 13:24 ` ✓ Fi.CI.BAT: success " Patchwork
2018-04-11 16:18 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-04-26 10:08 ` [PATCH] " Chris Wilson
2018-04-26 16:21 ` Michał Winiarski
2018-04-26 16:34   ` Chris Wilson

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